BitOps, Core, CoreClasses, CoreCreate, CoreProperties, Ports, Rosemary, RosemaryUser, TamarinPorts, TamarinOpsUtils, TamarinBlocks, Rope;
EuLu:
CEDAR
PROGRAM
IMPORTS CoreClasses, CoreCreate, Ports, Rosemary, TamarinPorts, TamarinBlocks, TamarinOpsUtils
= BEGIN
d1, d2, r, luEuop, selLu, Vdd, Gnd: NAT ← LAST[NAT];
luCt: Core.CellType;
luPorts: Ports.Port;
busBits: NAT ← 32;
euopBits: NAT ← 4;
Create:
PUBLIC
PROC
RETURNS [ct: Core.CellType] = {
-- Cell which this is replacing must have the Object satellite: cI𡤎uLu.Create[]
luCt ← CoreClasses.CreateUnspecified[
public: CoreCreate.WireList[
LIST[
CoreCreate.Seq["D1", busBits],
CoreCreate.Seq["D2", busBits],
CoreCreate.Seq["R", busBits],
CoreCreate.Seq["LUEuop", euopBits],
CoreCreate.Seq["SelLU", 2],
"Vdd", "Gnd"],
"LU", NIL],
name: luName
];
ct ← luCt;
InitPorts[ct];
};
LuInit: Rosemary.InitProc = {
--PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY ← NIL]--
InitPorts[cellType];
RETURN[NIL];
};
InitPortIndexes:
PROC [ct: Core.CellType] = {
[d1, d2, r, luEuop, selLu, Vdd, Gnd] ← Ports.PortIndexes[ct.public, "D1", "D2", "R", "LUEuop", "SelLU", "Vdd", "Gnd"];
};
InitPorts:
PROC [ct: Core.CellType] = {
InitPortIndexes[ct];
[] ← Ports.InitPorts[ct, ls, none, "D1"];
[] ← Ports.InitPorts[ct, ls, none, "D2"];
[] ← Ports.InitPorts[ct, ls, drive, "R"];
[] ← Ports.InitPorts[ct, ls, none, "LUEuop"];
[] ← Ports.InitPorts[ct, ls, none, "SelLU"];
[] ← Rosemary.SetFixedWire[ct.public[Vdd], H];
[] ← Rosemary.SetFixedWire[ct.public[Gnd], L];
};
LuEvalSimple: Rosemary.EvalProc = {
PROC [p: Ports.Port, stateAny: REF ANY]--
luPorts ← p;
IF TamarinPorts.PortToCard[p, selLu] = 3
THEN
TamarinPorts.SetP[
p,
r,
TamarinOpsUtils.WordToCard[
TamarinBlocks.LogicalUnit[
TamarinPorts.PortToCard[p, luEuop],
TamarinPorts.PortToTamWord[p, d1],
TamarinPorts.PortToTamWord[p, d2]
]
]
];
luPorts ← p;
};
luName: Rope.ROPE = Rosemary.Register[roseClassName: "LU", init: LuInit, evalSimple: LuEvalSimple];
END.