TamarinOps.mesa
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
by Ross January 26, 1987 3:05:03 pm PST
Last Edited by: Ross February 3, 1987 11:55:42 am PST
This interface consists entirely of type definitions for the architectural data structures for
the Tamarin Lisp processor. Much of this is borrowed from
[Indigo]<Dragon>DragOps>DragOpsCross.mesa with many thanks to Russ.
Basic Types and Associated Values
numFrames: NAT = 6;
numWordsPerFrame: NAT = 48;
Word:
TYPE =
PACKED
ARRAY FiveBitIndex
OF
BOOL;
TagZerosWord: TaggedWord = [ZerosByte, LOOPHOLE[LONG[0]]];
ZerosWord: Word =
LOOPHOLE[
LONG[0]];
We would like to use ALL[FALSE], but the compiler is really stupid
OnesWord: Word =
LOOPHOLE[
LONG[-1]];
We would like to use ALL[TRUE], but the compiler is really stupid
wordsPerPage: CARDINAL = 1024;
bytesPerWord: CARDINAL = 4;
charsPerWord: CARDINAL = 4;
bitsPerByte: CARDINAL = 8;
bitsPerCharacter: CARDINAL = 8;
bitsPerWord: CARDINAL = bitsPerByte*bytesPerWord;
bytesPerPage: CARDINAL = wordsPerPage*bytesPerWord;
logWordsPerPage: CARDINAL = 10; -- LogBase2[wordsPerPage]
logBitsPerByte: CARDINAL = 3; --LogBase2[bitsPerByte]
logBitsPerChar: CARDINAL = 3; --LogBase2[bitsPerCharacter]
logBytesPerWord: CARDINAL = 1; --LogBase2[bytesPerWord]
logCharsPerWord: CARDINAL = 1; --LogBase2[bytesPerWord]
logBitsPerWord: CARDINAL = logBitsPerByte + logBytesPerWord;
logBytesPerPage: CARDINAL = logBytesPerWord + logWordsPerPage;
PageCount:
TYPE =
INT;
actually, [0..maxPagesInVM]; intended for use by VM
PageNumber:
TYPE =
INT;
actually, [0..maxPagesInVM); intended for use by VM
maxPagesInVM: PageCount =
LONG[4]*
LONG[1024]*
LONG[1024];
22-bit page index
SixBitIndex: TYPE = [0..64);
SevenBitIndex: TYPE = [0..128);
FiveBitIndex: TYPE = [0..32);
TwoWords: TYPE = ARRAY [0..1] OF Word;
FourBitIndex: TYPE = [0..16);
Half:
TYPE =
PACKED
ARRAY FourBitIndex
OF
BOOL;
ZerosHalf: Half = LOOPHOLE[0];
OnesHalf: Half = LOOPHOLE[-1];
ThreeBitIndex: TYPE = [0..7];
FourHalves: TYPE = ARRAY [0..3] OF Half;
TwoHalves: TYPE = ARRAY [0..1] OF Half;
Byte:
TYPE =
PACKED
ARRAY ThreeBitIndex
OF
BOOL;
ZerosByte: Byte = LOOPHOLE[0];
OnesByte: Byte = LOOPHOLE[377B];
EightBytes: TYPE = PACKED ARRAY [0..7] OF Byte;
FourBytes:
TYPE =
PACKED
ARRAY ByteIndex
OF Byte;
ByteIndex: TYPE = [0..bytesPerWord);
BytesPerWord: NAT = 4;
TwoBytes: TYPE = PACKED ARRAY [0..1] OF Byte;
Comparison:
TYPE =
MACHINE
DEPENDENT {less(0), equal(1), greater(2)};
This type is the type to be returned from comparison operations.
ByteAddress:
TYPE =
RECORD [Word];
To be used to denote byte addresses, when the difference between bytes addresses and other words needs to be indicated.
WordAddress:
TYPE =
RECORD [Word];
To be used to denote word addresses, when the difference between addresses and other words needs to be indicated.
TaggedWord:
TYPE =
RECORD [
tag: Tag,
data: Word];
Bus:
TYPE =
RECORD [
name: Rope.ROPE,
isDriven: BOOL,
tw: TaggedWord];
Processor Register Numbers (tentative)
These assignments are to be used with the LIP, and SIP instructions. We use the ProcessorRegister declarations for both IFU and EU parts.
There are actually more assignments than are accessible through these instructions. These are marked by (NA), which indicates that the decode is reserved for the register, but that the data paths to allow the register to be used are not present.
StackFrame:
TYPE =
MACHINE
DEPENDENT {
frameHead (0), -- beginning of Stack Frame
pvarExt (7), -- pvar overflow (extension) slot
varsEnd (15), -- end of vars space
stackPtr (16), -- Stack ptr. word
pc (17), -- PC
nameTable (18), -- name table entry
funHeader (19), -- Function Header entry
cLink (20), -- clink entry
stackStart (21), -- start of additional vars or stack
stackEnd (numWordsPerFrame)
};
ProcessorRegister:
TYPE =
MACHINE
DEPENDENT {
Note: this numbering reflects the actual implementation of the decoding logic
cxtZero (0), -- starting address for context 0 (global)
cxtOne (64), -- starting address for context 1
cxtTwo (128), -- starting address for context 2
cxtThree (192), -- starting address for context 3
cxtFour (256), -- starting address for context 4
cxtFive (320), -- starting address for context 5
cxtGlobal (384), -- starting address for global context
lastReg (407), -- last real processor reg
curPC (408), -- last committed pc
nextPC (409)
};
StackedStatusWord:
TYPE =
MACHINE
DEPENDENT RECORD [
version (0: 00..07): [0..255] ← 0,
padBits (0: 08..13): [0..63] ← 0,
userMode (0: 14..14): BOOL ← FALSE, -- TRUE => user, FALSE => kernel
trapsEnabled (0: 15..15): BOOL ← FALSE,
padByte (0: 16..23): [0..255] ← 0,
lBase (0: 24..31): [0..255] ← 0 ]; -- EU local frame base
EuUnits:
TYPE =
MACHINE
DEPENDENT {
NOP (0),
Adder (1),
LU (2),
Shifter (3),
Prior (4),
LdMult (6),
UnLdMult (7)};
LuOp:
TYPE =
MACHINE
DEPENDENT {
tAND (1),
tXOR (6),
tOR (7),
tNOR (8),
tNAND (14)};
AdderOp:
TYPE =
MACHINE
DEPENDENT {
tADD (0),
tADDC (1),
tSUB (8),
tSUBC (9)};