DIRECTORY BitOps, Cabbage, CD, CDCommandOps, CDIO, CDSequencer, CDSequencerExtras, Core, CoreCreate, CoreOps, CoreProperties, FS, IO, List, PW, PWCore, Rope, Route, SinixOps, Sisyph, Tam, TamarinUtil, TerminalIO; TamarinUtilImpl: CEDAR PROGRAM IMPORTS BitOps, Cabbage, CDCommandOps, CDIO, CoreCreate, CoreOps, CoreProperties, FS, IO, List, PW, PWCore, Rope, Route, SinixOps, Sisyph, TerminalIO EXPORTS Tam, TamarinUtil = BEGIN LORA: TYPE = List.LORA; ROPE: TYPE = Rope.ROPE; mask: PUBLIC CD.Design _ NIL; tamMask: CD.Design _ NIL; tamMaskR: CD.Design _ NIL; constList: LORA _ NIL; dpCcList: LORA _ NIL; specRegConstD1List: LORA _ NIL; specRegConstD2List: LORA _ NIL; uCodeList: LORA _ NIL; uCodeRomA, uCodeRomB: PUBLIC ARRAY [0..255] OF Rope.ROPE; BitOnP: PUBLIC PROC [word, pos: NAT] RETURNS [v: BOOLEAN] ={ v _ 1 = BitOps.WShift[word, - pos, 1] }; RopeBitOnP: PUBLIC PROC [word: Rope.ROPE, pos: INT] RETURNS [v: BOOLEAN] = { v _ (IF pos<0 THEN FALSE ELSE (SELECT Rope.Fetch[word, pos] FROM '1 => TRUE, '0, 'X => FALSE, ENDCASE => ERROR)); }; ResetTamarinDefs: PUBLIC PROC = { constList _ NIL; dpCcList _ NIL; specRegConstD1List _ NIL; specRegConstD2List _ NIL; uCodeList _ NIL; }; GetTamarinConstants: PUBLIC PROC RETURNS[res: LORA] = { res _ List.Reverse[constList] }; GetDpCondCodes: PUBLIC PROC RETURNS[res: LORA] = { res _ List.Reverse[dpCcList] }; GetSpecRegConstants: PUBLIC PROC RETURNS[resD1: LORA, resD2: LORA] = { resD1 _ List.Reverse[specRegConstD1List]; resD2 _ List.Reverse[specRegConstD2List] }; GetUCodeContents: PUBLIC PROC RETURNS[res: LORA] = { res _ List.Reverse[uCodeList] }; TamConstant: PUBLIC PROC [atm: ATOM, val: INT] = { const: TamarinUtil.TamConst _ NEW[ TamarinUtil.TamConstRec]; const^ _ [atm, val]; constList _ CONS[ const, constList] }; DpCCode: PUBLIC PROC [index: NAT, d1, d2, nD1, nD, d1XorD2: Rope.ROPE] = { const: TamarinUtil.DpCondCode _ NEW[ TamarinUtil.DpCondCodeRec]; const^ _ [index, d1, d2, nD1, nD, d1XorD2]; dpCcList _ CONS[ const, dpCcList] }; SpecRegConst: PUBLIC PROC [wh, index: NAT, val: Rope.ROPE] = { const: TamarinUtil.SpecRegConstant _ NEW[ TamarinUtil.SpecRegConstRec]; const^ _ [index, val]; IF wh=0 THEN specRegConstD1List _ CONS[ const, specRegConstD1List] ELSE specRegConstD2List _ CONS[ const, specRegConstD2List] }; AddUCode: PUBLIC PROC [aAddr, bAddr: NAT, aeMI, aoMI, beMI, boMI: Rope.ROPE] = { const: TamarinUtil.UCodeWord _ NEW[ TamarinUtil.UCodeWordRec]; const^ _ [0, aAddr, bAddr, aeMI, aoMI, beMI, boMI]; uCodeList _ CONS[ const, uCodeList]; uCodeRomA[aAddr] _ aeMI; uCodeRomA[aAddr+1] _ aoMI; uCodeRomB[bAddr] _ beMI; uCodeRomB[bAddr+1] _ boMI; }; GetUCode: PUBLIC PROC = { stream: IO.STREAM; aindex, bindex: NAT; aeMI, aoMI, beMI, boMI: Rope.ROPE; uCodeList _ NIL; stream _ FS.StreamOpen["TamUCode"]; FOR i: NAT _ 0, i + 1 WHILE (i < 128) AND ~IO.EndOf[stream] DO aindex _ IO.GetInt[stream]; aeMI _ IO.GetTokenRope[stream].token; aoMI _ IO.GetTokenRope[stream].token; bindex _ IO.GetInt[stream]; beMI _ IO.GetTokenRope[stream].token; boMI _ IO.GetTokenRope[stream].token; AddUCode[aindex, bindex, aeMI, aoMI, beMI, boMI]; ENDLOOP; IO.Close[stream]; }; MakeDataBus: PUBLIC PROC [name: ROPE] RETURNS [res: CoreCreate.Wire] = { res _ CoreCreate.WireList[LIST[CoreCreate.Seq["tag", 2], CoreCreate.Seq["data", 32]], name] }; ConvertDataBus: PUBLIC PROC [wire: CoreCreate.Wire] RETURNS [res: CoreCreate.Wire] = { res _ CoreOps.CreateWire[LIST[CoreOps.SubrangeWire[wire, wire.size-2, 2, "tag"], CoreOps.SubrangeWire[wire, 0, wire.size-2, "data"]], CoreOps.GetShortWireName[wire]] }; ConvertDataBusBlock: PUBLIC PROC [wire: CoreCreate.Wire, name: Rope.ROPE _ NIL ] RETURNS [res: CoreCreate.Wire] = { res _ CoreOps.CreateWires[32, (IF name=NIL THEN CoreOps.GetShortWireName[wire] ELSE name)]; FOR block: NAT IN [0..7] DO FOR bit: NAT IN [0..3] DO res[block*4+bit] _ wire[block][bit]; ENDLOOP; ENDLOOP }; ConvertDataBusBlockPermute: PUBLIC PROC [wire: CoreCreate.Wire, name: Rope.ROPE _ NIL] RETURNS [res: CoreCreate.Wire] = { res _ CoreOps.CreateWires[32, (IF name=NIL THEN CoreOps.GetShortWireName[wire] ELSE name)]; FOR block: NAT IN [0..7] DO FOR bit: NAT IN [0..3] DO res[block+bit*8] _ wire[block][bit]; ENDLOOP; ENDLOOP }; DataBusToWire: PUBLIC PROC [wr: CoreCreate.Wire, n: INT] RETURNS [res: CoreCreate.Wire] = { res _ (IF n < 2 THEN wr[0][n] ELSE wr[1][n-2]) }; OpenLayout: PROC [] RETURNS [] = { maskFileName: Rope.ROPE _ "TamarinLayout"; tamMask _ CDIO.ReadDesign[maskFileName, NIL, NIL, NIL]; }; SetMask: PROC [command: CDSequencer.Command] = { tamMask _ command.design }; SetMaskR: PROC [command: CDSequencer.Command] = { tamMaskR _ command.design }; TamGetAttribute: PWCore.AttributesProc = { IF tamMask = NIL THEN { tamMask _ PW.OpenDesign["lp2ExecutionLayout.dale"]; }; CoreProperties.PutCellTypeProp[cellType, $PWCoreSourceDesign, tamMask]; CoreProperties.PutCellTypeProp[cellType, $LichenTransistorTolerances, Rope.Flatten["1.0, 1.0"]]; }; TamGetRAttribute: PWCore.AttributesProc = { IF tamMaskR = NIL THEN { tamMaskR _ PW.OpenDesign["LP2RegFileLayout.dale"]; }; CoreProperties.PutCellTypeProp[cellType, $PWCoreSourceDesign, tamMaskR]; CoreProperties.PutCellTypeProp[cellType, $LichenTransistorTolerances, Rope.Flatten["1.0, 1.0"]]; }; LayoutWithOutCabbageSignals: PUBLIC PWCore.LayoutProc = { TerminalIO.PutF["\nBEGIN: LayoutWithOutCabbageSignals: %g\n", IO.time[]]; obj _ PWCore.Layout[cellType ! Cabbage.Signal => {TerminalIO.PutF["*** Cabbage Signal: %g\n", IO.rope[explanation]]; RESUME}; Route.Signal => {TerminalIO.PutF["*** Route Signal: %g\n", IO.rope[explanation]]; RESUME} ]; TerminalIO.PutF["\nEND: LayoutWithOutCabbageSignals: %g\n", IO.time[]]}; NsExtractAndLayout: PROC [comm: CDSequencer.Command] = { root, cellType: Core.CellType; [root: root, cell: cellType] _ SinixOps.SelectedCellType[comm.design, Sisyph.mode]; IF root=NIL THEN RETURN; -- Extraction ended in error, message already printed TerminalIO.PutF["\nGenerating layout for %g.\n", IO.rope[CoreOps.GetCellTypeName[cellType]]]; [] _ PW.Draw[LayoutWithOutCabbageSignals[cellType]]; }; LayoutAndStore: PROC [comm: CDSequencer.Command] = { root, cellType: Core.CellType; [root: root, cell: cellType] _ SinixOps.SelectedCellType[comm.design, Sisyph.mode]; IF root=NIL THEN RETURN; -- Extraction ended in error, message already printed TerminalIO.PutF["\nGenerating layout for %g.\n", IO.rope[CoreOps.GetCellTypeName[cellType]]]; [] _ PW.Draw[PWCore.Layout[cellType]]; PWCore.Store[cellType] }; CDCommandOps.RegisterWithMenu[ menu: $ProgramMenu, entry: "Extract and Layout - No signals", doc: "Extract and Layout", proc: NsExtractAndLayout, queue: doQueue ]; CDCommandOps.RegisterWithMenu[ menu: $ProgramMenu, entry: "Layout and Store", doc: "Layout and Store", proc: LayoutAndStore, queue: doQueue ]; CDCommandOps.RegisterWithMenu[ menu: $ProgramMenu, entry: "Set Layout", doc: "Sets .mask file for schematic generated layout", proc: SetMask, queue: dontQueue ]; CDCommandOps.RegisterWithMenu[ menu: $ProgramMenu, entry: "Set Layout: Rom", doc: "Sets .mask file for schematic generated layout", proc: SetMaskR, queue: dontQueue ]; [] _ PWCore.RegisterLayoutAtom[ layoutAtom: $TamGet, layoutProc: PWCore.GetLayoutAtomRegistration[$Get].layoutProc, decorateProc: PWCore.GetLayoutAtomRegistration[$Get].decorateProc, attributesProc: TamGetAttribute ]; [] _ PWCore.RegisterLayoutAtom[ layoutAtom: $TamGetAndFlatten, layoutProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].layoutProc, decorateProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].decorateProc, attributesProc: TamGetAttribute ]; [] _ PWCore.RegisterLayoutAtom[ layoutAtom: $TamGetR, layoutProc: PWCore.GetLayoutAtomRegistration[$Get].layoutProc, decorateProc: PWCore.GetLayoutAtomRegistration[$Get].decorateProc, attributesProc: TamGetRAttribute ]; [] _ PWCore.RegisterLayoutAtom[ layoutAtom: $TamGetAndFlattenR, layoutProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].layoutProc, decorateProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].decorateProc, attributesProc: TamGetRAttribute ] END. ΖTamarinUtilImpl.mesa Copyright c 1987 by Xerox Corporation. All rights reserved. Last Edited by: Alan Bell October 28, 1987 10:57:50 am PST Krivacic September 4, 1987 5:31:53 pm PDT stream _ FS.StreamOpen["/Phylum/CTamarin/TamarinRoseSim/TamUCode"]; fileName: Rope.ROPE; fileName _ TerminalIO.RequestRope["Name of Layout File (include full path) > "]; fileName: Rope.ROPE; fileName _ TerminalIO.RequestRope["Name of Rom Layout File (include full path) > "]; [] _ PWCore.RegisterLayoutAtom[ layoutAtom: $TamGet, layoutProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].layoutProc, decorateProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].decorateProc, attributesProc: TamGetAttribute ]; Κ ”˜codešœ™Kšœ Οmœ1™Kšœ%žœ˜GKšœ˜Kš žœžœžœžœžœ˜€—K˜š Ÿœžœžœžœ žœ˜QK˜Kšœžœ˜>Kšœ3˜3Kšœ žœ˜$Kšœ˜Kšœ˜Kšœ˜Kšœ˜Kšœ˜—K˜šŸœž œ˜Kšœžœžœ˜Kšœžœ˜Kšœžœ˜"K˜Kšœ ž˜K™Kšœ žœ8™CKšœ žœ˜#K˜š žœžœ žœ žœžœžœ˜?Kšœ žœ˜Kšœžœ˜%Kšœžœ˜%Kšœ žœ˜Kšœžœ˜%Kšœžœ˜%Kšœ1˜1Kšžœ˜—K˜Kšžœ˜K˜—K˜š Ÿ œžœžœžœžœ˜HKšœžœ@˜^—K˜šŸœžœžœžœ˜VKšœžœ‹˜¨K˜—š Ÿœžœžœ$žœžœžœ˜sKš œžœžœžœ žœ ˜\šžœžœžœž˜šžœžœžœž˜Kšœ$˜$Kšžœ˜—Kšž˜—Kšœ˜K˜—š Ÿœžœžœ$žœžœžœ˜yKš œžœžœžœ žœ ˜\šžœžœžœž˜šžœžœžœž˜Kšœ$˜$Kšžœ˜—Kšž˜—Kšœ˜K˜—š Ÿ œžœžœžœžœ˜[Kšœžœžœ žœ˜1—K˜šŸ œžœžœ˜"Kšœžœ˜*Kš œ žœžœžœžœ˜7Kšœ˜—K˜šŸœžœ#˜0Kšœ˜Kšœ˜K˜—šŸœžœ#˜1Kšœ˜Kšœ˜K˜—šŸœ˜*Kšœžœ™šžœ žœžœ˜KšœP™PKšœ žœ'˜3Kšœ˜—KšœG˜GKšœ`˜`K˜K˜—šŸœ˜+Kšœžœ™šžœ žœžœ˜KšœT™TKšœ žœ%˜2Kšœ˜—KšœH˜HKšœ`˜`K˜—K˜šŸœžœ˜9šœ>žœ ˜Išœ0˜0Kšœ,žœ˜CKšžœ˜—šœ˜šœ*˜*Kšžœžœ˜!—Kšœ<žœ ˜I———šŸœžœ ˜8Jšœ˜JšœS˜SJš žœžœžœžœΟc5˜NJšœ1žœ*˜]Jšœžœ-˜4J˜J˜—šœžœ ˜4Jšœ˜JšœS˜SJš žœžœžœžœ 5˜NJšœ1žœ*˜]Jšœžœ˜&Jšœ˜Jšœ˜J˜—˜K˜K˜)K˜Kšœ˜Kšœ˜K˜K˜—˜K˜K˜K˜Kšœ˜Kšœ˜K˜K˜—˜K˜K˜K˜6K˜Kšœ˜K˜K˜—˜K˜K˜K˜6K˜Kšœ˜K˜—˜K˜—šœ˜Jšœ˜Jšœ?˜?JšœC˜CJšœ˜Jšœ˜—J˜šœ™Jšœ™JšœI™IJšœM™MJšœ™Jšœ™J™—šœ˜Jšœ˜JšœI˜IJšœM˜MJšœ˜Jšœ˜—K˜K˜šœ˜Jšœ˜Jšœ?˜?JšœC˜CJšœ ˜ Jšœ˜—J˜šœ˜Jšœ ˜ JšœI˜IJšœM˜MJšœ ˜ Jšœ˜—J˜Jšžœ˜J˜J˜—…—’,ό