DIRECTORY 
CD, 
CDSequencer,
Core USING [CellType, ROPE],
CoreCreate, 
List,
Sisyph USING [Context, ES], 
Tam,
TamarinUtil,
TilingClass USING [CreateTiling, SchematicsNeighborX, SchematicsNeighborY, 
TileArray, TileArrayRec, TileRec, TileRowRec];

TamarinDataPathImpl: CEDAR PROGRAM
IMPORTS CoreCreate, List, Sisyph, TamarinUtil, TilingClass
EXPORTS Tam = BEGIN

LORA: TYPE = List.LORA;
Wire: TYPE = CoreCreate.Wire;
WR: TYPE = CoreCreate.WR;
lastTile: TilingClass.TileArray _ NIL;


CreateSpecRegTemp:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {

ccWordLength: NAT = 34;

constSel: Wire;

d1Bus: Wire _ CoreCreate.Seq["D1", ccWordLength];
d2Bus: Wire _ CoreCreate.Seq["D2", ccWordLength];
rBus: Wire _ CoreCreate.Seq["R", ccWordLength];
d1res: Wire _ CoreCreate.Seq["d1res", ccWordLength];
d2res: Wire _ CoreCreate.Seq["d2res", ccWordLength];
d1Drive: Wire _ CoreCreate.Seq["d1Drive", 2];
d2Drive: Wire _ CoreCreate.Seq["d2Drive", 2];

specRegTempOne: Core.CellType _ Sisyph.ES["SpecRegTempOne.sch", tamarinCx];

tileArray: TilingClass.TileArray;
tileArray _ NEW[TilingClass.TileArrayRec[1]];
tileArray[0] _ NEW[TilingClass.TileRowRec[ccWordLength]];

FOR bit: NAT IN [0..ccWordLength) DO
tileArray[0][bit] _
NEW[TilingClass.TileRec _ [type: specRegTempOne,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["d1res", d1res[bit]], ["d2res", d2res[bit]], ["D1Sel", "D1Sel"], ["D2Sel", "D2Sel"], ["load", "load"], ["reset", "reset"], ["Clock", "Clock"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;

cellType _ TilingClass.CreateTiling[
name: "SpecRegTemp",
public: CoreCreate.WireList[LIST[constSel, TamarinUtil.ConvertDataBus[d1Bus], TamarinUtil.ConvertDataBus[d2Bus], TamarinUtil.ConvertDataBus[rBus], TamarinUtil.ConvertDataBus[d1res], TamarinUtil.ConvertDataBus[d2res], "D1Sel", "D2Sel", "load", "reset", "Clock", "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};

CreateSpecRegDrive:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {

ccWordLength: NAT = 34;

constSel: Wire;

d1Bus: Wire _ CoreCreate.Seq["D1", ccWordLength];
d2Bus: Wire _ CoreCreate.Seq["D2", ccWordLength];
rBus: Wire _ CoreCreate.Seq["R", ccWordLength];
mux: Wire _ CoreCreate.Seq["mux", ccWordLength];
d1res: Wire _ CoreCreate.Seq["d1res", ccWordLength];
d2res: Wire _ CoreCreate.Seq["d2res", ccWordLength];
d1Drive: Wire _ CoreCreate.Seq["D1Drive", 2];
d2Drive: Wire _ CoreCreate.Seq["D2Drive", 2];

specRegDriveOne: Core.CellType _ Sisyph.ES["SpecRegDriveOne.sch", tamarinCx];

tileArray: TilingClass.TileArray;
tileArray _ NEW[TilingClass.TileArrayRec[1]];
tileArray[0] _ NEW[TilingClass.TileRowRec[ccWordLength]];

FOR bit: NAT IN [0..ccWordLength) DO
tileArray[0][bit] _
NEW[TilingClass.TileRec _ [type: specRegDriveOne,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["d1res", d1res[bit]], ["d2res", d2res[bit]], ["mux", mux[bit]], ["D1MuxDrive", "D1MuxDrive"], ["D2MuxDrive", "D2MuxDrive"], ["D1Drive", d1Drive], ["D2Drive", d2Drive], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;

cellType _ TilingClass.CreateTiling[
name: "SpecRegDrive",
public: CoreCreate.WireList[LIST[constSel, TamarinUtil.ConvertDataBus[d1Bus], TamarinUtil.ConvertDataBus[d2Bus], TamarinUtil.ConvertDataBus[rBus], TamarinUtil.ConvertDataBus[d1res], TamarinUtil.ConvertDataBus[d2res], TamarinUtil.ConvertDataBus[mux], "D1MuxDrive", "D2MuxDrive", d1Drive, d2Drive, "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};

CreateSpecRegConstants:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {

ccWordLength: NAT = 34;

constSel: Wire;

d1Bus: Wire _ CoreCreate.Seq["D1", ccWordLength];
d2Bus: Wire _ CoreCreate.Seq["D2", ccWordLength];
rBus: Wire _ CoreCreate.Seq["R", ccWordLength];
d1res: Wire _ CoreCreate.Seq["d1res", ccWordLength];
d2res: Wire _ CoreCreate.Seq["d2res", ccWordLength];

d1Constants: LORA;
d2Constants: LORA;
specRegD1Rows: NAT;
specRegD2Rows: NAT;

constSelReMap: ARRAY [0..7] OF NAT _ [1, 0, 7, 6, 5, 4, 3, 2];

ct: Core.CellType;
specRegConst11: Core.CellType _ Sisyph.ES["SpecRegConst11.sch", tamarinCx];
specRegConstD10: Core.CellType _ Sisyph.ES["SpecRegConstD10.sch", tamarinCx];
specRegConstD20: Core.CellType _ Sisyph.ES["SpecRegConstD20.sch", tamarinCx];

tileArray: TilingClass.TileArray;
rowIndex: NAT _ 0;
nbrConsts: NAT;

[d1Constants, d2Constants] _ TamarinUtil.GetSpecRegConstants[];
specRegD1Rows_ List.Length[d1Constants];
specRegD2Rows_ List.Length[d2Constants];
nbrConsts _ specRegD1Rows+specRegD2Rows;
constSel _ CoreCreate.Seq["constSel", nbrConsts];
tileArray _ NEW[TilingClass.TileArrayRec[nbrConsts]];

FOR const: LORA _ d1Constants, const.rest UNTIL const=NIL DO
constElt: TamarinUtil.SpecRegConstant _ NARROW[const.first];
tileArray[nbrConsts-constSelReMap[rowIndex]-1] _ NEW[TilingClass.TileRowRec[ccWordLength]];
FOR bit: NAT IN [0..ccWordLength) DO
ct _ (IF  TamarinUtil.RopeBitOnP[constElt.val, (IF bit>ccWordLength-3 THEN bit-ccWordLength+2 ELSE bit+2)]
THEN specRegConst11 ELSE specRegConstD10);
tileArray[nbrConsts-constSelReMap[rowIndex]-1][bit] _
NEW[TilingClass.TileRec _ [type: ct,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["d1res", d1res[bit]], ["d2res", d2res[bit]], ["Sel", constSel[constSelReMap[rowIndex]]], ["Gnd", "Gnd"]]]];
ENDLOOP;
rowIndex _ rowIndex+1;
ENDLOOP;

FOR const: LORA _ d2Constants, const.rest UNTIL const=NIL DO
constElt: TamarinUtil.SpecRegConstant _ NARROW[const.first];
tileArray[nbrConsts-constSelReMap[rowIndex]-1] _ NEW[TilingClass.TileRowRec[ccWordLength]];
FOR bit: NAT IN [0..ccWordLength) DO
ct _ (IF  TamarinUtil.RopeBitOnP[constElt.val, (IF bit>ccWordLength-3 THEN bit-ccWordLength+2 ELSE bit+2)]
THEN specRegConst11 ELSE specRegConstD20);
tileArray[nbrConsts-constSelReMap[rowIndex]-1][bit] _
NEW[TilingClass.TileRec _ [type: ct,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["d1res", d1res[bit]], ["d2res", d2res[bit]], ["Sel", constSel[constSelReMap[rowIndex]]], ["Gnd", "Gnd"]]]];
ENDLOOP;
rowIndex _ rowIndex+1;
ENDLOOP;

cellType _ TilingClass.CreateTiling[
name: "SpecRegConstants",
public: CoreCreate.WireList[LIST[constSel, TamarinUtil.ConvertDataBus[d1Bus], TamarinUtil.ConvertDataBus[d2Bus], TamarinUtil.ConvertDataBus[rBus], TamarinUtil.ConvertDataBus[d1res], TamarinUtil.ConvertDataBus[d2res], "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};

CreateDpCcDvr:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {

ccWordLength: NAT = 34;
dpCcSelSize: NAT = 6;

d1Bus: Wire _ CoreCreate.Seq["D1", ccWordLength];
d2Bus: Wire _ CoreCreate.Seq["D2", ccWordLength];
rBus: Wire _ CoreCreate.Seq["R", ccWordLength];
dpCCode: Wire _ CoreCreate.Seq["DpCCode", dpCcSelSize];
nSel: Wire _ CoreCreate.Seq["nSel", dpCcSelSize];
sel: Wire _ CoreCreate.Seq["sel", dpCcSelSize];
ccD1: Wire _ CoreCreate.Seq["ccD1", ccWordLength];
ccnD1: Wire _ CoreCreate.Seq["ccnD1", ccWordLength];
ccD2: Wire _ CoreCreate.Seq["ccD2", ccWordLength];
ccnD2: Wire _ CoreCreate.Seq["ccnD2", ccWordLength];
ccD1xorD2: Wire _ CoreCreate.Seq["ccD1xorD2", ccWordLength];
muxBus: Wire _ CoreCreate.Seq["MuxBus", 8];

dpCcDriver: Core.CellType _ Sisyph.ES["DpCcDvrElt.sch", tamarinCx];
dpCcDvrLeft: Core.CellType _ Sisyph.ES["DpCcDvrLeft.sch", tamarinCx];
dpCcDvrRt: Core.CellType _ Sisyph.ES["DpCcDvrRt.sch", tamarinCx];

tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[1]];

tileArray[0] _ NEW[TilingClass.TileRowRec[ccWordLength+2]];
tileArray[0][0] _
NEW[TilingClass.TileRec _ [type: dpCcDvrLeft,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];

FOR bit: NAT IN [0..ccWordLength) DO
tileArray[0][bit+1] _
NEW[TilingClass.TileRec _ [type: dpCcDriver,
renaming: LIST[ ["ccD1", ccD1[bit]], ["ccnD1", ccnD1[bit]], ["ccD2", ccD2[bit]], ["ccnD2", ccnD2[bit]], ["ccD1xorD2", ccD1xorD2[bit]], ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;

tileArray[0][ccWordLength+1] _
NEW[TilingClass.TileRec _ [type: dpCcDvrRt,
renaming: LIST[ ["MuxBus", muxBus], ["DpCcCondRes", "DpCcCondRes"], ["DpCCode", dpCCode], ["sel", sel], ["nSel", nSel], ["res", "res"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];

lastTile _ tileArray;

cellType _ TilingClass.CreateTiling[
name: "DpCcDvr",
public: CoreCreate.WireList[LIST[TamarinUtil.ConvertDataBus[d1Bus], TamarinUtil.ConvertDataBus[d2Bus], TamarinUtil.ConvertDataBus[rBus], muxBus, dpCCode, nSel, sel, ccD1, ccnD1, ccD2, ccnD2, ccD1xorD2, "res", "DpCcCondRes", "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};

CreateDpCcBot:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {

ccWordLength: NAT = 34;
dpCcSelSize: NAT = 6;

d1Bus: Wire _ CoreCreate.Seq["D1", ccWordLength];
d2Bus: Wire _ CoreCreate.Seq["D2", ccWordLength];
rBus: Wire _ CoreCreate.Seq["R", ccWordLength];
nSel: Wire _ CoreCreate.Seq["nSel", dpCcSelSize];
sel: Wire _ CoreCreate.Seq["sel", dpCcSelSize];
ccD1: Wire _ CoreCreate.Seq["ccD1", ccWordLength];
ccnD1: Wire _ CoreCreate.Seq["ccnD1", ccWordLength];
ccD2: Wire _ CoreCreate.Seq["ccD2", ccWordLength];
ccnD2: Wire _ CoreCreate.Seq["ccnD2", ccWordLength];
ccD1xorD2: Wire _ CoreCreate.Seq["ccD1xorD2", ccWordLength];
muxBus: Wire _ CoreCreate.Seq["MuxBus", 8];

tags: LORA _ TamarinUtil.GetDpCondCodes[];
ccRows: NAT _ List.Length[tags];

ct: Core.CellType;

ccBasect: Core.CellType _ Sisyph.ES["ccBase.sch", tamarinCx];
ccD10D2Xct: Core.CellType _ Sisyph.ES["ccD10D2X.sch", tamarinCx];
ccD11D2Xct: Core.CellType _ Sisyph.ES["ccD11D2X.sch", tamarinCx];
ccD1XD20ct: Core.CellType _ Sisyph.ES["ccD1XD20.sch", tamarinCx];
ccD10D20ct: Core.CellType _ Sisyph.ES["ccD10D20.sch", tamarinCx];
ccD11D20ct: Core.CellType _ Sisyph.ES["ccD11D20.sch", tamarinCx];
ccD1XD21ct: Core.CellType _ Sisyph.ES["ccD1XD21.sch", tamarinCx];
ccD10D21ct: Core.CellType _ Sisyph.ES["ccD10D21.sch", tamarinCx];
ccD11D21ct: Core.CellType _ Sisyph.ES["ccD11D21.sch", tamarinCx];
ccD1eqD2ct: Core.CellType _ Sisyph.ES["ccD1eqD2.sch", tamarinCx];

dpCcEltLeft: Core.CellType _ Sisyph.ES["DpCcEltLeft.sch", tamarinCx]; 
dpCcSpacer: Core.CellType _ Sisyph.ES["DpCcSpacer.sch", tamarinCx]; 
dpCcDecode0: Core.CellType _ Sisyph.ES["DpCcDecode0.sch", tamarinCx];
dpCcDecode1: Core.CellType _ Sisyph.ES["DpCcDecode1.sch", tamarinCx];
dpCcSense: Core.CellType _ Sisyph.ES["DpCcSense.sch", tamarinCx]; 

rowIndex: NAT _ 0;
tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[ccRows]];

FOR tagList: LORA _ tags, tagList.rest UNTIL tagList=NIL DO
tagElt: TamarinUtil.DpCondCode _ NARROW[tagList.first];
tileArray[rowIndex] _ NEW[TilingClass.TileRowRec[ccWordLength+dpCcSelSize+3]];

tileArray[rowIndex][0] _
NEW[TilingClass.TileRec _ [type:  dpCcEltLeft,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];

FOR bit: NAT IN [0..ccWordLength) DO
mapBit: NAT _ IF bit < (ccWordLength - 2) THEN  bit + 2 ELSE bit - (ccWordLength - 2);
d1: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.d1, mapBit];
d2: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.d2, mapBit];
nD1: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.nD1, mapBit];
nD2: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.nD2, mapBit];
d1XorD2: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.d1XorD2, mapBit];
SELECT TRUE FROM
(~d1 AND ~d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccBasect};
(~d1 AND ~d2 AND nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD10D2Xct};
(d1 AND ~d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD11D2Xct};
(~d1 AND ~d2 AND ~nD1 AND nD2 AND ~d1XorD2) => {ct _ ccD1XD20ct};
(~d1 AND ~d2 AND nD1 AND nD2 AND ~d1XorD2) => {ct _ ccD10D20ct};
(d1 AND ~d2 AND ~nD1 AND nD2 AND ~d1XorD2) => {ct _ ccD11D20ct};
(~d1 AND d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD1XD21ct};
(~d1 AND d2 AND nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD10D21ct};
(d1 AND d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD11D21ct};
(~d1 AND ~d2 AND ~nD1 AND ~nD2 AND d1XorD2) => {ct _ ccD1eqD2ct};
ENDCASE => ERROR;

tileArray[rowIndex][bit+1] _
NEW[TilingClass.TileRec _ [type: ct,
renaming: LIST[ ["ccD1", ccD1[bit]], ["ccnD1", ccnD1[bit]], ["ccD2", ccD2[bit]], ["ccnD2", ccnD2[bit]], ["ccD1xorD2", ccD1xorD2[bit]], ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["Gnd", "Gnd"]]]];
ENDLOOP;

tileArray[rowIndex][ccWordLength+1] _
NEW[TilingClass.TileRec _ [type:  dpCcSpacer,
renaming: NIL]];

FOR bit: NAT IN [0..dpCcSelSize) DO
tileArray[rowIndex][ccWordLength+bit+2] _
NEW[TilingClass.TileRec _
[type: (IF TamarinUtil.BitOnP[tagElt.index, dpCcSelSize-bit-1] THEN dpCcDecode1 ELSE dpCcDecode0),
renaming: LIST[ ["sel", sel[bit]], ["nSel", nSel[bit]], ["Gnd", "Gnd"]]]];
ENDLOOP;

tileArray[rowIndex][ccWordLength+dpCcSelSize+2] _
NEW[TilingClass.TileRec _ [type: dpCcSense,
renaming: LIST[ ["MuxBus", muxBus], ["res", "res"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];

rowIndex _ rowIndex + 1;
ENDLOOP;

lastTile _ tileArray;

IF rowIndex # (ccRows) THEN ERROR;

cellType _ TilingClass.CreateTiling[
name: "DpCcBot",
public: CoreCreate.WireList[ LIST[TamarinUtil.ConvertDataBus[d1Bus], TamarinUtil.ConvertDataBus[d2Bus], TamarinUtil.ConvertDataBus[rBus], muxBus, nSel, sel, ccD1, ccnD1, ccD2, ccnD2, ccD1xorD2, "res", "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};

CreateIBufCore:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {
nRows: NAT _ 8;
d1: Wire _ CoreCreate.Seq["D1", 32];
d2: Wire _ CoreCreate.Seq["D2", 32];
R: Wire _ CoreCreate.Seq["R", 32];
x: Wire _ CoreCreate.Seq["X32", 32];
selCur: Wire _ CoreCreate.Seq["SelCur", nRows];
selNext: Wire _ CoreCreate.Seq["SelNext", nRows];
selWrite: Wire _ CoreCreate.Seq["SelWrite", nRows];
curIWd: Wire _ CoreCreate.Seq["CurIWd", 32];
nextIWd: Wire _ CoreCreate.Seq["NextIWd", 32];

ibufDrive: Core.CellType _ Sisyph.ES["IBufDrive.sch", tamarinCx];
ibufReg:  Core.CellType _ Sisyph.ES["IBufReg.sch", tamarinCx];

tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[nRows+1]];
tileArray[0] _ NEW[TilingClass.TileRowRec[32]];
FOR  i: NAT IN [0..31] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: ibufDrive,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["Clock", "Clock"], ["nWtIBuf", "nWtIBuf"], ["X", x[i]], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]] ]
]]; 
ENDLOOP;

FOR row: NAT IN [0..nRows) DO
tileArray[row+1] _ NEW[TilingClass.TileRowRec[32]];
FOR  i: NAT IN [0..31] DO
tileArray[row+1][i] _ NEW[TilingClass.TileRec _ [
type: ibufReg,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["SelCur", selCur[row]], ["SelNext", selNext[row]], ["SelWrite", selWrite[row]], ["CurIWd", curIWd[i]], ["NextIWd", nextIWd[i]], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]]]
]];
ENDLOOP;
ENDLOOP;

lastTile _ tileArray;

cellType _ TilingClass.CreateTiling[
name: "IBufCore",
public: CoreCreate.WireList[LIST[d1, d2, R, x, selCur, selNext, selWrite, curIWd, nextIWd, "nWtIBuf", "Clock", "Vdd", "Gnd"]], 
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};

CreateIShiftCore:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {
CreateBus: PROC [name: Core.ROPE] RETURNS [wire: Wire] =  {
wire _ CoreCreate.WireList[ LIST [ CoreCreate.Seq[NIL, 4], CoreCreate.Seq[NIL, 4], CoreCreate.Seq[NIL, 4], CoreCreate.Seq[NIL, 4], CoreCreate.Seq[NIL, 4], CoreCreate.Seq[NIL, 4], CoreCreate.Seq[NIL, 4], CoreCreate.Seq[NIL, 4]], name];
};

nRows: NAT _ 8;

d1: Wire _ CreateBus["D1"];
d1out: Wire _ CreateBus["D1Out"];
d2: Wire _ CreateBus["D2"];
R: Wire _ CreateBus["R"];
curIWd: Wire _ CreateBus["CurIWd"];
nextIWd: Wire _ CreateBus["NextIWd"];

opcode: Wire _ CoreCreate.Seq["newOpcode", 8];
iBufN: Wire _ CoreCreate.Seq["newIBufN", 8];

selIData: Wire _ CoreCreate.Seq["SelIData", 2];
selDataSize: Wire _ CoreCreate.Seq["SelDataSize", 4];
selNext: Wire _ CoreCreate.Seq["SelNext", nRows];
selWrite: Wire _ CoreCreate.Seq["SelWrite", nRows];


iShiftBlock: Core.CellType _ Sisyph.ES["IShiftBlock.sch", tamarinCx];

tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[1]];
tileArray[0] _ NEW[TilingClass.TileRowRec[8]];
FOR  i: NAT IN [0..6] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: iShiftBlock,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["SelDataSize", selDataSize],  ["SelIData", selIData], ["Sel0", "Sel0"], ["Sel1", "Sel1"],   ["Sel2", "Sel2"], ["Sel3", "Sel3"], ["Clock", "Clock"], ["Load", "Load"], ["D1", d1[i]], ["D1Out", d1out[i]], ["D2", d2[i]], ["R", R[i]] , ["NextWord", nextIWd[i]], ["CurWord", curIWd[i]], ["OpOut", opcode[i]], ["IBufNOut", iBufN[i]] ]
]]; 
ENDLOOP;

tileArray[0][7] _ NEW[TilingClass.TileRec _ [
type: iShiftBlock,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["SelDataSize", selDataSize], ["SelIData", selIData], ["Sel0", "Sel0"], ["Sel1", "Sel1"], ["Sel2", "Sel2"], ["Sel3", "Sel3"], ["Clock", "Clock"], ["Load", "Load"], ["D1", d1[7]], ["D1Out", d1out[7]], ["D2", d2[7]], ["R", R[7]], ["NextWord", nextIWd[7]], ["CurWord", curIWd[7]], ["OpOut", opcode[7]], ["IBufNOut", iBufN[7]] ]
]];

lastTile _ tileArray;

cellType _ TilingClass.CreateTiling[
name: "IShiftCore",
public: CoreCreate.WireList[LIST[d1, d2, R, d1out, curIWd, nextIWd, selDataSize, selIData, opcode, iBufN, "Sel0", "Sel1", "Sel2", "Sel3", "Load", "Clock", "Vdd", "Gnd"]], 
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];

};

CreatePc:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {
muxBus: Wire _ CoreCreate.Seq["MuxBus", 8];
d1: Wire _ CoreCreate.Seq["D1", 34];
d2: Wire _ CoreCreate.Seq["D2", 34];
R: Wire _ CoreCreate.Seq["R", 34];
rdAddr: Wire _ CoreCreate.Seq["IRdAddr", 5];
opLength: Wire _ CoreCreate.Seq["LOpLength", 3];
enb: Wire _ CoreCreate.Seq["Enb", 2];

pca: Core.CellType _ Sisyph.ES["PCa.sch", tamarinCx];
pcb:  Core.CellType _ Sisyph.ES["PCb.sch", tamarinCx];
pcc: Core.CellType _ Sisyph.ES["PCc.sch", tamarinCx];
pcd: Core.CellType _ Sisyph.ES["PCd.sch", tamarinCx];
pce: Core.CellType _ Sisyph.ES["PCe.sch", tamarinCx];

tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[1]];
tileArray[0] _ NEW[TilingClass.TileRowRec[34]];

FOR  i: NAT IN [0..19] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: pce,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["Enb", enb], ["Clock", "Clock"], ["iD1", "iD1"], ["iMuxBus", "iMuxBus"], ["iNextPc", "iNextPc"],["iSamePc", "iSamePc"] ]
]]; 
ENDLOOP;

FOR  i: NAT IN [20..23] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: pcd,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["Enb", enb], ["Clock", "Clock"], ["iD1", "iD1"], ["iMuxBus", "iMuxBus"], ["iNextPc", "iNextPc"],["iSamePc", "iSamePc"]  ]
]]; 
ENDLOOP;

FOR  i: NAT IN [24..26] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: pcc,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["MuxBus", muxBus[i-24]], ["Enb", enb], ["Clock", "Clock"], ["iD1", "iD1"], ["iMuxBus", "iMuxBus"], ["iNextPc", "iNextPc"],["iSamePc", "iSamePc"]  ]
]]; 
ENDLOOP;

FOR  i: NAT IN [27..28] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: pcc,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["RdAddr", rdAddr[i-27]], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["MuxBus", muxBus[i-24]], ["Enb", enb], ["Clock", "Clock"], ["iD1", "iD1"], ["iMuxBus", "iMuxBus"], ["iNextPc", "iNextPc"],["iSamePc", "iSamePc"]  ]
]]; 
ENDLOOP;

FOR  i: NAT IN [29..31] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: pcb,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["MuxBus", muxBus[i-24]], ["OpLength", opLength[i-29]], ["RdAddr", rdAddr[i-27]], ["Enb", enb], ["Clock", "Clock"], ["iD1", "iD1"], ["iMuxBus", "iMuxBus"], ["iNextPc", "iNextPc"],["iSamePc", "iSamePc"]  ]
]]; 
ENDLOOP;

FOR  i: NAT IN [32..33] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: pca,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["Enb", enb], ["Clock", "Clock"], ["iD1", "iD1"], ["iMuxBus", "iMuxBus"], ["iNextPc", "iNextPc"],["iSamePc", "iSamePc"]  ]
]]; 
ENDLOOP;

lastTile _ tileArray;

cellType _ TilingClass.CreateTiling[
name: "PcCore",
public: CoreCreate.WireList[LIST[TamarinUtil.ConvertDataBus[d1], TamarinUtil.ConvertDataBus[d2], TamarinUtil.ConvertDataBus[R], muxBus, rdAddr, opLength, enb, "iD1", "iMuxBus", "iSamePc", "iNextPc", "Clock", "Vdd", "Gnd"]], 
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};

CreateRegMuxBlock:  PUBLIC PROC [tamarinCx: Sisyph.Context, n: NAT] RETURNS [cellType: Core.CellType] = {
d1: Wire _ CoreCreate.Seq["D1", n+1];
d2: Wire _ CoreCreate.Seq["D2", n+1];
R: Wire _ CoreCreate.Seq["R", n+1];
eltCtl: Wire _ CoreCreate.Seq["EltCtl", 4];
muxBus: Wire _ CoreCreate.Seq["MuxBus", 8];
regAddr: Wire _ CoreCreate.Seq["RegAddr", 6];
val: Wire _ CoreCreate.Seq["Val", n];
load: Wire _ CoreCreate.Seq["Load", 2];
enb: Wire _ CoreCreate.Seq["Enb", 2];

regMuxBase: Core.CellType _ Sisyph.ES["RegMuxBase.sch", tamarinCx];

regMuxBit: Core.CellType _ Sisyph.ES["RegMuxBit.sch", tamarinCx];

tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[1]];
tileArray[0] _ NEW[TilingClass.TileRowRec[n+1]];

FOR  i: NAT IN [0..n) DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: regMuxBit,
renaming: 
IF i < (n-6) THEN
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["Val", val[i]], ["MuxBus", muxBus[i + 8-n]] ]
ELSE
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["Val", val[i]], ["MuxBus", muxBus[i + 8-n]], ["RegAddr", regAddr[i - (n-6)]] ]
]]; 
ENDLOOP;


tileArray[0][n] _  
NEW[TilingClass.TileRec _ [
type: regMuxBase, 
renaming: 
SELECT n FROM 
6 =>
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[n]], ["D2", d2[n]], ["R", R[n]], ["EltCtl", eltCtl], ["regEnb.RegEnb", "RegEnb"], ["muxEnb.MuxEnb", "MuxEnb"], ["Load", load] ,["Clock", "Clock"], ["Mux0",  muxBus[0]], ["Mux1",  muxBus[1]] ],
7 =>
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[n]], ["D2", d2[n]], ["R", R[n]], ["EltCtl", eltCtl], ["regEnb.RegEnb", "RegEnb"], ["muxEnb.MuxEnb", "MuxEnb"], ["Load", load] ,["Clock", "Clock"], ["Mux0",  muxBus[0]] ],
ENDCASE =>
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[n]], ["D2", d2[n]], ["R", R[n]], ["EltCtl", eltCtl], ["regEnb.RegEnb", "RegEnb"], ["muxEnb.MuxEnb", "MuxEnb"], ["Load", load] ,["Clock", "Clock"] ]
]];

lastTile _ tileArray;

cellType _ TilingClass.CreateTiling[
name: "RegMuxBlock",
public: CoreCreate.WireList[LIST[d1, d2, R, muxBus, regAddr, val, eltCtl, "RegEnb", "MuxEnb", load, "Clock", "Vdd", "Gnd"]], 
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};

CreateRegMuxLsb:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {
d1: Wire _ CoreCreate.Seq["D1", 8];
d2: Wire _ CoreCreate.Seq["D2", 8];
R: Wire _ CoreCreate.Seq["R", 8];
muxBus: Wire _ CoreCreate.Seq["MuxBus", 8];
regAddr: Wire _ CoreCreate.Seq["RegAddr", 6];
newuK: Wire _ CoreCreate.Seq["newuK",  8];
newOpcode: Wire _ CoreCreate.Seq["newOpcode",  8];
newIBufN: Wire _ CoreCreate.Seq["newIBufN", 8];
rtRegEnb: Wire _ CoreCreate.Seq["rtRegEnb", 2];
rtMuxEnb: Wire _ CoreCreate.Seq["rtMuxEnb", 2];
rtRegSel: Wire _ CoreCreate.Seq["rtRegSel", 3];
rtMuxSel: Wire _ CoreCreate.Seq["rtMuxSel", 4];
opMask: Wire _ CoreCreate.Seq["OpMask", 2];
newop: Wire _ CoreCreate.Seq["NewOp", 2];
load: Wire _ CoreCreate.Seq["Load", 2];
loadK: Wire _ CoreCreate.Seq["LoadK", 2];


regMuxLsbElt: Core.CellType _ Sisyph.ES["RegMuxLsbElt.sch", tamarinCx];
regMuxLsbHiElt: Core.CellType _ Sisyph.ES["RegMuxLsbHiElt.sch", tamarinCx];

tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[1]];
tileArray[0] _ NEW[TilingClass.TileRowRec[8]];

FOR  i: NAT IN [0..3] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: regMuxLsbHiElt,
renaming: 
(SELECT i FROM

0,1 =>
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["MuxBus", muxBus[i]], ["newuK", newuK[i]], ["newOpcode", newOpcode[i]], ["newIBufN", newIBufN[i]], ["OpMask", opMask[0]],  ["rtRegEnb", rtRegEnb], ["rtRegSel", rtRegSel], ["rtMuxEnb", rtMuxEnb], ["rtMuxSel", rtMuxSel], ["NewOp", newop], ["Load", load], ["LoadK", loadK], ["Clock", "Clock"] ],

2,3 =>
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["MuxBus", muxBus[i]], ["RegAddr", regAddr[i-2]],  ["newuK", newuK[i]], ["newOpcode", newOpcode[i]], ["newIBufN", newIBufN[i]], ["OpMask", opMask[0]],  ["rtRegEnb", rtRegEnb], ["rtRegSel", rtRegSel], ["rtMuxEnb", rtMuxEnb], ["rtMuxSel", rtMuxSel], ["NewOp", newop], ["Load", load], ["LoadK", loadK], ["Clock", "Clock"] ],

ENDCASE => ERROR)

]]; 
ENDLOOP;

FOR  i: NAT IN [4..7] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: regMuxLsbElt,
renaming: 
(SELECT i FROM

4 =>
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["MuxBus", muxBus[i]], ["RegAddr", regAddr[i-2]],  ["newuK", newuK[i]], ["newOpcode", newOpcode[i]], ["newIBufN", newIBufN[i]], ["OpMask", opMask[1]],  ["rtRegEnb", rtRegEnb], ["rtRegSel", rtRegSel], ["rtMuxEnb", rtMuxEnb], ["rtMuxSel", rtMuxSel], ["NewOp", newop], ["Load", load], ["LoadK", loadK], ["Clock", "Clock"] ],
5 =>
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["MuxBus", muxBus[i]], ["RegAddr", regAddr[i-2]],  ["newuK", newuK[i]], ["newOpcode", newOpcode[i]], ["newIBufN", newIBufN[i]], ["OpMask", "Gnd"],  ["rtRegEnb", rtRegEnb], ["rtRegSel", rtRegSel], ["rtMuxEnb", rtMuxEnb], ["rtMuxSel", rtMuxSel], ["NewOp", newop], ["Load", load], ["LoadK", loadK], ["Clock", "Clock"] ],
6,7 =>
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", d1[i]], ["D2", d2[i]], ["R", R[i]], ["MuxBus", muxBus[i]], ["RegAddr", regAddr[i-2]],  ["newuK", newuK[i]], ["newOpcode", newOpcode[i]], ["newIBufN", newIBufN[i]], ["OpMask", "Gnd"],  ["rtRegEnb", rtRegEnb], ["rtRegSel", rtRegSel], ["rtMuxEnb", rtMuxEnb], ["rtMuxSel", rtMuxSel], ["NewOp", newop], ["Load", load], ["LoadK", loadK], ["Clock", "Clock"] ],
ENDCASE => ERROR)

]]; 
ENDLOOP;

lastTile _ tileArray;

cellType _ TilingClass.CreateTiling[
name: "RegMuxLsb",
public: CoreCreate.WireList[LIST[d1, d2, R, muxBus, regAddr, newuK, rtRegEnb, rtRegSel, rtMuxEnb, rtMuxSel, newOpcode, newIBufN, opMask, newop, load, loadK, "Clock", "Vdd", "Gnd"]], 
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};


END.


ΊTamarinDataPathImpl.mesa
Copyright c 1987 by Xerox Corporation.  All rights reserved.
Last Edited by: Alan Bell October 27, 1987 1:50:08 pm PST
Krivacic September 4, 1987 5:52:46 pm PDT

CreateIShifter:  PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = {
R: Wire _ CoreCreate.Seq["R", 32];
Sel: Wire _ CoreCreate.Seq["Sel", 4];
IBSres: Wire _ CoreCreate.Seq["IBSres", 32];
OpCode: Wire _ CoreCreate.Seq["OpCode", 8];
NextIWd: Wire _ CoreCreate.Seq["NextIWd", 32];
CurIWd: Wire _ CoreCreate.Seq["CurIWd", 32];

Extract all of the cells once
IShiftTopCT: Core.CellType _ Sisyph.ES["IShiftTop.sch", tamarinCx];
IShiftTopNCCT:  Core.CellType _ Sisyph.ES["IShiftTopNC.sch", tamarinCx];
IShiftBaseCT: Core.CellType _ Sisyph.ES["IShiftBase.sch", tamarinCx];
IShiftBotCT: Core.CellType _ Sisyph.ES["IShiftBot.sch", tamarinCx];

tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[6]];
tileArray[0] _ NEW[TilingClass.TileRowRec[40]];
FOR  i: NAT IN [0..31] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: IShiftBotCT,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], 
["R", R[i]], ["IBSres", IBSres[i]], ["NextIWd", NextIWd[i]], ["CurIWd", CurIWd[i]] ]
]]; 
ENDLOOP;
FOR  i: NAT IN [32..39] DO
tileArray[0][i] _ NEW[TilingClass.TileRec _ [
type: IShiftBotCT,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], 
["R", "Gnd"], ["IBSres", OpCode[i-32]] ]
]]; 
ENDLOOP;


FOR row: NAT IN [1..4] DO
tileArray[row] _ NEW[TilingClass.TileRowRec[40]];
FOR  i: NAT IN [0..39] DO
tileArray[row][i] _ NEW[TilingClass.TileRec _ [
type: IShiftBaseCT,
renaming: LIST[ ["Select", Sel[row-1]] ]
]]; 
ENDLOOP;
ENDLOOP;

tileArray[5] _ NEW[TilingClass.TileRowRec[40]];
 FOR  i: NAT IN [0..31] DO
tileArray[5][i] _ NEW[TilingClass.TileRec _ [
type: IShiftTopCT,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"] ]
]]; 
ENDLOOP;
 FOR  i: NAT IN [32..39] DO
tileArray[5][i] _ NEW[TilingClass.TileRec _ [
type: IShiftTopNCCT,
flatten: FALSE,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"] ]
]]; 
ENDLOOP;

lastTile _ tileArray;

cellType _ TilingClass.CreateTiling[
name: "InstShifter",
public: CoreCreate.WireList[LIST[IBSres, R, Sel, OpCode, NextIWd, CurIWd, "Vdd", "Gnd"]], 
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};

Extract all of the cells once
Extract all of the cells once
Extract all of the cells once
pce - adder of opLength (3)
pcd - incrementer (3)
pcc - incrementer, input MuxBus (3)
pcc - incrementer, output RdAddr, input MuxBus (2)
pcb - adder of opLength, output RdAddr, input MuxBus (3)
pca - dummy cell (2)
Extract all of the cells once
-- Do the Bits of the Register

-- Do the Right hand side of the Reg Elt
Extract all of the cells once
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