DIRECTORY CD, CDSequencer, Core USING [CellType], CoreCreate, List, Sisyph USING [Context, ES], Tam, TamarinUtil, TilingClass USING [CreateTiling, SchematicsNeighborX, SchematicsNeighborY, TileArray, TileArrayRec, TileRec, TileRowRec]; TamarinDataPath: CEDAR PROGRAM IMPORTS CoreCreate, List, Sisyph, TamarinUtil, TilingClass EXPORTS Tam = BEGIN LORA: TYPE = List.LORA; Wire: TYPE = CoreCreate.Wire; WR: TYPE = CoreCreate.WR; lastTile: TilingClass.TileArray _ NIL; CreateSpecRegConstants: PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = { ccWordLength: NAT = 34; constSel: Wire; d1Bus: Wire _ TamarinUtil.MakeDataBus["D1"]; d2Bus: Wire _ TamarinUtil.MakeDataBus["D2"]; rBus: Wire _ TamarinUtil.MakeDataBus["R"]; d1res: Wire _ TamarinUtil.MakeDataBus["d1res"]; d2res: Wire _ TamarinUtil.MakeDataBus["d2res"]; d1Constants: LORA; d2Constants: LORA; specRegD1Rows: NAT; specRegD2Rows: NAT; ct: Core.CellType; specRegConst11: Core.CellType _ Sisyph.ES["SpecRegConst11.sch", tamarinCx]; specRegConstD10: Core.CellType _ Sisyph.ES["SpecRegConstD10.sch", tamarinCx]; specRegConstD20: Core.CellType _ Sisyph.ES["SpecRegConstD20.sch", tamarinCx]; tileArray: TilingClass.TileArray; rowIndex: NAT _ 0; [d1Constants, d2Constants] _ TamarinUtil.GetSpecRegConstants[]; specRegD1Rows_ List.Length[d1Constants]; specRegD2Rows_ List.Length[d2Constants]; constSel _ CoreCreate.Seq["constSel", specRegD1Rows+specRegD2Rows]; tileArray _ NEW[TilingClass.TileArrayRec[specRegD1Rows+specRegD2Rows]]; FOR const: LORA _ d1Constants, const.rest UNTIL const=NIL DO constElt: TamarinUtil.SpecRegConstant _ NARROW[const.first]; tileArray[rowIndex] _ NEW[TilingClass.TileRowRec[ccWordLength]]; FOR bit: NAT IN [0..ccWordLength) DO ct _ (IF TamarinUtil.RopeBitOnP[constElt.val, bit] THEN specRegConst11 ELSE specRegConstD10); tileArray[rowIndex][bit] _ NEW[TilingClass.TileRec _ [type: ct, flatten: FALSE, renaming: LIST[ ["D1", TamarinUtil.DataBusToWire[d1Bus, bit]], ["D2", TamarinUtil.DataBusToWire[d2Bus, bit]], ["R", TamarinUtil.DataBusToWire[rBus, bit]], ["d1res", TamarinUtil.DataBusToWire[d1res, bit]], ["d2res", TamarinUtil.DataBusToWire[d2res, bit]], ["Sel", constSel[rowIndex]], ["Gnd", "Gnd"]]]]; ENDLOOP; rowIndex _ rowIndex+1; ENDLOOP; FOR const: LORA _ d2Constants, const.rest UNTIL const=NIL DO constElt: TamarinUtil.SpecRegConstant _ NARROW[const.first]; tileArray[rowIndex] _ NEW[TilingClass.TileRowRec[ccWordLength]]; FOR bit: NAT IN [0..ccWordLength) DO ct _ (IF TamarinUtil.RopeBitOnP[constElt.val, bit] THEN specRegConst11 ELSE specRegConstD20); tileArray[rowIndex][bit] _ NEW[TilingClass.TileRec _ [type: ct, flatten: FALSE, renaming: LIST[ ["D1", TamarinUtil.DataBusToWire[d1Bus, bit]], ["D2", TamarinUtil.DataBusToWire[d2Bus, bit]], ["R", TamarinUtil.DataBusToWire[rBus, bit]], ["d1res", TamarinUtil.DataBusToWire[d1res, bit]], ["d2res", TamarinUtil.DataBusToWire[d2res, bit]], ["Sel", constSel[rowIndex]], ["Gnd", "Gnd"]]]]; ENDLOOP; rowIndex _ rowIndex+1; ENDLOOP; cellType _ TilingClass.CreateTiling[ name: "SpecRegConstants", public: CoreCreate.WireList[LIST[constSel, d1Bus, d2Bus, rBus, d1res, d2res, "Gnd"]], tileArray: tileArray, neighborX: TilingClass.SchematicsNeighborX, neighborY: TilingClass.SchematicsNeighborY]; }; CreateDpCc: PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = { ccWordLength: NAT = 34; dpCcSelSize: NAT = 5; d1Bus: Wire _ CoreCreate.Seq["D1", ccWordLength]; d2Bus: Wire _ CoreCreate.Seq["D2", ccWordLength]; rBus: Wire _ CoreCreate.Seq["R", ccWordLength]; selIn: Wire _ CoreCreate.Seq["SelIn", dpCcSelSize]; tags: LORA _ TamarinUtil.GetDpCondCodes[]; ccRows: NAT _ List.Length[tags]+1; ct: Core.CellType; ccBasect: Core.CellType _ Sisyph.ES["ccBase.sch", tamarinCx]; ccD10D2Xct: Core.CellType _ Sisyph.ES["ccD10D2X.sch", tamarinCx]; ccD11D2Xct: Core.CellType _ Sisyph.ES["ccD11D2X.sch", tamarinCx]; ccD1XD20ct: Core.CellType _ Sisyph.ES["ccD1XD20.sch", tamarinCx]; ccD10D20ct: Core.CellType _ Sisyph.ES["ccD10D20.sch", tamarinCx]; ccD11D20ct: Core.CellType _ Sisyph.ES["ccD10D20.sch", tamarinCx]; ccD1XD21ct: Core.CellType _ Sisyph.ES["ccD10D21.sch", tamarinCx]; ccD10D21ct: Core.CellType _ Sisyph.ES["ccD10D21.sch", tamarinCx]; ccD11D21ct: Core.CellType _ Sisyph.ES["ccD11D21.sch", tamarinCx]; ccD1eqD2ct: Core.CellType _ Sisyph.ES["ccD1eqD2.sch", tamarinCx]; dpCcDriver: Core.CellType _ Sisyph.ES["DpCcDriver.sch", tamarinCx]; dpCcSelDvr: Core.CellType _ Sisyph.ES["DpCcSelDvr.sch", tamarinCx]; dpCcDecode0: Core.CellType _ Sisyph.ES["DpCcDecode0.sch", tamarinCx]; dpCcDecode1: Core.CellType _ Sisyph.ES["DpCcDecode1.sch", tamarinCx]; dpCcSenseOut: Core.CellType _ Sisyph.ES["DpCcSenseOut.sch", tamarinCx]; dpCcSense: Core.CellType _ Sisyph.ES["DpCcSense.sch", tamarinCx]; rowIndex: NAT _ 0; tileArray: TilingClass.TileArray _ NEW[TilingClass.TileArrayRec[ccRows]]; tileArray[ccRows-1] _ NEW[TilingClass.TileRowRec[ccWordLength+dpCcSelSize+1]]; FOR bit: NAT IN [0..ccWordLength) DO tileArray[ccRows-1][bit] _ NEW[TilingClass.TileRec _ [type: dpCcDriver, flatten: FALSE, renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]]; ENDLOOP; FOR bit: NAT IN [0..dpCcSelSize) DO tileArray[ccRows-1][ccWordLength+bit] _ NEW[TilingClass.TileRec _ [type: dpCcSelDvr, flatten: FALSE, renaming: LIST[ ["SelIn", selIn[bit]], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]]; ENDLOOP; tileArray[ccRows-1][ccWordLength+dpCcSelSize] _ NEW[TilingClass.TileRec _ [type: dpCcSenseOut, flatten: FALSE, renaming: LIST[ ["SelOut", "SelOut"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]]; FOR tagList: LORA _ tags, tagList.rest UNTIL tagList=NIL DO tagElt: TamarinUtil.DpCondCode _ NARROW[tagList.first]; tileArray[rowIndex] _ NEW[TilingClass.TileRowRec[ccWordLength+dpCcSelSize+1]]; FOR bit: NAT IN [0..ccWordLength) DO d1: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.d1, bit]; d2: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.d2, bit]; nD1: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.nD1, bit]; nD2: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.nD2, bit]; d1XorD2: BOOLEAN _ TamarinUtil.RopeBitOnP[tagElt.d1XorD2, bit]; SELECT TRUE FROM (~d1 AND ~d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccBasect}; (~d1 AND ~d2 AND nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD10D2Xct}; (d1 AND ~d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD11D2Xct}; (~d1 AND ~d2 AND ~nD1 AND nD2 AND ~d1XorD2) => {ct _ ccD1XD20ct}; (~d1 AND ~d2 AND nD1 AND nD2 AND ~d1XorD2) => {ct _ ccD10D20ct}; (d1 AND ~d2 AND ~nD1 AND nD2 AND ~d1XorD2) => {ct _ ccD11D20ct}; (~d1 AND d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD1XD21ct}; (~d1 AND d2 AND nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD10D21ct}; (d1 AND d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct _ ccD11D21ct}; (~d1 AND ~d2 AND ~nD1 AND ~nD2 AND d1XorD2) => {ct _ ccD1eqD2ct}; ENDCASE => ERROR; tileArray[rowIndex][bit] _ NEW[TilingClass.TileRec _ [type: ct, flatten: FALSE, renaming: LIST[ ["Gnd", "Gnd"]]]]; ENDLOOP; FOR bit: NAT IN [0..dpCcSelSize) DO tileArray[rowIndex][ccWordLength+bit] _ NEW[TilingClass.TileRec _ [type: (IF TamarinUtil.BitOnP[tagElt.index, bit] THEN dpCcDecode1 ELSE dpCcDecode0), flatten: FALSE, renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]]; ENDLOOP; tileArray[rowIndex][ccWordLength+dpCcSelSize] _ NEW[TilingClass.TileRec _ [type: dpCcSense, flatten: FALSE, renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]]; rowIndex _ rowIndex + 1; ENDLOOP; lastTile _ tileArray; IF rowIndex # (ccRows-1) THEN ERROR; cellType _ TilingClass.CreateTiling[ name: "DpCc", public: CoreCreate.WireList[LIST[d1Bus, d2Bus, rBus, selIn, "DpCcCondRes", "Vdd", "Gnd"]], tileArray: tileArray, neighborX: TilingClass.SchematicsNeighborX, neighborY: TilingClass.SchematicsNeighborY]; }; END. ژTamarinDataPath.mesa Copyright c 1987 by Xerox Corporation. All rights reserved. Last Edited by: Alan Bell June 6, 1987 1:29:30 pm PDT ‌ت‡– "cedar" styleکcodeڑœ™Kڑœ دmœ1™