DIRECTORY Basics, BitOps, Core, CoreClasses, CoreCreate, CoreProperties, Ports, Rosemary, RosemaryUser, TamPorts, Rope, TamDefs, TamarinUtilImpl, TerminalIO, IO, Sisyph, FS; TamMemCells: CEDAR PROGRAM IMPORTS Ports, Rosemary, TamPorts, TamarinUtilImpl, TerminalIO, IO, CoreClasses, CoreCreate, FS, Rope SHARES TamarinUtilImpl = BEGIN OPEN TamDefs; memMax: NAT = 1000; MemState: TYPE = REF MemStateRec; MemStateRec: TYPE = RECORD [ writeData, writeTag, writeCycle, cas, physAddr, x, nClock, vdd, gnd: NAT _ LAST[NAT], lastClock: BOOL]; mem: ARRAY [0..memMax] OF Rope.ROPE; ReadMemory: PUBLIC PROC [name: Rope.ROPE _ NIL] = { stream: IO.STREAM; memIndex: NAT; memData: Rope.ROPE; stream _ FS.StreamOpen[(IF name = NIL THEN "TamMemory" ELSE name)]; WHILE ~IO.EndOf[stream] DO memIndex _ IO.GetInt[stream]; memData _ IO.GetTokenRope[stream].token; mem[memIndex] _ memData; ENDLOOP; IO.Close[stream]; }; CreateMemory: PUBLIC PROC [tamarinCx: Sisyph.Context] RETURNS [cellType: Core.CellType] = { cellType _CoreClasses.CreateUnspecified[CoreCreate.WireList[LIST["Vdd", "Gnd", "nClock", "WriteData", "WriteTag", "WriteCycle", "Cas", CoreCreate.Seq["PhysAddr", 32], CoreCreate.Seq["X", 40] ]], "Memory"]; [] _ Ports.InitPorts[cellType, l, none, "Vdd", "Gnd", "nClock", "WriteData", "WriteTag", "WriteCycle"]; [] _ Ports.InitPorts[cellType, ls, none, "PhysAddr", "X"]; }; MemInit: Rosemary.InitProc = { state: MemState _ NEW[MemStateRec]; state.lastClock _ FALSE; [state.vdd, state.gnd, state.nClock] _ Ports.PortIndexes[cellType.public, "Vdd", "Gnd", "nClock"]; [state.writeData, state.writeTag, state.writeCycle, state.cas, state.physAddr, state.x] _ Ports.PortIndexes[cellType.public, "WriteData", "WriteTag", "WriteCycle", "Cas", "PhysAddr", "X"]; [] _ Rosemary.SetFixedWire[cellType.public[state.vdd], H]; [] _ Rosemary.SetFixedWire[cellType.public[state.gnd], L]; stateAny _ state; }; MemEvalSimple: Rosemary.EvalProc = { XSet: PROC [p: Ports.Port, index: NAT, val: CARD, name: ATOM _ NIL] RETURNS [pval: CARD] = { IF TamPorts.HasXs[p, index] THEN { TamPorts.SetPVal[p, index, val]; p[index].d _ none; TerminalIO.PutF["X Input in Mem: %g index: %g \n", IO.atom[name], IO.int[index]]; }; pval _ TamPorts.PortToCard[p, index]; }; state: MemState _ NARROW[stateAny]; nClock: CARD _ XSet[p, state.nClock, 0, $nClock]; writeData: CARD _ XSet[p, state.writeData, 0, $writeData]; writeTag: CARD _ XSet[p, state.writeTag, 0, $writeTag]; writeCycle: CARD _ XSet[p, state.writeCycle, 0, $writeCycle]; casXSet: CARD _ XSet[p, state.cas, 0, $cas]; physAddr: CARD _ XSet[p, state.physAddr, 0, $physAddr]; clockset: BOOL _ TamPorts.PortToBool[p, state.nClock]; writing: BOOL _ TamPorts.PortToBool[p, state.writeCycle]; wtag: BOOL _ TamPorts.PortToBool[p, state.writeTag]; wdata: BOOL _ TamPorts.PortToBool[p, state.writeData]; cas: BOOL _ TamPorts.PortToBool[p, state.cas]; tag, data, xBus, memRope: Rope.ROPE; p[state.x].d _ none; IF clockset AND cas THEN IF writing THEN { -- chip is writing memory xBus _ Ports.LSToRope[p[state.x].ls, 40, 2]; tag _ Rope.Substr[(IF wtag THEN xBus ELSE mem[physAddr]), 0, 6]; data _ Rope.Substr[(IF wdata THEN xBus ELSE mem[physAddr]), 6, 34]; memRope _ Rope.Concat[tag, data]; mem[physAddr] _ memRope; TerminalIO.PutF["Writing Mem[%g] _ %g \n", IO.int[physAddr], IO.rope[memRope]]; } ELSE { -- chip is reading memory memRope _ mem[physAddr]; TamPorts.RopeToLS[memRope, p[state.x].ls]; p[state.x].d _ drive; TerminalIO.PutF["Reading Mem[%g] _ %g \n", IO.int[physAddr], IO.rope[memRope]]; }; stateAny _ state; }; uCodeName: Rope.ROPE = Rosemary.Register[roseClassName: "Memory", init: MemInit, evalSimple: MemEvalSimple]; END. ΨTamMemCells.mesa Copyright Σ 1987 by Xerox Corporation. All rights reserved. Krivacic September 23, 1987 2:42:24 pm PDT Last Edited by: Krivacic September 14, 1987 2:43:13 pm -------------------- Tamarin Memory Types --------------------- -------------------- Tamarin Memory Initialization --------------------- -------------------- Tamarin Memory Cell Creation --------------------- -------------------- Tamarin Memory Cell Initialization --------------------- --PROC [cellType: Core.CellType, p: Ports.Port] RETURNS [stateAny: REF ANY _ NIL]-- -------------------- Tamarin Memory Evaluation Proc --------------------- PROC [p: Ports.Port, stateAny: REF ANY]-- -- Clear any inputs with X's, setup to go to Reset Κ‰– "cedar" style˜Jšœ―Οr™°J˜J˜JšΟk ˜ Icodešœ£˜£J˜šΟn œžœž˜Jšžœ^˜eJšžœ˜Jšœžœžœ ˜J˜JšΟcœ œ™?J˜Jšœžœ˜Jšœ žœžœ ˜!Kš œ žœžœHžœžœžœžœ˜„Kšœžœ žœžœ˜$K˜K˜Jš œ œ™HK˜š Ÿ œžœžœ žœžœ˜4˜Kšœžœžœ˜Kšœ žœ˜Kšœžœ˜Kš œ žœ žœžœžœ žœ˜CK˜šžœžœžœ˜Kšœ žœ˜Kšœ žœ˜(Kšœ˜Kšžœ˜—K˜Kšžœ˜—K˜—J™J™Jš œ œ™GK˜K˜šŸ œžœžœžœ˜\˜KšœΝ˜ΝKšœg˜gKšœ:˜:—K˜—J˜J˜Jš œ$ œ™MJ˜K˜šŸœ˜K™Kš S™SK˜Kšœžœ˜#Kšœžœ˜K˜Kšœb˜bKšœΌ˜ΌK˜Kšœ:˜:Kšœ:˜:Kšœ˜Kšœ˜K˜—J˜Jš œ  œ™IJ˜J˜šŸ œ˜$J˜Jšžœžœžœ ™*J˜šŸœžœžœžœžœžœžœžœ˜ZJ˜šžœžœ˜"Jšœ ˜ Jšœ˜Jšœ4žœ žœ ˜RJ˜—Jšœ%˜%J˜J˜—J˜Jšœžœ ˜%J˜Jš 2™2J˜Jšœžœ&˜2Jšœ žœ+˜:Jšœ žœ)˜7Jšœ žœ-˜=Jšœ žœ˜,Jšœ žœ)˜7Jšœ žœ(˜6Jšœ žœ,˜9Jšœžœ*˜4Jšœžœ+˜6Jšœžœ%˜.Jšœžœ˜$J˜Jšœ˜šžœžœ˜šžœ žœ ˜-Jšœ,˜,Jšœžœžœžœ˜AJšœžœžœžœ˜HJšœ!˜!Jšœ˜Jšœ,žœ"˜PJšœ˜šžœ ˜#Jšœ˜Jšœ*˜*J˜Jšœ,žœ"˜PJšœ˜——Jšœ˜—Jšœ˜—J˜J™J˜JšœžœX˜lJ˜J˜Jšžœ˜—J™JšΟb˜—…—|έ