-- ClockCtl.oracle
-- (ClockIn ResetIn OpValid clrflags setflags irq2 irq1 muxbus) (nClock2 Clock2 nClock Clock ResetOut Preconds) 
-- Last Edited by: Alan Bell September 13, 1987 11:12:34 am PDT
-- Krivacic October 12, 1987 3:52:20 pm PDT

0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 1 0 0 0 0 0 00 | X X X X X XX
1 1 0 0 0 0 0 00 | X X X X X XX
0 1 0 0 0 0 0 00 | X X X X X XX
1 1 0 0 0 0 0 00 | X X X X X XX
0 1 0 0 0 0 0 00 | X X X X X XX
1 1 0 0 0 0 0 00 | X X X X X XX
0 1 0 0 0 0 0 00 | X X X X X XX
1 1 0 0 0 0 0 00 | X X X X X XX
0 1 0 0 0 0 0 00 | X X X X X XX
1 1 0 0 0 0 0 00 | X X X X X XX
0 1 0 0 0 0 0 00 | X X X X X XX
1 1 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 1 0 0 0 FF | X X X X X XX
0 0 0 1 0 0 0 FF | X X X X X XX
1 0 0 1 0 0 0 FF | X X X X X XX
0 0 0 1 0 0 0 FF | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 0 1 0 00 | X X X X X XX
1 0 0 0 0 1 0 00 | X X X X X XX
0 0 0 0 0 1 0 00 | X X X X X XX
1 0 0 0 0 1 0 00 | X X X X X XX
0 0 0 0 0 1 0 00 | X X X X X XX
1 0 0 0 0 1 0 00 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 1 0 0 02 | X X X X X XX
1 0 0 0 1 0 0 02 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 1 0 0 0 10 | X X X X X XX
1 0 0 1 0 0 0 10 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
0 0 0 0 0 1 1 00 | X X X X X XX
1 0 0 0 0 1 1 00 | X X X X X XX
0 0 0 0 0 1 1 00 | X X X X X XX
1 0 0 0 0 1 1 00 | X X X X X XX
0 0 0 0 0 1 1 00 | X X X X X XX
1 0 0 0 0 1 1 00 | X X X X X XX
0 0 0 1 0 1 1 10 | X X X X X XX
1 0 0 1 0 1 1 10 | X X X X X XX
0 0 0 0 0 1 1 00 | X X X X X XX
1 0 0 0 0 0 1 00 | X X X X X XX
0 0 0 0 1 0 0 04 | X X X X X XX
1 0 0 0 1 0 0 04 | X X X X X XX
0 0 0 0 0 0 0 00 | X X X X X XX
1 0 0 0 0 0 0 00 | X X X X X XX
.