TamarinUtilImpl.mesa
Copyright © 1987 by Xerox Corporation. All rights reserved.
Last Edited by: Alan Bell October 28, 1987 10:57:50 am PST
Krivacic September 4, 1987 5:31:53 pm PDT
DIRECTORY
BitOps,
Cabbage,
CD,
CDCommandOps,
CDIO,
CDSequencer,
CDSequencerExtras,
Core,
CoreCreate,
CoreOps,
CoreProperties,
FS,
IO,
List,
PW,
PWCore,
Rope,
Route,
SinixOps,
Sisyph,
Tam,
TamarinUtil,
TerminalIO;
TamarinUtilImpl:
CEDAR
PROGRAM
IMPORTS BitOps, Cabbage, CDCommandOps, CDIO, CoreCreate, CoreOps, CoreProperties, FS, IO, List, PW, PWCore, Rope, Route, SinixOps, Sisyph, TerminalIO
EXPORTS Tam, TamarinUtil = BEGIN
LORA: TYPE = List.LORA;
ROPE: TYPE = Rope.ROPE;
mask: PUBLIC CD.Design ← NIL;
tamMask: CD.Design ← NIL;
tamMaskR: CD.Design ← NIL;
constList: LORA ← NIL;
dpCcList: LORA ← NIL;
specRegConstD1List: LORA ← NIL;
specRegConstD2List: LORA ← NIL;
uCodeList: LORA ← NIL;
uCodeRomA, uCodeRomB: PUBLIC ARRAY [0..255] OF Rope.ROPE;
BitOnP:
PUBLIC
PROC [word, pos:
NAT]
RETURNS [v:
BOOLEAN] ={
v ← 1 = BitOps.WShift[word, - pos, 1]
};
RopeBitOnP:
PUBLIC
PROC [word: Rope.
ROPE, pos:
INT]
RETURNS [v:
BOOLEAN] = {
v ← (
IF pos<0
THEN
FALSE
ELSE
(
SELECT Rope.Fetch[word, pos]
FROM
'1 => TRUE,
'0, 'X => FALSE,
ENDCASE => ERROR));
};
ResetTamarinDefs:
PUBLIC
PROC = {
constList ← NIL;
dpCcList ← NIL;
specRegConstD1List ← NIL;
specRegConstD2List ← NIL;
uCodeList ← NIL; };
GetTamarinConstants:
PUBLIC
PROC
RETURNS[res:
LORA] = {
res ← List.Reverse[constList] };
GetDpCondCodes:
PUBLIC
PROC
RETURNS[res:
LORA] = {
res ← List.Reverse[dpCcList] };
GetSpecRegConstants:
PUBLIC
PROC
RETURNS[resD1:
LORA, resD2:
LORA] = {
resD1 ← List.Reverse[specRegConstD1List];
resD2 ← List.Reverse[specRegConstD2List] };
GetUCodeContents:
PUBLIC
PROC
RETURNS[res:
LORA] = {
res ← List.Reverse[uCodeList] };
TamConstant:
PUBLIC
PROC [atm:
ATOM, val:
INT] = {
const: TamarinUtil.TamConst ← NEW[ TamarinUtil.TamConstRec];
const^ ← [atm, val];
constList ← CONS[ const, constList] };
DpCCode:
PUBLIC
PROC [index:
NAT, d1, d2, nD1, nD, d1XorD2: Rope.
ROPE] = {
const: TamarinUtil.DpCondCode ← NEW[ TamarinUtil.DpCondCodeRec];
const^ ← [index, d1, d2, nD1, nD, d1XorD2];
dpCcList ← CONS[ const, dpCcList] };
SpecRegConst:
PUBLIC
PROC [wh, index:
NAT, val: Rope.
ROPE] = {
const: TamarinUtil.SpecRegConstant ← NEW[ TamarinUtil.SpecRegConstRec];
const^ ← [index, val];
IF wh=0 THEN specRegConstD1List ← CONS[ const, specRegConstD1List]
ELSE specRegConstD2List ← CONS[ const, specRegConstD2List] };
AddUCode:
PUBLIC
PROC [aAddr, bAddr:
NAT,
aeMI, aoMI, beMI, boMI: Rope.
ROPE] = {
const: TamarinUtil.UCodeWord ← NEW[ TamarinUtil.UCodeWordRec];
const^ ← [0, aAddr, bAddr, aeMI, aoMI, beMI, boMI];
uCodeList ← CONS[ const, uCodeList];
uCodeRomA[aAddr] ← aeMI;
uCodeRomA[aAddr+1] ← aoMI;
uCodeRomB[bAddr] ← beMI;
uCodeRomB[bAddr+1] ← boMI;
};
GetUCode:
PUBLIC PROC = {
stream: IO.STREAM;
aindex, bindex: NAT;
aeMI, aoMI, beMI, boMI: Rope.ROPE;
uCodeList ← NIL;
stream ← FS.StreamOpen["/Phylum/CTamarin/TamarinRoseSim/TamUCode"];
stream ← FS.StreamOpen["TamUCode"];
FOR i:
NAT ← 0, i + 1
WHILE (i < 128)
AND ~
IO.EndOf[stream]
DO
aindex ← IO.GetInt[stream];
aeMI ← IO.GetTokenRope[stream].token;
aoMI ← IO.GetTokenRope[stream].token;
bindex ← IO.GetInt[stream];
beMI ← IO.GetTokenRope[stream].token;
boMI ← IO.GetTokenRope[stream].token;
AddUCode[aindex, bindex, aeMI, aoMI, beMI, boMI];
ENDLOOP;
IO.Close[stream];
};
MakeDataBus:
PUBLIC
PROC [name:
ROPE]
RETURNS [res: CoreCreate.Wire] = {
res ← CoreCreate.WireList[LIST[CoreCreate.Seq["tag", 2], CoreCreate.Seq["data", 32]], name] };
ConvertDataBus:
PUBLIC
PROC [wire: CoreCreate.Wire]
RETURNS [res: CoreCreate.Wire] = {
res ← CoreOps.CreateWire[LIST[CoreOps.SubrangeWire[wire, wire.size-2, 2, "tag"],
CoreOps.SubrangeWire[wire, 0, wire.size-2, "data"]], CoreOps.GetShortWireName[wire]] };
ConvertDataBusBlock:
PUBLIC
PROC [wire: CoreCreate.Wire, name: Rope.
ROPE ←
NIL ]
RETURNS [res: CoreCreate.Wire] = {
res ← CoreOps.CreateWires[32, (IF name=NIL THEN CoreOps.GetShortWireName[wire] ELSE name)];
FOR block:
NAT
IN [0..7]
DO
FOR bit:
NAT
IN [0..3]
DO
res[block*4+bit] ← wire[block][bit];
ENDLOOP;
ENDLOOP
};
ConvertDataBusBlockPermute:
PUBLIC
PROC [wire: CoreCreate.Wire, name: Rope.
ROPE ←
NIL]
RETURNS [res: CoreCreate.Wire] = {
res ← CoreOps.CreateWires[32, (IF name=NIL THEN CoreOps.GetShortWireName[wire] ELSE name)];
FOR block:
NAT
IN [0..7]
DO
FOR bit:
NAT
IN [0..3]
DO
res[block+bit*8] ← wire[block][bit];
ENDLOOP;
ENDLOOP
};
DataBusToWire:
PUBLIC
PROC [wr: CoreCreate.Wire, n:
INT]
RETURNS [res: CoreCreate.Wire] = {
res ← (IF n < 2 THEN wr[0][n] ELSE wr[1][n-2]) };
OpenLayout:
PROC []
RETURNS [] = {
maskFileName: Rope.ROPE ← "TamarinLayout";
tamMask ← CDIO.ReadDesign[maskFileName, NIL, NIL, NIL];
};
SetMask:
PROC [command: CDSequencer.Command] = {
tamMask ← command.design
};
SetMaskR:
PROC [command: CDSequencer.Command] = {
tamMaskR ← command.design
};
TamGetAttribute: PWCore.AttributesProc = {
fileName: Rope.ROPE;
IF tamMask =
NIL
THEN {
fileName ← TerminalIO.RequestRope["Name of Layout File (include full path) > "];
tamMask ← PW.OpenDesign["lp2ExecutionLayout.dale"];
};
CoreProperties.PutCellTypeProp[cellType, $PWCoreSourceDesign, tamMask];
CoreProperties.PutCellTypeProp[cellType, $LichenTransistorTolerances, Rope.Flatten["1.0, 1.0"]];
};
TamGetRAttribute: PWCore.AttributesProc = {
fileName: Rope.ROPE;
IF tamMaskR =
NIL
THEN {
fileName ← TerminalIO.RequestRope["Name of Rom Layout File (include full path) > "];
tamMaskR ← PW.OpenDesign["LP2RegFileLayout.dale"];
};
CoreProperties.PutCellTypeProp[cellType, $PWCoreSourceDesign, tamMaskR];
CoreProperties.PutCellTypeProp[cellType, $LichenTransistorTolerances, Rope.Flatten["1.0, 1.0"]];
};
LayoutWithOutCabbageSignals:
PUBLIC PWCore.LayoutProc = {
TerminalIO.PutF["\nBEGIN: LayoutWithOutCabbageSignals: %g\n",
IO.time[]];
obj ← PWCore.Layout[cellType ! Cabbage.Signal =>
{TerminalIO.PutF["*** Cabbage Signal: %g\n", IO.rope[explanation]];
RESUME};
Route.Signal =>
{TerminalIO.PutF["*** Route Signal: %g\n",
IO.rope[explanation]]; RESUME} ];
TerminalIO.PutF["\nEND: LayoutWithOutCabbageSignals: %g\n", IO.time[]]};
NsExtractAndLayout:
PROC [comm: CDSequencer.Command] = {
root, cellType: Core.CellType;
[root: root, cell: cellType] ← SinixOps.SelectedCellType[comm.design, Sisyph.mode];
IF root=NIL THEN RETURN; -- Extraction ended in error, message already printed
TerminalIO.PutF["\nGenerating layout for %g.\n", IO.rope[CoreOps.GetCellTypeName[cellType]]];
[] ← PW.Draw[LayoutWithOutCabbageSignals[cellType]];
};
LayoutAndStore:
PROC [comm: CDSequencer.Command] = {
root, cellType: Core.CellType;
[root: root, cell: cellType] ← SinixOps.SelectedCellType[comm.design, Sisyph.mode];
IF root=NIL THEN RETURN; -- Extraction ended in error, message already printed
TerminalIO.PutF["\nGenerating layout for %g.\n", IO.rope[CoreOps.GetCellTypeName[cellType]]];
[] ← PW.Draw[PWCore.Layout[cellType]];
PWCore.Store[cellType]
};
CDCommandOps.RegisterWithMenu[
menu: $ProgramMenu,
entry: "Extract and Layout - No signals",
doc: "Extract and Layout",
proc: NsExtractAndLayout,
queue: doQueue
];
CDCommandOps.RegisterWithMenu[
menu: $ProgramMenu,
entry: "Layout and Store",
doc: "Layout and Store",
proc: LayoutAndStore,
queue: doQueue
];
CDCommandOps.RegisterWithMenu[
menu: $ProgramMenu,
entry: "Set Layout",
doc: "Sets .mask file for schematic generated layout",
proc: SetMask,
queue: dontQueue
];
CDCommandOps.RegisterWithMenu[
menu: $ProgramMenu,
entry: "Set Layout: Rom",
doc: "Sets .mask file for schematic generated layout",
proc: SetMaskR,
queue: dontQueue
];
[] ← PWCore.RegisterLayoutAtom[
layoutAtom: $TamGet,
layoutProc: PWCore.GetLayoutAtomRegistration[$Get].layoutProc,
decorateProc: PWCore.GetLayoutAtomRegistration[$Get].decorateProc,
attributesProc: TamGetAttribute
];
[] ← PWCore.RegisterLayoutAtom[
layoutAtom: $TamGet,
layoutProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].layoutProc,
decorateProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].decorateProc,
attributesProc: TamGetAttribute
];
[] ← PWCore.RegisterLayoutAtom[
layoutAtom: $TamGetAndFlatten,
layoutProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].layoutProc,
decorateProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].decorateProc,
attributesProc: TamGetAttribute
];
[] ← PWCore.RegisterLayoutAtom[
layoutAtom: $TamGetR,
layoutProc: PWCore.GetLayoutAtomRegistration[$Get].layoutProc,
decorateProc: PWCore.GetLayoutAtomRegistration[$Get].decorateProc,
attributesProc: TamGetRAttribute
];
[] ← PWCore.RegisterLayoutAtom[
layoutAtom: $TamGetAndFlattenR,
layoutProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].layoutProc,
decorateProc: PWCore.GetLayoutAtomRegistration[$GetAndFlatten].decorateProc,
attributesProc: TamGetRAttribute
]
END.