TamarinMemPathImpl.mesa
Copyright © 1987 by Xerox Corporation. All rights reserved.
Last Edited by: Alan Bell October 3, 1987 4:47:28 pm PDT
Krivacic September 3, 1987 3:38:23 pm PDT
DIRECTORY
CD,
CDSequencer,
Core USING [CellType, ROPE],
CoreCreate,
List,
Sisyph USING [Context, ES],
Tam,
TamarinUtil,
TilingClass
USING [CreateTiling, SchematicsNeighborX, SchematicsNeighborY,
TileArray, TileArrayRec, TileRec, TileRowRec];
TamarinMemPathImpl:
CEDAR
PROGRAM
IMPORTS CoreCreate, Sisyph, TamarinUtil, TilingClass
EXPORTS Tam
= BEGIN
LORA: TYPE = List.LORA;
Wire: TYPE = CoreCreate.Wire;
WR: TYPE = CoreCreate.WR;
lastTile: TilingClass.TileArray ← NIL;
CreateMemBuffer:
PUBLIC
PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: Core.CellType] = {
constSel: Wire;
d1Bus: Wire ← CoreCreate.Seq["D1", 34];
d2Bus: Wire ← CoreCreate.Seq["D2", 34];
rBus: Wire ← CoreCreate.Seq["R", 34];
x: Wire ← CoreCreate.Seq["X", 40];
xtoD2Enb: Wire ← CoreCreate.Seq["XtoD2Enb", 2];
xOutEnb: Wire ← CoreCreate.Seq["XOutEnb", 2];
memBufferElt: Core.CellType ← Sisyph.ES["MemBufferElt.sch", tamarinCx];
memBufferHiElt: Core.CellType ← Sisyph.ES["MemBufferHiElt.sch", tamarinCx];
tileArray: TilingClass.TileArray;
tileArray ← NEW[TilingClass.TileArrayRec[1]];
tileArray[0] ← NEW[TilingClass.TileRowRec[34]];
FOR bit:
NAT
IN [0..26)
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: memBufferHiElt,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["X1", x[bit+8]], ["XOutEnb", xOutEnb], ["XtoD2Enb", xtoD2Enb], ["SelData", "SelData"], ["SelTag", "SelTag"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
FOR bit:
NAT
IN [26..32)
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: memBufferElt,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["X1", x[bit+8]], ["X2", x[bit-26]], ["XOutEnb", xOutEnb], ["XtoD2Enb", xtoD2Enb], ["SelData", "SelData"], ["SelTag", "SelTag"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
FOR bit:
NAT
IN [32..34)
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: memBufferHiElt,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["X1", x[bit-32+6]], ["XOutEnb", xOutEnb], ["XtoD2Enb", xtoD2Enb], ["SelData", "SelData"], ["SelTag", "SelTag"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
cellType ← TilingClass.CreateTiling[
name: "MemBufferCore",
public: CoreCreate.WireList[LIST[constSel, TamarinUtil.ConvertDataBus[d1Bus], TamarinUtil.ConvertDataBus[d2Bus], TamarinUtil.ConvertDataBus[rBus], x, xOutEnb, xtoD2Enb, "SelData", "SelTag", "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};
CreateTLB:
PUBLIC
PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: Core.CellType] = {
d1Bus: Wire ← CoreCreate.Seq["D1", 32];
d2Bus: Wire ← CoreCreate.Seq["D2", 32];
rBus: Wire ← CoreCreate.Seq["R", 32];
vAddr: Wire ← CoreCreate.Seq["vAddr", 32];
tlbElt: Core.CellType ← Sisyph.ES["TLBelt.sch", tamarinCx];
tileArray: TilingClass.TileArray;
tileArray ← NEW[TilingClass.TileArrayRec[1]];
tileArray[0] ← NEW[TilingClass.TileRowRec[32]];
-- Top bits of Address
FOR bit:
NAT
IN [0..0]
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: tlbElt,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["vAddr", vAddr[bit]], ["ByteAddr", "ByteAddr"], ["nByteAddr", "nByteAddr"], ["s1", "Gnd"], ["s2", "Gnd"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
FOR bit:
NAT
IN [1..30]
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: tlbElt,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["vAddr", vAddr[bit]], ["ByteAddr", "ByteAddr"], ["nByteAddr", "nByteAddr"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
FOR bit:
NAT
IN [31..31]
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: tlbElt,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["vAddr", vAddr[bit]], ["ByteAddr", "ByteAddr"], ["nByteAddr", "nByteAddr"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
cellType ← TilingClass.CreateTiling[
name: "TLBCore",
public: CoreCreate.WireList[LIST[d1Bus, d2Bus, rBus, vAddr, "ByteAddr", "nByteAddr", "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};
CreateAddrSel:
PUBLIC
PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: Core.CellType] = {
d1Bus: Wire ← CoreCreate.Seq["D1", 32];
d2Bus: Wire ← CoreCreate.Seq["D2", 32];
rBus: Wire ← CoreCreate.Seq["R", 32];
mapAddr: Wire ← CoreCreate.Seq["MapAddr", 32];
phyAddr: Wire ← CoreCreate.Seq["PhyAddr", 32];
muxBus: Wire ← CoreCreate.Seq["MuxBus", 8];
uK2: Wire ← CoreCreate.Seq["uK2", 8];
uMemLatchSrc: Wire ← CoreCreate.Seq["uMemLatchSrc", 3];
uMemOffset: Wire ← CoreCreate.Seq["uMemOffset", 2];
uPhyAddrSrc: Wire ← CoreCreate.Seq["uPhyAddrSrc", 2];
iWrAddr: Wire 𡤌oreCreate.Seq["iWrAddr",3];
addrSelHiBit: Core.CellType ← Sisyph.ES["AddrSelHiBit.sch", tamarinCx];
addrSelLoBit: Core.CellType ← Sisyph.ES["AddrSelLoBit.sch", tamarinCx];
tileArray: TilingClass.TileArray;
tileArray ← NEW[TilingClass.TileArrayRec[1]];
tileArray[0] ← NEW[TilingClass.TileRowRec[32]];
-- Top bits of Address
FOR bit:
NAT
IN [0..24)
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: addrSelHiBit,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["MapAddr", mapAddr[bit]], ["PhyAddr", phyAddr[bit]], ["uMemLatchSrc", uMemLatchSrc], ["uPhyAddrSrc", uPhyAddrSrc], ["LatchPhys", "LatchPhys"], ["Clock", "Clock"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
-- Lower bits of Address in the path of the 8 bit adder
FOR bit:
NAT
IN [24..29)
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: addrSelLoBit,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["MuxBus", muxBus[bit-24]], ["uK2", uK2[bit-24]], ["MapAddr", mapAddr[bit]], ["PhyAddr", phyAddr[bit]], ["uMemLatchSrc", uMemLatchSrc], ["uMemOffset", uMemOffset], ["uPhyAddrSrc", uPhyAddrSrc], ["LatchPhys", "LatchPhys"], ["Clock", "Clock"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
-- 2 bits of the Address where the IBuf iWrAddr is taken from
FOR bit:
NAT
IN [29..31)
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: addrSelLoBit,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["MuxBus", muxBus[bit-24]], ["uK2", uK2[bit-24]], ["MapAddr", mapAddr[bit]], ["PhyAddr", phyAddr[bit]], ["iWrAddr", iWrAddr[bit - 29]], ["uMemLatchSrc", uMemLatchSrc], ["uMemOffset", uMemOffset], ["uPhyAddrSrc", uPhyAddrSrc], ["LatchPhys", "LatchPhys"], ["Clock", "Clock"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
-- LSB bit of Address where carry in is 0, LSB of iWrAddr is taken from
FOR bit:
NAT
IN [31..32)
DO
tileArray[0][bit] ←
NEW[TilingClass.TileRec ← [type: addrSelLoBit,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]], ["MuxBus", muxBus[bit-24]], ["uK2", uK2[bit-24]], ["MapAddr", mapAddr[bit]], ["PhyAddr", phyAddr[bit]], ["iWrAddr", iWrAddr[bit - 29]], ["uMemLatchSrc", uMemLatchSrc], ["uMemOffset", uMemOffset], ["uPhyAddrSrc", uPhyAddrSrc], ["LatchFetchPc", "LatchFetchPc"], ["LatchPhys", "LatchPhys"], ["Cin", "Vdd"], ["Clock", "Clock"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
cellType ← TilingClass.CreateTiling[
name: "AddrSelCore",
public: CoreCreate.WireList[LIST[d1Bus, d2Bus, rBus, muxBus, uK2, mapAddr, phyAddr, iWrAddr, uMemLatchSrc, uMemOffset, uPhyAddrSrc, "Clock", "LatchPhys", "LatchFetchPc", "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};
END.