TamarinEUImpl.mesa
Copyright © 1987 by Xerox Corporation. All rights reserved.
Last Edited by: Ross May 15, 1987 12:24:48 pm PDT
Last Edited by: Alan Bell October 5, 1987 6:11:31 pm PDT
Krivacic July 14, 1987 9:44:10 am PDT
DIRECTORY
CD,
CDSequencer,
Core USING [CellType],
CoreCreate,
PWCore,
Sisyph USING [Context, ES],
Tam,
TamarinUtil,
TilingClass
USING [CreateTiling, SchematicsNeighborX, SchematicsNeighborY,
TileArray, TileArrayRec, TileRec, TileRowRec];
TamarinEUImpl:
CEDAR
PROGRAM
IMPORTS CoreCreate, PWCore, Sisyph, TamarinUtil, TilingClass
EXPORTS Tam =
BEGIN OPEN CoreCreate;
extractFlag: BOOLEAN ← TRUE;
lastTile: TilingClass.TileArray ← NIL;
lastCellType: CellType ← NIL;
DataColumn:
PUBLIC
PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: CellType] = {
cellType ← IF extractFlag THEN Sisyph.ES["DataColumn.sch", tamarinCx] ELSE PWCore.Retrieve["DataColumn"];
};
CreateAdder:
PUBLIC PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: CellType] = {
NUMBITS: NAT = 32;
BlAndRip:
PROC [numRipples, index:
NAT]
RETURNS [] = {
tileArray[0][index] ←
NEW[TilingClass.TileRec ← [
type: block,
flatten: FALSE,
renaming:
LIST[["Vdd", "Vdd"], ["Gnd", "Gnd"], ["EUCondRes", "EUCondRes"],
["euCC", euCC], ["D1", D1[index]], ["D2", D2[index]],
["R", R[index]], ["SelAdder", SelAdder], ["DOADD", DoAdd[1]], ["DOSUB", DoAdd[0]]]
]];
FOR i:
NAT
IN [1..numRipples]
DO
tileArray[0][index-i] ←
NEW[TilingClass.TileRec ← [
type: ripple,
flatten: FALSE,
renaming:
LIST[["Vdd", "Vdd"], ["Gnd", "Gnd"], ["EUCondRes", "EUCondRes"],
["euCC", euCC], ["D1", D1[index-i]],
["D2", D2[index-i]], ["R", R[index-i]], ["SelAdder", SelAdder],
["DOADD", DoAdd[1]], ["DOSUB", DoAdd[0]]]
]];
ENDLOOP;
RETURN;
};
D1: Wire ← Seq["D1", NUMBITS];
D2: Wire ← Seq["D2", NUMBITS];
R: Wire ← Seq["R", NUMBITS];
euCC: Wire ← Seq["euCC", 2];
SelAdder: Wire ← Seq["SelAdder", 2];
CarryIn: Wire ← Seq["CarryIn", 2];
GKout: Wire ← Seq["GKout", 2];
Pout: Wire ← Seq["Pout", 2];
DoAdd: Wire ← Seq["DoAdd", 2];
Bcin: Wire ← Seq["Bcin", 2];
tileArray: TilingClass.TileArray ← NEW[TilingClass.TileArrayRec[1]];
block: Core.CellType ← Sisyph.ES["BlockAdder.sch", tamarinCx];
ripple: Core.CellType ← Sisyph.ES["RippleAdder.sch", tamarinCx];
i: NAT ← NUMBITS - 2;
j: NAT ← 1;
-- Start building at the middle stuff, then put on the least sig. side followed by the ms side
tileArray[0] ← NEW[TilingClass.TileRowRec[NUMBITS]];
I want the control over the actual placement of the cells
BlAndRip[1, 30];
BlAndRip[2, 28];
BlAndRip[3, 25];
BlAndRip[4, 21];
BlAndRip[5, 16];
BlAndRip[5, 10];
BlAndRip[3, 4];
tileArray[0][
NUMBITS-1] ←
NEW[TilingClass.TileRec ← [
type: block,
flatten: FALSE,
renaming:
LIST[["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", D1[
NUMBITS-1]],
["D2", D2[NUMBITS-1]],
["R", R[NUMBITS-1]], ["EUCondRes", "EUCondRes"], ["euCC", euCC],
["SelAdder", SelAdder], ["DOADD", DoAdd[1]],
["DOSUB", DoAdd[0]], ["NGKIN", "Gnd"], ["GKIN", "Vdd"],
["PIN", "Vdd"], ["NPIN", "Gnd"], ["CIN", CarryIn[1]], ["NCIN", CarryIn[0]]]
]];
tileArray[0][0] ←
NEW[TilingClass.TileRec ← [
type: ripple,
flatten: FALSE,
renaming:
LIST[["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", D1[0]], ["D2", D2[0]],
["R", R[0]], ["EUCondRes", "EUCondRes"], ["euCC", euCC],
["SelAdder", SelAdder], ["NGKOUT", GKout[0]], ["GKOUT", GKout[1]],
["POUT", Pout[1]], ["NPOUT", Pout[0]], ["NCIN2", Bcin[0]], ["CIN2", Bcin[1]],
["DOADD", DoAdd[1]], ["DOSUB", DoAdd[0]], ["SUM", "sum0"]]
]];
lastTile ← tileArray;
lastCellType ← cellType ← TilingClass.CreateTiling[
name: "AdderCore",
public: WireList[
LIST[
D1,
D2, R, "Vdd", "Gnd", DoAdd, CarryIn,
SelAdder, GKout, Pout, Bcin, "sum0", euCC, "EUCondRes"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};
CreateShifter:
PUBLIC PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: CellType] = {
Select: Wire ← Seq["Select", 16];
shResult: Wire ← Seq["shResult", 32];
D1Bus: Wire ← Seq["D1Bus", 32];
D2Bus: Wire ← Seq["D2Bus", 32];
shTopOut: Wire ← Seq["shTopOut", 32];
RBus: Wire ← Seq["RBus", 32];
spass: Wire ← Seq["spass", 16];
ShiftBotCtl: Wire ← Seq["ShiftBotCtl", 3];
SelShifter: Wire ← Seq["SelShifter", 2];
D1tBus: Wire ← Seq["D1t", 2];
D2tBus: Wire ← Seq["D2t", 2];
RtBus: Wire ← Seq["Rt", 2];
tileArray: TilingClass.TileArray ← NEW[TilingClass.TileArrayRec[18]];
-- 17 is the top and I'll start building there
tileArray[17] ← NEW[TilingClass.TileRowRec[33]];
FOR i:
NAT
IN [0..32)
DO
tileArray[17][i] ←
NEW[TilingClass.TileRec ← [
type: Sisyph.ES["ShiftTop.sch", tamarinCx],
flatten: FALSE,
renaming:
LIST[["Vdd", "Vdd"], ["Gnd", "Gnd"], ["D1", D1Bus[i]], ["D2", D2Bus[i]],
["R", RBus[i]]]
]];
ENDLOOP;
-- build the right edge
tileArray[17][32] ←
NEW[TilingClass.TileRec ← [
type: Sisyph.ES["ShiftTopR.sch", tamarinCx],
flatten: FALSE,
renaming: LIST[["Vdd", "Vdd"], ["Gnd", "Gnd"]]
]];
-- line n of shifter is tileArray[16-n]
FOR row:
NAT
DECREASING
IN [1..16]
DO
tileArray[row] ← NEW[TilingClass.TileRowRec[33]];
FOR i:
NAT
IN [0..31]
DO
tileArray[row][i] ←
NEW[TilingClass.TileRec ← [
type: Sisyph.ES["ShiftBase.sch", tamarinCx],
flatten: FALSE,
renaming: LIST[ ["Select", Select[16-row]] ]
]];
ENDLOOP;
-- build the right edge
tileArray[row][32] ←
NEW[TilingClass.TileRec ← [
type: Sisyph.ES["ShiftBaseR.sch", tamarinCx],
flatten: FALSE,
renaming: LIST[ ["Select", Select[16-row]] ]
]];
ENDLOOP;
-- 0 is the bottom
tileArray[0] ← NEW[TilingClass.TileRowRec[33]];
FOR i:
NAT
IN [0..31]
DO
tileArray[0][i] ←
NEW[TilingClass.TileRec ← [
type: Sisyph.ES["ShiftBottom.sch", tamarinCx],
flatten: FALSE,
renaming:
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"],
["D1", D1Bus[i]], ["D2", D2Bus[i]], ["R", RBus[i]], ["ShiftBotCtl", ShiftBotCtl],
["SelShifter", SelShifter] ]
]];
ENDLOOP;
tileArray[0][32] ←
NEW[TilingClass.TileRec ← [
type: Sisyph.ES["ShiftBottomR.sch", tamarinCx],
flatten: FALSE,
renaming:
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["SelShifter", SelShifter],
["ShiftBotCtl", ShiftBotCtl], ["D1t0", D1tBus[0]], ["D2t0", D2tBus[0]], ["Rt0", RtBus[0]], ["D1t1", D1tBus[1]], ["D2t1", D2tBus[1]], ["Rt1", RtBus[1]] ]
]];
lastTile ← tileArray;
lastCellType ← cellType ← TilingClass.CreateTiling[
name: "BarrelShifter",
public: Wires[D1Bus, D2Bus, RBus, D1tBus, D2tBus, RtBus, "Vdd", "Gnd", Select, ShiftBotCtl, SelShifter],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};
CreateShiftTag:
PUBLIC
PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: CellType] = {
pos: NAT ← 0;
D1: Wire ← TamarinUtil.MakeDataBus["D1"];
D2: Wire ← TamarinUtil.MakeDataBus["D2"];
R: Wire ← TamarinUtil.MakeDataBus["R"];
SelTag: Wire ← Seq["SelTag", 2];
TagControl: Wire ← Seq["TagControl", 4];
SelTagShift: Wire ← Seq["SelTagShift", 2];
ShiftMerge: Wire ← Seq["ShiftMerge", 2];
Extract all of the cells once
ShiftTagTopCT: Core.CellType ← Sisyph.ES["ShiftTagTop.sch", tamarinCx];
ShiftTagMidCT: Core.CellType ← Sisyph.ES["ShiftTagMid.sch", tamarinCx];
ShiftTagMidBCT: Core.CellType ← Sisyph.ES["ShiftTagMidB.sch", tamarinCx];
ShiftTagBotCT: Core.CellType ← Sisyph.ES["ShiftTagBot.sch", tamarinCx];
ShiftTagTagCT: Core.CellType ← Sisyph.ES["ShiftTagTag.sch", tamarinCx];
tileArray: TilingClass.TileArray ← NEW[TilingClass.TileArrayRec[1]];
tileArray[0] ← NEW[TilingClass.TileRowRec[34]];
FOR i:
NAT
IN [pos..pos+5)
DO
pos ← pos + 1;
tileArray[0][i] ←
NEW[TilingClass.TileRec ← [
type: ShiftTagTopCT,
renaming:
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"],
["R", R[1][i]], ["D1", D1[1][i]], ["D2", D2[1][i]] ]
]];
ENDLOOP;
FOR i:
NAT
IN [pos..pos+20)
DO
pos ← pos + 1;
tileArray[0][i] ←
NEW[TilingClass.TileRec ← [
type: ShiftTagMidCT,
renaming:
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"],
["R", R[1][i]], ["D1", D1[1][i]], ["D2", D2[1][i]] ]
]];
ENDLOOP;
FOR i:
NAT
IN [pos..pos+2)
DO
pos ← pos + 1;
tileArray[0][i] ←
NEW[TilingClass.TileRec ← [
type: ShiftTagMidBCT,
renaming:
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"],
["R", R[1][i]], ["D1", D1[1][i]], ["D2", D2[1][i]] ]
]];
ENDLOOP;
FOR i:
NAT
IN [pos..pos+5)
DO
pos ← pos + 1;
tileArray[0][i] ←
NEW[TilingClass.TileRec ← [
type: ShiftTagBotCT,
renaming:
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"],
["R", R[1][i]], ["D1", D1[1][i]], ["D2", D2[1][i]] ]
]];
ENDLOOP;
FOR i:
NAT
IN [pos..pos+2)
DO
pos ← pos + 1;
tileArray[0][i] ←
NEW[TilingClass.TileRec ← [
type: ShiftTagTagCT,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"], ["SelTag", SelTag], ["TagControl", TagControl], ["SelTagShift", SelTagShift], ["ShiftMerge", ShiftMerge],
["R", R[0][i-32]], ["D1", D1[0][i-32]], ["D2", D2[0][i-32]] ]
]];
ENDLOOP;
lastTile ← tileArray;
lastCellType ← cellType ← TilingClass.CreateTiling[
name: "TagShift",
public: WireList[LIST[D1, D2, R, SelTag, TagControl, SelTagShift, ShiftMerge, "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};
CreateLU:
PUBLIC
PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: CellType] = {
pos: NAT ← 0;
D1: Wire ← Seq["D1", 32];
D2: Wire ← Seq["D2", 32];
R: Wire ← Seq["R", 32];
SelLU: Wire ← Seq["SelLU", 2];
LUEuop: Wire ← Seq["LUEuop", 4];
Extract all of the cells once
LuCT: Core.CellType ← Sisyph.ES["LogicalUnit.sch", tamarinCx];
tileArray: TilingClass.TileArray ← NEW[TilingClass.TileArrayRec[1]];
tileArray[0] ← NEW[TilingClass.TileRowRec[32]];
FOR i:
NAT
IN [0..32)
DO
tileArray[0][i] ←
NEW[TilingClass.TileRec ← [
type: LuCT,
renaming:
LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"],
["R", R[i]], ["D1", D1[i]], ["D2", D2[i]], ["LUEuop", LUEuop], ["SelLU", SelLU] ]
]];
ENDLOOP;
lastTile ← tileArray;
lastCellType ← cellType ← TilingClass.CreateTiling[
name: "TagShift",
public: WireList[LIST[D1, D2, R, SelLU, LUEuop, "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};
ShiftDecode:
PUBLIC PROC [numBits:
NAT, tamarinCx: Sisyph.Context]
RETURNS [cellType: CellType] = {
twoToTheN: ARRAY [0..8] OF NAT = [1, 2, 4, 8, 16, 32, 64, 128, 256];
numCols: NAT ← (2 * numBits) + 2;
numRows: NAT ← twoToTheN[numBits];
bit: Wire ← Seq["bit", numBits];
out: Wire ← Seq["out", numRows];
Sel: Wire ← Seq["Sel", numBits];
nSel: Wire ← Seq["nSel", numBits];
Extract all of the cells once
DTransCT: Core.CellType ← Sisyph.ES["DecTrans.sch", tamarinCx];
DBlankCT: Core.CellType ← Sisyph.ES["DecBlank.sch", tamarinCx];
DEndCT: Core.CellType ← Sisyph.ES["DecEnd.sch", tamarinCx];
DInvCT: Core.CellType ← Sisyph.ES["DecInv.sch", tamarinCx];
bitVals: NAT;
tileArray: TilingClass.TileArray ← NEW[TilingClass.TileArrayRec[numRows]];
FOR i:
NAT
IN [0..numRows)
DO
tileArray[i] ← NEW[TilingClass.TileRowRec[numCols]];
Put on the two ends
tileArray[i][0] ←
NEW[TilingClass.TileRec ← [
type: DInvCT,
flatten: FALSE,
renaming: LIST[["Vdd", "Vdd"], ["Gnd", "Gnd"], ["out", out[i]]]
]];
tileArray[i][numCols-1] ←
NEW[TilingClass.TileRec ← [
type: DEndCT,
flatten: FALSE,
renaming: LIST[["Vdd", "Vdd"], ["Gnd", "Gnd"]]
]];
Now do the guts
bitVals ← i;
FOR j:
NAT
DECREASING
IN [0..numBits)
DO
bit: BOOL ← LOOPHOLE[(bitVals MOD 2), BOOL];
IF bit
THEN {
tileArray[i][2*j + 1] ←
NEW[TilingClass.TileRec ← [
type: DBlankCT,
flatten: FALSE,
renaming: LIST[["Gnd", "Gnd"], ["sel", Sel[j]]]
]];
tileArray[i][2*j + 2] ←
NEW[TilingClass.TileRec ← [
type: DTransCT,
flatten: FALSE,
renaming: LIST[["Gnd", "Gnd"], ["sel", nSel[j]]]
]];
}
ELSE {
tileArray[i][2*j + 1] ←
NEW[TilingClass.TileRec ← [
type: DTransCT,
flatten: FALSE,
renaming: LIST[["Gnd", "Gnd"], ["sel", Sel[j]]]
]];
tileArray[i][2*j + 2] ←
NEW[TilingClass.TileRec ← [
type: DBlankCT,
flatten: FALSE,
renaming: LIST[["Gnd", "Gnd"], ["sel", nSel[j]]]
]];
};
bitVals ← bitVals/2;
ENDLOOP;
ENDLOOP;
lastTile ← tileArray;
lastCellType ← cellType ← TilingClass.CreateTiling[
name: "ShiftDecode",
public: Wires[out, Sel, nSel, "Vdd", "Gnd"],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY
];
};
END.