CreateSpecRegConstants:
PUBLIC
PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: Core.CellType] = {
ccWordLength: NAT = 34;
constSel: Wire;
d1Bus: Wire ← TamarinUtil.MakeDataBus["D1"];
d2Bus: Wire ← TamarinUtil.MakeDataBus["D2"];
rBus: Wire ← TamarinUtil.MakeDataBus["R"];
d1res: Wire ← TamarinUtil.MakeDataBus["d1res"];
d2res: Wire ← TamarinUtil.MakeDataBus["d2res"];
d1Constants: LORA;
d2Constants: LORA;
specRegD1Rows: NAT;
specRegD2Rows: NAT;
ct: Core.CellType;
specRegConst11: Core.CellType ← Sisyph.ES["SpecRegConst11.sch", tamarinCx];
specRegConstD10: Core.CellType ← Sisyph.ES["SpecRegConstD10.sch", tamarinCx];
specRegConstD20: Core.CellType ← Sisyph.ES["SpecRegConstD20.sch", tamarinCx];
tileArray: TilingClass.TileArray;
rowIndex: NAT ← 0;
[d1Constants, d2Constants] ← TamarinUtil.GetSpecRegConstants[];
specRegD1Rows← List.Length[d1Constants];
specRegD2Rows← List.Length[d2Constants];
constSel ← CoreCreate.Seq["constSel", specRegD1Rows+specRegD2Rows];
tileArray ← NEW[TilingClass.TileArrayRec[specRegD1Rows+specRegD2Rows]];
FOR const:
LORA ← d1Constants, const.rest
UNTIL const=
NIL
DO
constElt: TamarinUtil.SpecRegConstant ← NARROW[const.first];
tileArray[rowIndex] ← NEW[TilingClass.TileRowRec[ccWordLength]];
FOR bit:
NAT
IN [0..ccWordLength)
DO
ct ← (IF TamarinUtil.RopeBitOnP[constElt.val, bit]
THEN specRegConst11 ELSE specRegConstD10);
tileArray[rowIndex][bit] ←
NEW[TilingClass.TileRec ← [type: ct,
flatten: FALSE,
renaming: LIST[ ["D1", TamarinUtil.DataBusToWire[d1Bus, bit]], ["D2", TamarinUtil.DataBusToWire[d2Bus, bit]], ["R", TamarinUtil.DataBusToWire[rBus, bit]], ["d1res", TamarinUtil.DataBusToWire[d1res, bit]], ["d2res", TamarinUtil.DataBusToWire[d2res, bit]], ["Sel", constSel[rowIndex]], ["Gnd", "Gnd"]]]];
ENDLOOP;
rowIndex ← rowIndex+1;
ENDLOOP;
FOR const:
LORA ← d2Constants, const.rest
UNTIL const=
NIL
DO
constElt: TamarinUtil.SpecRegConstant ← NARROW[const.first];
tileArray[rowIndex] ← NEW[TilingClass.TileRowRec[ccWordLength]];
FOR bit:
NAT
IN [0..ccWordLength)
DO
ct ← (IF TamarinUtil.RopeBitOnP[constElt.val, bit]
THEN specRegConst11 ELSE specRegConstD20);
tileArray[rowIndex][bit] ←
NEW[TilingClass.TileRec ← [type: ct,
flatten: FALSE,
renaming: LIST[ ["D1", TamarinUtil.DataBusToWire[d1Bus, bit]], ["D2", TamarinUtil.DataBusToWire[d2Bus, bit]], ["R", TamarinUtil.DataBusToWire[rBus, bit]], ["d1res", TamarinUtil.DataBusToWire[d1res, bit]], ["d2res", TamarinUtil.DataBusToWire[d2res, bit]], ["Sel", constSel[rowIndex]], ["Gnd", "Gnd"]]]];
ENDLOOP;
rowIndex ← rowIndex+1;
ENDLOOP;
cellType ← TilingClass.CreateTiling[
name: "SpecRegConstants",
public: CoreCreate.WireList[LIST[constSel, d1Bus, d2Bus, rBus, d1res, d2res, "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};
CreateDpCc:
PUBLIC
PROC [tamarinCx: Sisyph.Context]
RETURNS [cellType: Core.CellType] = {
ccWordLength: NAT = 34;
dpCcSelSize: NAT = 5;
d1Bus: Wire ← CoreCreate.Seq["D1", ccWordLength];
d2Bus: Wire ← CoreCreate.Seq["D2", ccWordLength];
rBus: Wire ← CoreCreate.Seq["R", ccWordLength];
selIn: Wire ← CoreCreate.Seq["SelIn", dpCcSelSize];
tags: LORA ← TamarinUtil.GetDpCondCodes[];
ccRows: NAT ← List.Length[tags]+1;
ct: Core.CellType;
ccBasect: Core.CellType ← Sisyph.ES["ccBase.sch", tamarinCx];
ccD10D2Xct: Core.CellType ← Sisyph.ES["ccD10D2X.sch", tamarinCx];
ccD11D2Xct: Core.CellType ← Sisyph.ES["ccD11D2X.sch", tamarinCx];
ccD1XD20ct: Core.CellType ← Sisyph.ES["ccD1XD20.sch", tamarinCx];
ccD10D20ct: Core.CellType ← Sisyph.ES["ccD10D20.sch", tamarinCx];
ccD11D20ct: Core.CellType ← Sisyph.ES["ccD10D20.sch", tamarinCx];
ccD1XD21ct: Core.CellType ← Sisyph.ES["ccD10D21.sch", tamarinCx];
ccD10D21ct: Core.CellType ← Sisyph.ES["ccD10D21.sch", tamarinCx];
ccD11D21ct: Core.CellType ← Sisyph.ES["ccD11D21.sch", tamarinCx];
ccD1eqD2ct: Core.CellType ← Sisyph.ES["ccD1eqD2.sch", tamarinCx];
dpCcDriver: Core.CellType ← Sisyph.ES["DpCcDriver.sch", tamarinCx];
dpCcSelDvr: Core.CellType ← Sisyph.ES["DpCcSelDvr.sch", tamarinCx];
dpCcDecode0: Core.CellType ← Sisyph.ES["DpCcDecode0.sch", tamarinCx];
dpCcDecode1: Core.CellType ← Sisyph.ES["DpCcDecode1.sch", tamarinCx];
dpCcSenseOut: Core.CellType ← Sisyph.ES["DpCcSenseOut.sch", tamarinCx];
dpCcSense: Core.CellType ← Sisyph.ES["DpCcSense.sch", tamarinCx];
rowIndex: NAT ← 0;
tileArray: TilingClass.TileArray ← NEW[TilingClass.TileArrayRec[ccRows]];
tileArray[ccRows-1] ← NEW[TilingClass.TileRowRec[ccWordLength+dpCcSelSize+1]];
FOR bit:
NAT
IN [0..ccWordLength)
DO
tileArray[ccRows-1][bit] ←
NEW[TilingClass.TileRec ← [type: dpCcDriver,
flatten: FALSE,
renaming: LIST[ ["D1", d1Bus[bit]], ["D2", d2Bus[bit]], ["R", rBus[bit]],
["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
FOR bit:
NAT
IN [0..dpCcSelSize)
DO
tileArray[ccRows-1][ccWordLength+bit] ←
NEW[TilingClass.TileRec ← [type: dpCcSelDvr,
flatten: FALSE,
renaming: LIST[ ["SelIn", selIn[bit]], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
tileArray[ccRows-1][ccWordLength+dpCcSelSize] ←
NEW[TilingClass.TileRec ← [type: dpCcSenseOut,
flatten: FALSE,
renaming: LIST[ ["SelOut", "SelOut"], ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
FOR tagList:
LORA ← tags, tagList.rest
UNTIL tagList=
NIL
DO
tagElt: TamarinUtil.DpCondCode ← NARROW[tagList.first];
tileArray[rowIndex] ← NEW[TilingClass.TileRowRec[ccWordLength+dpCcSelSize+1]];
FOR bit:
NAT
IN [0..ccWordLength)
DO
d1: BOOLEAN ← TamarinUtil.RopeBitOnP[tagElt.d1, bit];
d2: BOOLEAN ← TamarinUtil.RopeBitOnP[tagElt.d2, bit];
nD1: BOOLEAN ← TamarinUtil.RopeBitOnP[tagElt.nD1, bit];
nD2: BOOLEAN ← TamarinUtil.RopeBitOnP[tagElt.nD2, bit];
d1XorD2: BOOLEAN ← TamarinUtil.RopeBitOnP[tagElt.d1XorD2, bit];
SELECT
TRUE
FROM
(~d1 AND ~d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct ← ccBasect};
(~d1 AND ~d2 AND nD1 AND ~nD2 AND ~d1XorD2) => {ct ← ccD10D2Xct};
(d1 AND ~d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct ← ccD11D2Xct};
(~d1 AND ~d2 AND ~nD1 AND nD2 AND ~d1XorD2) => {ct ← ccD1XD20ct};
(~d1 AND ~d2 AND nD1 AND nD2 AND ~d1XorD2) => {ct ← ccD10D20ct};
(d1 AND ~d2 AND ~nD1 AND nD2 AND ~d1XorD2) => {ct ← ccD11D20ct};
(~d1 AND d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct ← ccD1XD21ct};
(~d1 AND d2 AND nD1 AND ~nD2 AND ~d1XorD2) => {ct ← ccD10D21ct};
(d1 AND d2 AND ~nD1 AND ~nD2 AND ~d1XorD2) => {ct ← ccD11D21ct};
(~d1 AND ~d2 AND ~nD1 AND ~nD2 AND d1XorD2) => {ct ← ccD1eqD2ct};
ENDCASE => ERROR;
tileArray[rowIndex][bit] ←
NEW[TilingClass.TileRec ← [type: ct,
flatten: FALSE,
renaming: LIST[ ["Gnd", "Gnd"]]]];
ENDLOOP;
FOR bit:
NAT
IN [0..dpCcSelSize)
DO
tileArray[rowIndex][ccWordLength+bit] ←
NEW[TilingClass.TileRec ←
[type: (IF TamarinUtil.BitOnP[tagElt.index, bit] THEN dpCcDecode1 ELSE dpCcDecode0),
flatten: FALSE,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
ENDLOOP;
tileArray[rowIndex][ccWordLength+dpCcSelSize] ←
NEW[TilingClass.TileRec ← [type: dpCcSense,
flatten: FALSE,
renaming: LIST[ ["Vdd", "Vdd"], ["Gnd", "Gnd"]]]];
rowIndex ← rowIndex + 1;
ENDLOOP;
lastTile ← tileArray;
IF rowIndex # (ccRows-1) THEN ERROR;
cellType ← TilingClass.CreateTiling[
name: "DpCc",
public: CoreCreate.WireList[LIST[d1Bus, d2Bus, rBus, selIn,
"DpCcCondRes", "Vdd", "Gnd"]],
tileArray: tileArray,
neighborX: TilingClass.SchematicsNeighborX,
neighborY: TilingClass.SchematicsNeighborY];
};