<> <<>> DIRECTORY CD, Core, CoreCreate, CoreOps, Rope, CoreClasses, ProcessProps, Commander, IO; MakeESim: CEDAR PROGRAM IMPORTS ProcessProps, IO, CoreClasses, CoreOps, Rope = BEGIN RemapRec: TYPE = RECORD [public, global: Rope.ROPE]; RemapEntry: TYPE = REF RemapRec; RemapList: TYPE = LIST OF RemapEntry; RemapTable: TYPE = LIST OF RemapList; eSimStrean: IO.STREAM _ NARROW [ProcessProps.GetProp[$CommanderHandle], Commander.Handle].out; count: NAT; GlobalWireName: PROC [wire: Core.Wire, remap: RemapTable] RETURNS [wirename: Rope.ROPE] = { <> }; MakeRemapTable: PROC [actual, public: Core.WireSeq, remap: RemapTable] RETURNS [newRemap: RemapTable] = { <> }; PrintTransistor: PROC [ct: Core.CellType, remap: RemapTable] = { tran: CoreClasses.Transistor _ NARROW[ct.data]; IO.PutF[eSimStrean, "\nTransister: %g, length: %g, width: %g", [rope[CoreClasses.transistorTypeNames[tran.type]]], [integer[tran.length]], [integer[tran.width]] ]; count _ count + 1; < 100 THEN ERROR;>> }; PrintCellType: PROC [ct: Core.CellType, remap: RemapTable] = { className: Rope.ROPE _ ct.class.name; <> <<>> IO.PutF[eSimStrean, "\nCell: %g: %g", [rope[CoreOps.GetCellTypeName[ct]]], [rope[className]] ]; WHILE ct.class.recast # NIL DO IO.PutF[eSimStrean, "\nDown layer of %g: %g", [rope[CoreOps.GetCellTypeName[ct]]], [rope[className]] ]; ct _ ct.class.recast[ct]; className _ ct.class.name ENDLOOP; <<>> SELECT TRUE FROM Rope.Equal["Record",className] => PrintCellRecord[NARROW[ct.data], remap]; Rope.Equal["Transistor",className] => PrintTransistor[ct, remap]; ENDCASE => {IO.PutF[eSimStrean," ... Unknown Cell "]; ERROR;}; }; PrintCellRecord: PROC [crec: CoreClasses.RecordCellType, remap: RemapTable] = { IO.PutF[eSimStrean,"\nCellRecord"]; FOR i: NAT _ 0, i + 1 WHILE i < crec.size DO PrintCellInstance[crec.instances[i], remap]; ENDLOOP; }; PrintCellInstance: PROC [cinst: CoreClasses.CellInstance, remap: RemapTable] = { PrintCellType[cinst.type, remap]; }; ExtractESim: PROC [ct: Core.CellType, filename: Rope.ROPE] = { <> }; END.