MakeESim:
CEDAR
PROGRAM
IMPORTS ProcessProps, IO, CoreClasses, CoreOps, Rope =
BEGIN
RemapRec: TYPE = RECORD [public, global: Rope.ROPE];
RemapEntry: TYPE = REF RemapRec;
RemapList: TYPE = LIST OF RemapEntry;
RemapTable: TYPE = LIST OF RemapList;
eSimStrean: IO.STREAM ← NARROW [ProcessProps.GetProp[$CommanderHandle], Commander.Handle].out;
count: NAT;
GlobalWireName:
PROC [wire: Core.Wire, remap: RemapTable]
RETURNS [wirename: Rope.
ROPE] = {
See if wire name is in the 1st remap table. If so then return the remapped name, else return the given name.
};
MakeRemapTable:
PROC [actual, public: Core.WireSeq, remap: RemapTable]
RETURNS [newRemap: RemapTable] = {
Map the public wires to the actual names. Check if the actual names are themselves re-mapped at a lower level in the remap table, and place the most global name with the public in the remap table. Format of the table is:
{[(public name, globalname), ... (...)], [(public name, globalname), ... (...)], ... [...] }
};
PrintTransistor:
PROC [ct: Core.CellType, remap: RemapTable] = {
tran: CoreClasses.Transistor ← NARROW[ct.data];
IO.PutF[eSimStrean,
"\nTransister: %g, length: %g, width: %g",
[rope[CoreClasses.transistorTypeNames[tran.type]]],
[integer[tran.length]],
[integer[tran.width]]
];
count ← count + 1;
IF count > 100 THEN ERROR;
};
PrintCellType:
PROC [ct: Core.CellType, remap: RemapTable] = {
className: Rope.ROPE ← ct.class.name;
remap ← MakeRemapTable[];
IO.PutF[eSimStrean,
"\nCell: %g: %g",
[rope[CoreOps.GetCellTypeName[ct]]],
[rope[className]]
];
WHILE ct.class.recast #
NIL
DO
IO.PutF[eSimStrean,
"\nDown layer of %g: %g",
[rope[CoreOps.GetCellTypeName[ct]]],
[rope[className]]
];
ct ← ct.class.recast[ct];
className ← ct.class.name
ENDLOOP;
SELECT
TRUE
FROM
Rope.Equal["Record",className] => PrintCellRecord[NARROW[ct.data], remap];
Rope.Equal["Transistor",className] => PrintTransistor[ct, remap];
ENDCASE =>
{IO.PutF[eSimStrean," ... Unknown Cell "]; ERROR;};
};
PrintCellRecord:
PROC [crec: CoreClasses.RecordCellType, remap: RemapTable] = {
IO.PutF[eSimStrean,"\nCellRecord"];
FOR i:
NAT ← 0, i + 1
WHILE i < crec.size
DO
PrintCellInstance[crec.instances[i], remap];
ENDLOOP;
};
PrintCellInstance:
PROC [cinst: CoreClasses.CellInstance, remap: RemapTable] = {
PrintCellType[cinst.type, remap];
};
ExtractESim:
PROC [ct: Core.CellType, filename: Rope.
ROPE] = {
For i in ct.instances do ....
};
END.