* --------------------------------------------------------; * Tamarin test microcode * for * CMOS Chip I * FILE: {PHYLUM}EMULATOR>TESTUCODE2.tedit * --------------------------------------------------------; * -------------------------------------------------------- * Copyright (c) 1987 Xerox Corporation * All rights reserved. * -------------------------------------------------------- * Test UCode to test the Processor; Label_Reset Aside OpLength_0 MemOp_Map EUop_D1 Tag_Int RD1addr_MuxBus_K_0 RD2addr_MuxBus W2addr_Temp1 Raddr_K RCxt Waddr_K WCxt WriteOctal MemOffset_MuxBus MemLatchSrc_MapAddr PhysAddrSrc_PhysAddr LatchFetchPc PcSrc_D1 NewArg_MuxBus NewArg2_MuxBus NewTos_MuxBus NewBotCxt AltCxt_K NewTopCxt; MemOp_Map EUop_D2 Tag_Int NewTos_MuxBus_K_2 NewArg_MuxBus Raddr_K RCxt Waddr_K WCxt AltCxt_K RD1addr_MuxBus RD2addr_MuxBus W2addr_Temp1 MemOffset_K2_1 MemLatchSrc_PhysAddr PhysAddrSrc_PhysAddr; Label_Loop MemOp_Map EUop_+ Tag_Int RD1addr_Temp1 W2addr_Temp1 WriteData RD2addr_MuxBus_Arg NewArg_Arg+1 Raddr_K RCxt Waddr_K WCxt AltCxt_K_2 MemOffset_K2_1 MemLatchSrc_PhysAddr PhysAddrSrc_PhysAddr MuxCCode_Arg#0 EuCCode_NoOverflow JumpT_Loop JumpF_Next; Label_Next Aside OpLength_0 MemOp_Map EUop_D1 Tag_Int RD1addr_MuxBus_K_0 RD2addr_MuxBus W2addr_Temp1 Raddr_K RCxt Waddr_K WCxt WriteOctal MemOffset_MuxBus MemLatchSrc_MapAddr PhysAddrSrc_PhysAddr LatchFetchPc PcSrc_D1 NewArg_MuxBus NewArg2_MuxBus NewTos_MuxBus NewBotCxt AltCxt_K NewTopCxt JumpT_Reset; Label_Noop Aside OpLength_0 JumpT_Noop; Label_Interrupt1 OpLength_0 JumpT_Done; Label_Interrupt2 OpLength_0 JumpT_Done; Label_AdjustFrames OpLength_0 JumpT_Done; Label_RefCount OpLength_0 JumpT_Done; End; PreConditions OpNbr_0 Reset RefCount AdjustFrames Interrupt1 Interrupt2; UniStart OpNbr_200Q; OpName_-X- Start_Go; End; GACHA——zş