Tamarin: A Custom VLSI-Based Lisp Machine January 29, 1987 Tamarin A Custom VLSI-Based Lisp Machine Mark Ross January 29, 1987 Presentation to Fuji-Xerox Outline Project Philosophy and Goals System Configurations Lisp Architecture Project Status Project Philosophy and Goals AISBU needs an improved delivery vehicle for its Lisp system · Performance must be improved · Cost/performance must come down · Size reduction would be helpful Specialized architectures can improve Lisp performance Project Philosophy and Goals (cont.) Goals: · Build an initial Lisp System Product · Develop a Custom VLSI Processor Provide specific support for Xerox Lisp Improve performance over a 6085/1186 by 5X Require a minimum of "glue" chips · Create a Technology base for a series of VLSI Lisp machines Path for future performance enhancements Adaptable to many system configurations System Configurations 1186 Softcard PC-AT Softcard Embedded system Highly parallel architecture SoftCard Concept Example of 1186 SoftCard Lisp Architecture - Mismatches Premise: Specialized architectures can improve Lisp performance Performance Mismatches: · 16 bit word vs. full pointer · Hardware stack · Bottle-neck at instruction fetching · Ineffecient Memory coupling · Slow Virtual Memory Translation Lisp Architecture - Requirements Special Requirements of Lisp: · Micro Conditionality · Complex Function Call · Tagged Pointers and Typed Data · Dynamic Scoping · Common Lisp Multiple Values Closures Function Arguments Lexical Scoping Tamarin Specifics Tamarin Addresses the previously mentioned issues with several key constructs (general and Lisp specific) General: · Hardware stacks and stack operations · Instruction Buffer · Unique Micro Code Implementation · Close Memory Coupling (fast block transfers) · Virtual Memory Map Cache (TLB) Lisp Specific: · 40 bit architecture (tag is built in to data word) · Function Call Support · Common Loops support · Binding Stack support Tamarin Feature Summary The following is a partial list of the features present in the CMOS Tamarin processor · Stack Frame structure : 6 frames X 40 words per frame · Instruction Timing 3 stage pipeline · Functional Units Memory Controller General ALU and Shifter Multiplier/Divider Micro-Code ROM Register Control Processor Block Diagram A Word on RISC Tamarin as a RISC machine · Many instructions execute in one micro-instruction per opcode. The ones that don't would require multiple cycle implementations on a standard RISC machine (e.g., Lisp Function Call) · Many internal registers · Simple Instructions and single addressing mode. Tamarin is at least a FISC machine (Fast Instruction Set Computer) Project Status NMOS chip is back from fabrication Testing of the processor is starting There are signs of life from the Memory Interface chip NMOS design effort was complete Micro-code was completed Much simulation was performed CMOS chip development is continuing A display controller board for the 6085 using the TI 34010 graphics controller is under development Hardware Development Team Alan Bell Project Leader, system arch. Bob Krivacic Microcode & support software Chuck Sainsbury Mask Layout & board layout Celeste Chapman System Level engineering Mark Ross Architecture and primary CMOS designer Slide Title Point of the presentation · Bullet of the presentation, · is a bullet char Indented point of the presentation Centered point of the presentation Centered point of the presentation Centered point of the presentation Centered point of the presentation Centered point of the presentation Κ’–"slides" style– PressFonts˜Iunleaded•Mark insideFooteršΡdis*˜*K– outsideFooterš˜title˜)ragged˜M˜M˜M˜ M˜M˜M˜˜˜M˜M˜M˜M˜M˜————šœ˜M˜˜