Tamarin: A Custom VLSI-Based Lisp Machine
March 26,1987
Tamarin
Lisp Architecture
Mark Ross
March 26, 1987
Design Review Presentation
Outline
Block Diagram
Detailed block description
Timing details
Processor Block Diagram
Details of the PC and IBuf
Tamarin Feature Summary
· Register File :
6 frames X 40 words per frame (plus a global frame). Static Ram 8T (extra read xstors)
· Execution Units
Multiplier
Adder
Funnel Shifter (64 to 32 bits)
Priority Encoder (finds the first one)
Logical Unit
Feature Summary (cont.)
· Microcode ROM
Double bank implementation (2 Micro-instructions fetched per cycle. Mux decides which to use.)
· Instruction Buffer and PC logic
32 byte instruction buffer. Variable priority instruction fetch. Inst. buffer bypassing on jump.
· Memory Controller
On chip TLB (16 entries)
Supports burst mode (multi-cycle) reads and writes. Directly computes RAS and CAS.
Background instruction fetching (fetch is generally transparent).
Timing Issues
The Tamarin CMOS processor uses a two stage instruction pipeline. Timings for various operations are shown below:
· Generic instruction rate = 1 instruction per clock cycle
· Single word read or write = 3 cycles
· Multiple (n) word read or write = 3 + (n-1) cycles
· Page relative Jump = 4 or 5 cycles (depends on jump target address)
· Off Page Jump = 5 or 6 cycles (depends on jump target address)
· Function Call = > 11 cycles
Historical Perspective
Comparison of the CMOS and nMOS Tamarin processors:
· Word size - 40 bits vs. 32 bits
· Cycle time - 80 ns vs. 300 ns.
· 6 frames X 40 words vs. 4 frames X 40 words
· Synchronous memory coupling vs. asynchronous delay line.
· 16 entry TLB vs. 10 entry TLB
· Multiplier and increased number of functional units
· no cycle penalty for micro-conditional sequencing vs. 1 cycle penalty