Instruction and Memory Timing
The Tamarin CMOS processor uses a two stage instruction pipeline. Its first stage performs instruction fetch and decode while the second stage performs instruction execution. Timings for various operations are shown below:
· Generic instruction rate = 1 instruction per clock cycle
· Single word read or write = 3 cycles
· Multiple (n) word read or write = 3 + (n-1) cycles
· Page relative Jump = 5 cycles
· Off Page Jump = 6 cycles
· Function Call = > 11 cycles
Instruction and Memory Timing (cont).
Normal:
Fetch & Dec| Execute
Fetch & Dec| Execute
Mem. read/write:
F & D| Ex
F & D| Map | RAS/CAS | Wt. Back | Dead
F & D| Ex
Functional Units (cont.)
· Microcode ROM
Double bank implementation (2 Micro-instructions fetched per cycle. Mux decides which to use.)
· Instruction Buffer and PC logic
32 byte instruction buffer. Continuous, low priority fetch. Inst. buffer bypassing on jump.
· Memory Controller
On chip TLB (16 entries)
Supports burst mode (multi-cycle) reads and writes. Directly computes RAS and CAS.
Offset is used for adjusting fetch address (this is always page-relative).
Background instruction fetching (fetch is generally transparent).
Critical Path Timing
Two paths compete: one for decode and one for execution.
Decode Path:
Read words from inst buffer
Extract OpCode and IBufN
Present the micro-PCs to UCode Rom
Fetch from UCode Rom
Mux. the MI words. (requires condition code)
Store in register.
Execution Path:
Read words from Ram
Perform operation (Add is the worst case).
Get condition code
Conditional Write-back to reg. file (based on Cond. code)