{Phylum}<CTamarin>Doc>Details.tedit
11/18/87


CMOS 1 (Details to finish current chip):

- Global Control Flags & Preconditions: (Reset, Irq1, Irq2, StackOverFlow, Reference Count, Output Interrupt).  Change the pre-condition ordering so that NotOpValid is the lowest priority.  Add precondition logic for StackOverFlow & Reference Count.

- Finish Virtual Memory TLB.  Determine who detects a TLB miss and who/how it gets refilled.  Also how PageFault, ReadWriteAccess, Dirty, etc interract.

- Memory Controller:

	* Use NEXT state to determine Ras & Cas.
	* Latched state is what happened on the previous cycle.
	* Allow a PcRas after a Map cycle (necessary for jumps & fn calls).

The memory controller wastes too many cycles.  Counting the Map of a PC address, it takes 5 cycles before the 1st IBuf Word is read: Map, Data, Idle, PcRas, PcCas. (Remember that it takes 3 Reads before execution begins). This can even be worse (by 2 cycles) if a PcCas is to occur on the 1st cycle of the Map microinstruction.  There should only be 3 cycles from map to 1st read: Map, PcRas, PcCas.  (This is still a 6 cycle jump latency, after the new PC has been determined).

- Memory Buffer:  The Tags are written from the lower bits of D2.  It might be better to write the tags from the MuxBus so that all 40 bits can be written at once.  Possibly usefull for clearing out new objects.

- Move CLink, Code Pointer, Binding Stack, Flag/Tos Word, & PC to Reg Locations 59..63 (-5..-1), to free up the VarK space in reg file.

- Writeback of T/Nil (or just Nil) on condition code.  Would save cycles in comparison opcodes such as GREATERP, EQ, etc.  What might be needed is an EUop which would place T or Nil onto the RBus depending on the DpCondRes (for True / False comparisons like GREATERP, EQ), and an EUop which would place D1 or Nil onto the RBus (for value / Nil comparisons like ?). For function call, depending on how things fall out having the Register File be able to write from either the RBus or Nil, depending on the DpCondRes may be helpfull.

- Allow RegMux registers the ability to Subtract 1 (i.e. NewTos_Tos-1).  This has been worked around in most cases, but it does cost cycles, noteably in the shift opcodes.

- Local Frame Flags & Tos (Multiple values, Catch Frame, etc):

	* Merge Tos with the flag word.
	* Retieve Tos from the flag word.
	* OR in previous frame's MV flag.
	* Method to set & test the flags.

  These issues can be worked around as follows:

* Use tag merge EU to merge Tos.  Works while tags are 7 bits, but the Flag word would be a Fix or Float depending on Tos.

* Use the tag shifter to retrieve Tos.

* Test the previous frame's MV flag & perform a logical or only when multiple values are expected.

* Can set with 1 cycle using logical or & IBufN, but it would take 2 (or 3 if no T/Nil writeback) to perform a logical and & then test for 0.

- Condition code to test Bit 3 of the Opcode (bits numbered: 76543210).  Part of the RegMux condition codes. (This could be done by placing Opcode on data bus & using a data path condition code, but it my cost an extra cycle to do it.  Used on exit from the method call microcode to determine how to  continue the funcition call).

- Reset of the VM TLB is not yet defined (assumed part of the memory control).

- May need 1 more bit in the Memory condition code to handle TLB misses.
 
- Have PcWriteOk (LAND nStall DpCondRes MuxCondRes) instead of (LAND nStall DpCondRes).   

- Put back ability to do Absolute jumps?  This requires having some of the Pc bits going into the AddrSel mux select when doing a jump of this type.  Note that there will still be a cycle delay since the address must first be latched, and then stored.  If this remains the case, then using then on-page jumps may not be any faster than doing a Map.

- Move the Preconditions to the upper half of the Opcode Address space (128 - 255), if the current method of using powers of 2 to indicate the addresses (i.e. 1, 2, 4, ...).

CMOS ? (Promised 3x DayBreak replacement board):

- 8 Stack Frames.

- 1.5 Cmos.

- Reg File Writeback Pipeline?

- BitBlt.

- External Floating Point Processor.

- 32 bit Pointers.

- Reference Counting.

- 512 words of UCode.

- 75 ns cycle time.

- 5x Daybreak (w/o writeback pipeline).

- Faster Jumps.

- Self contained display.


CMOS 1.5:

- Reg File Writeback Pipeline.

- Register Stacks Behind: PC, Tos, Flags, Binding Stack.

- 2 bit / cycle multiply with floating point controls.

- Memory Buffer with: Parity check, Ref Count / GC, DCR Coding, Inviz Ptrs.

- After the fact Abort for memory fetch.

- Overflow detect on shifter & multiplier.

- T/Nil writeback on CCode, not RBus (must be able to write T/Nil & JUST Nil).

- UCode subroutine calls.

- change IBuf timing (save 1 cycle on jumps & fn calls).

- larger number of frames.

- Better Memory Control.

CMOS 2.0:

- Static Ram cache.

- Larger TLB size (on or off chip).

- Jump ideas:

	* 1 cycle jumps (cache Opcode & IBufN of destination with jump).

	* Cache Return Instruction.

	* Force lower 6 bits of Fetch Pc to that of the Pc for absolute jumps?

- Fast context switch.

- Indirect Pointers.

- 4 way uJumps.


MICROCODE:

The microcode for the following opcodes has been entered and some of them partially tested.   

Constants: 		'T, 'NIL, '0, '1, 'Unbound, SICX, SICXX, ICONST, PCONST, SCONST, IMMCONST.


Variable Access:	VARK, VARK_, VARK_^, VARX, VARX_, GVAR, GVAR_, IREGX, IREGX_^, OVAR1.X, OVAR1.X_.
				Note: Should the stores (^) be store & pop (_^) instead?

Stack Operations:	COPY, SWAP, POP, MoveTos, SetTos.

Type Checking:		FIXP, FLOATP, POINTERP, IMMEDIATEP, CONSP, SYMBOLP, SUBTYPEP.N GETTYPEBITS, GETPTRBITS, SETTYPE.N SETSUBTYPE.  It is not clear if some of these opcodes (FIXP, FLOATP, etc) should return T or (Tos) when the condition is true. 

Comparisons:		EQ, EQUAL, EQL, =, GREATERP.

Arithmetic:		PLUS, ADDX, DIFFERENCE, SUBX, NEG.  Floating Point operations cause a Ufn.  Note: NEG should be able to operate on floats.

Logical:			LOGOR, LOGAND, LOGXOR, LOGNOT.

Shifts:			ARSH, LLSH.N, LRSH.N, LLSH, LRSH, DSHIFT.N, DSHIFT.

Address Calculation:	GETPTR.N, GETBASE.N, SYMBOLCELL.N, PUTPTR.N RPLPTR.N ADDBASE.

Lists:			CAR, CDR, SETF-CAR, SETF-CDR (full cons cells only).

Function Call:		FN0-7 (normal functions only), RET.

Ufn's:			A Ufn call was made of 1 argument.

Preconditons:		Interrupt, Refcount, & Stack Refill preconditions have not been tested, but code exists. RETENI & RETNP have not been re-coded.

Misc:				SETFLAGS, CLRFLAGS, TESTFLAGS, DISINT, ENBINT, MYCLINK, MYCLINK_ (^?) WRITEOCTALNIL WRITEOCTALUNBOUND.

Frame Handlers:		Frames were both pushed out & restored with the LoadFrame & DumpFrame routines.

Jumps:			JUMPX, FJUMPX, TJUMPX, JUMPK, TJUMPK, FJUMPK, JUMPXX, NJUMPX, NJUMPXX, T^JUMP F^JUMP (all are relative jumps & very slow).


The microcode for the following opcodes have not been entered or is some cases not yet designed.   

Free Variables: 	Free variable Lookup along with the associated variable access and binding stack opcodes has not yet been fully designed.

Type Opcodes:		TYPEP, UFNTYPEP.  These are the main type comparison opcodes.  The type system has not yet been decided.

Arithmetic:		ADC & SBC. Add & subtract operations for multi-word elements.

Function Call:		The tail, multiple-value, and re-use frame function calls have not been decided.  There has been no work done on APPLY or what to do about multiple-values either.  Method call & closure call have also been left out.

CDR Coding:		CDR coding is presumed to be out of the current chip.

Memory Allocation:	CONS, CREATECELL.  These opcodes depend heavily on the memory, CDR coding, & type system design.  No work so far.

Garbage Collection:	INCREFCOUNT, DECREFCOUNT, CMPLREFCOUNT.  Opcodes to assist the garbage collector.  Unfortunately the existing ref counting code cannot be shared with these opcodes.

Memory System:		PageFault, TLB miss, & TLB refill have not been worked through.  This waits on a better memroy controller & TLB.

Arg List:			NARGS, NTHARG, FINDKEY, & RESLIST.  Opcodes to manipulate the arglist.  Depend on the non existent arglist  overflow spec.

Processes:			CONTEXTSWITCH, CSTORE.  Context switch is still assumed to be done by changing the CLINK. 

Slot Access:		The opcodes to access Common-Loops objects have not been fully designed.  (There are some preliminary designs).


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