DRAFT Tamarin-1 DRAFT Stephen Purcell based on work and discussion by Alan Bell Bill vanMelle July 1985 Tamarin-1 Goals VLSI Lisp Processor Prototype Demo in 6-12 months 100% Higher Performance than DandeTiger Lower Cost than Daybreak Growth Path to Family of Products Engineering Response Schedule Development Resources and Cost Goal: Prototype Demo in 6-12 months Reduce uncertainty quickly Justify additional resources and costs Demonstrate at AAAI-86 Launch product timely Goal: 100% Higher Performance than DandeTiger At least 50% faster due to 32 or 40 bit word size At least 50% faster due to On-chip stack frames Technical Response 2 Custom Chips Lisp Processor Chip (LPC) Memory Interface Chip (MIC) Single Board for IBM PC Bus 4 MBytes Dynamic RAM IBM PC for I/O Goal: Growth Path to Family of Products Technology improvements: CMOS Software architecture improvements Floating Point hardware Reference Counting Assist Larger Virtual Memory Cdr coding Hashing Integrated I/0 Controllers for workstation Multiprocessor architecture Tamarin Bus Design (Look ma, no bus) Processor wants a close coupling to RAM chips Tamarin Bus is defined by the RAM chip pins Addresses and control are buffered Data pins are connected directly Arbitration for master-of-bus chip Master directly drives RAS and CAS timing Nibble mode DRAMS Bus Bandwidth Comparisons (bits per second) Floppy 0 .5 Mbps Hard disk AT 5 Mbps Ethernet 10 Mbps Total XT 8 Mbps 8 bits per 5 x 210 ns Total AT 20 Mbps 16 bits per 5 x 167 ns Tamarin bus 256 Mbps 4 (nibl) words per 500 ns Display 40 Mbps BitBlt RRW 20 Mbps (DLion, large area) BitBlt RRW 7 Mbps (memory writes only) Tamarin Stack Design . Accept enough complexity to get enough speed. Keep (at least) the active stack frame on-chip. On-chip registers are fastest and multi-ported. 32-64 words total (Header, VARS, Stack). Furthermore, keep 4 stack (0.5-1 KBytes) frames on-chip. Limits dump/restore overhead to 10%. Chose fixed frame size (50) rather than variable size. + Simplifies chip + Dedicated special registers: PC, StkDepth + Simple to decode absolute variable addresses) (except 2 bit frame number) -- Large frames overflow sooner (<1%) Stack Frame 8 Header words Flags, StkDepth, UseCnt PC Code Header Name Table CLink (caller) ALink (free variable access) Memory Extension Next Frame 20 Local Variables IVars Copied from caller (explain) PVars Initialized to UNBIND FVars Pointer to memory, initially UNBIND 20 Evaluation Stack words 48 Words Total Movable boundary between Variables and Stack Evolutionary Integration Strategy 0) DLispOps (instruction set) on DLion today 1) Extend DLispOps by TamarinOps emulator (in Lisp) Run in two modes with co-existing versions of: Stack Space and UFNs Function Definition Space Virtual Memory Map Compiled Code format and UFN Table Two EVAL functions for two emulators (no free variable lookup between worlds) 2) TamarinOps on DLion (emulator and debugger) 3) Tamarin Card on BusMaster and DLion 4) Tamarin Card in IBM-PC Software Tasks in Semi-Wizard Weeks Stage TamarinOps on DLion 9 wks Simulate Tamarin Lisp Processor Chip 8 wks Diagnostic Software (Preliminary Checkout) 7 wks Demo of windows on Tamarin Lisp Card 8 wks I/O Software on IBM PC and in Lisp 8 wks Stage TamarinOps on DLion 9 wks Detailed spec of 1st TamarinOps 1 wk Practice loadup in a fork 1 wk CdrCode OFF, 32 bit Pointer fields Explore Compiler; create newUnbind opcode 1 wk TamarinOps Compiler code generator & loader 1 wk Code TamarinOps emulator in Lisp 1 wk Debug call and return 1 wk Debug compiler, loader & emulator changes 1 wk Fight hard problems and unexpected delays 2 wks Simulate Tamarin Lisp Processor Chip 8 wks Recode Tamarin emulator more like the chip: Stack dumping and restoring 1 wk Instruction Fetch Unit 1 wk Virtual Map cache 1 wk Achieve "PLA code" compatability 1 wks Simulate the PLAs controlling the data paths 1 wks Capture test vectors 2 wks Fight hard problems and unexpected delays 1 wk Diagnostic Software (Preliminary Checkout) 7 wks General framework 1 wk MIC diagnostics 2 wks RAM diagnostics 1 wk LPC diagnostics 3 wks I/O Software on IBM PC and in Lisp 8 wks Init/Boot/Sysin 2 wks Lisp call to PC subroutines 2 wks Lisp call to PC BIOS (device drivers) 1 wk Lisp call to PC DOS 1 wk Device driver (heads) in Lisp 3 wks Disk, KeyboardMouse, Ether, Floppy, RS232 (LIST ((PAGE NIL NIL (0 0 612 792) ((FOLIO NIL (PARALOOKS (QUAD CENTERED) CHARLOOKS (SUPERSCRIPT 0 SIZE 8 FAMILY MODERN OVERLINE OFF STRIKEOUT OFF UNDERLINE OFF SLOPE REGULAR WEIGHT MEDIUM)) (270 36 72 36) NIL) (TEXT NIL NIL (72 72 468 648) NIL))) (PAGE NIL NIL (0 0 612 792) ((FOLIO NIL (PARALOOKS (QUAD CENTERED) CHARLOOKS (SUPERSCRIPT 0 SIZE 10 FAMILY GACHA OVERLINE OFF STRIKEOUT OFF UNDERLINE OFF SLOPE REGULAR WEIGHT MEDIUM)) (270 36 72 36) NIL) (TEXT NIL NIL (72 72 492 624) NIL))) (PAGE NIL NIL (0 0 612 792) ((FOLIO NIL (PARALOOKS (QUAD CENTERED) CHARLOOKS (SUPERSCRIPT 0 SIZE 10 FAMILY GACHA OVERLINE OFF STRIKEOUT OFF UNDERLINE OFF SLOPE REGULAR WEIGHT MEDIUM)) (270 36 72 36) NIL) (TEXT NIL NIL (72 72 492 624) NIL))))) $´´Æ $´Æ 0Î 0 0   $H¶ $TZx  MODERN€MODERN MODERNMODERNMODERN                        ,  $          $  (     - 3 1               !  $      ,    )  / - % # $ ,   ,',0()  .01*9&7-1'           !    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