IDEAS JUMPS Have RegisterFile Set 2 (or 1) condition codes: D1 value = NIL D2 value = NIL This way the condition code can be checked even if the value is not going out to the bus. Then the Jump conditionals can be: EUop_Plus OpLength_0 Raddr_Tos RD1addr_Pc RD2addr_MuxBus_Opcode<4> W2addr_Pc RegFileCondCode_D1=Nil WriteT JumpF_Done JumpT_Pause; Label_Pause JumpT_Done; Be Able To Dynamically Set OpLength On short jumps (of distance K): OpLength_MuxBus_Opcode<4> JumpT_Pause; May still need to pause 1 cycle since oplength is not latched in time for the decode. Unless we can say: OpLength_Opcode<4> JumpT_Done; Then we can have a short 1 cycle jump (ala our NOP of 0-4). This does not give us time to check the condition though, which would add another cycle. Unless we could set oplength depending on the value of a previous condition. (Which must be saved on interruts etc). PC Should go out to D1 & D2; & IBufData Should go to D1 & D2 The Negative jumps need Pc - Offset, which is D1- D2, The Tag logic uses D1=IBufData, D2=Taginfo when packing tags Frame Dumping uses D2_Pc when writing the Pc to memory Function Call Info - Assuming Binding Stack, Pc, and Flag word are moved to Frame by code (i.e. no pc/stack/bs arrays). - Can overlap ONE microinstruction with a new memory operation (i.e. Start Memory, free cycle, use memory). CALL Read DefCell / Set BS / Write Def into Frame slot 3 Set IVars NIL, Test page fault 1 Read SP / Save TOS / Write SP Info / Test CCodeP 3 Save PC 1 Read PC / Write 1 Fetch Instructions / Copy Args 4 -- 13 RETURN Get Old PC & Set 1 Fetch Instructions / Decode 4 -- 5 Fast Function Call - Assumes seperate Pc, Tos, & BS Arrays - Ability to write Ivars to NIL in parallel with other operatios - 1 cycle cache CALL Read DefCell / Set BS / Write Def/ Test Page Fault 1 Read Pc / Write Pc / Save Pc / Test CCodeP 1 Read SP / Save TOS / Write SP Info / Set IVars NIL 1 Fetch Instructions / Copy Args 1 -- 4 RETURN Get Old PC & Set 1 Fetch Instructions / Decode 2 -- 3 STACK FRAME LAODING & DUMPING The number of words required to save a frame are as follows: 8/16 for the IVARS 5 for PC, SP, BS, CLINK, & FN Ptr. x for PVARS & current stack depth. On the CMOS I chip the frame is laid out so that the 1st 16 slots are taken by IVARS & PVARS so that then must allways be saved during a Fn call. It would be nice to move the PVARS after the FN ptr & CLINK so that those PVAR slots need only be saved when there is data in them. That would require changing the VARK opcodes so that the ones which accessed the upper 8 slots would work somewhat differently (by using opcode<5> for instance) so that the PVARS could be relocated to position 16 instead of starting at location 8. (This implies the opcodes are broken into chuncks of 8 instead of 16). CONS PRECONDITION Consing will take place by having a global register point to the next free cell to cons. The free cell will have a ptr to the next free cell after that. If it is NIll, a precondition must occur so that when the opcode is finished the memory ufn is run to allocate more cons cells (or whatever type of cell was just exhausted). GREATERP & other opcodes returning T & or NIL This opcode should be able to return in 1 or 2 cycles, instead of 1 or 3 cycles. What is needed is the ability to either have a latched GreaterP condition code & use in on the next cycle, or the ability to write NIL onto the RBus (& or to Register File). Mabey a Execution Unit which can place the Constant NIL onto the RBus? Placing NIL into the RegisterFile would be most useful. It could also be used in other places to put NIL back into the reg file when doing other usefull stuff. Many opcodes jump to specifically set NIL because are using D1 & D2 for comparisons. Might also be usefull to Place T or NIL on RBus / Register File depending on the result of the DpCCode. (See TypeBits opcode which compares 2 things then jumps to set T or NIL onto TOS). DP CONDITION CODES We need to be able to specify an OR ing of several conditions of the data path. i.e. NumberP or FixP or FloatP... etc. (Do this by assigning several conditions the SAME number). ABORTing Memory Operations On some of the jumps we want to update the SP & start a memory operation of IBUF, but abort the memory operation if the DPCCode fails. ((GACHA €GACHA GACHA D6(DEFAULTFONT 1 (GACHA 12Q) (GACHA 10Q) (TERMINAL 10Q)) /~ /7# 'j<Ď<6=7el6&4&# (A70'&# =##XI-ýł‡Áózş