HARDWARE FUNCTIONAL SPEC Copyright (c) 1986, 1987 Xerox Corporation All Rights Reserved Xerox Internal use Only Table of Contents System Description Clocks Data Paths Register File Register Decoder Register Mapper Register Multiplexer Tos Arg Arg2 Opcode Opcode<4> IBufN K TopCxt BotCxt Executeion Units ALU LU Shifter TagLogic Conditional Units Data Path Condition Codes RegMux Condition Codes Result Condition Codes Macro Instruction Fetch Units Program Counter Instruction Fetch & Buffers IBuf Shifter Micro Instruction Fetch Preconditions Misc Logic Virtual Memory System Memory Control Unit Special Registers Temp1 Mar Constants Microcode Format SYSTEM DESCRIPTION The CMOS I Tamarin processor is fabricated using 1.5 micron CMOS technology. It is designed to support the special features necessary to run Lisp efficiently, including tag bits, microconditionality, CDR coding, internal frame cache, large virtual address space, onboard memory manager, fast function call & return, garbage collection primitives, and Ufn opcode support. It is also closely coupled with memory to provide fast transfer between the memory system and the microprocessor. The major components of the processor are Register File, Register Decoder, Register Mapper, Tag Logic, Shifter, ALU, LU, Data Path Condition Codes, Register Mux, Tos, Program Counters, Instruction Buffer Logic, Virtual Memory Unit, Memory Control, External Pads, Microinstruction Fetch, Conditional Unit, Precondition Unit, Microcode Roms and Data Paths. Most of the units are interconnected via one of the major data paths of the system: D1, D2, RBus, or MuxBus. CLOCKS The CMOS I Tamarin processor requires one external clock to control its internal frequency. This clock is internally be broken down into the Clock and ClockBar signals used inside the processor. Each complete cycle of clock & clockbar represents one half of a micro cycle, with one half being the read cycle and the other the write cycle, represented by the signals WriteState and ReadState. The relationship of the clock signals is seen in the following graph: K@@@@@@"xq㏄>|@@@"D BB @@@@*D BB @@@@*x C x@@@*P B@@@@H BB@@@@D BB@@@@DpC|@@@@@@<|!>@@@"@Q! @@@"@Q! @@@@@@@@@@p'@@@"@D@@@"@@@@ @@@@ @DH@@@"@DO@@@"@$H@@@|p'@@@@@@@p @@@"@@@@@"@@@@ @@@@ @@@@@"@@@@@"@ @@@|p  A machine cycle begins on the rising edge of the Readstate signal, and this is the time at which most the machine's edge triggered latches are activated to latch in the state of the next instruction. The machine is in the read cycle when ReadState is high, and in the write cycle when WriteState is high. DATA PATHS The major data paths of the microprocessor are three 34 bit busses which perform most of the data transfers. The two operand source busses are D1 & D2, and the result bus is the RBus. Data is placed onto the D1 and D2 busses during the read cycle of the processor. The computed result is then place onto the RBus and stored during the write cycle. The MuxBus is an 9 bit bus which is used to specify operands to the shifter and memory system, to move data from the RegMux to the D1 & D2 data busses, to move data from the D2 bus to the RegMux, and also to move data between RegMux registers. Unlike the larger data busses, the MuxBus changes value at each machine cycle, so there are different values on the MuxBus at read & write cycles. REGISTER FILE Inputs EvenWordLines, OddWordLines, RBus, WriteOk Outputs: RE, RO The register file conceptually contains 9 banks of registers: 8 activation frames each of which contain the stack frame for a particular function call, and one global frame containing special registers. The actual layout of the register file is two speperate halves with one half being the odd addresses and the other being even addresses. The split register halves allows two consecutive registers to be fetched out of the register file simultaniously so that top of stack operands can be fetched together. Addresses for the register file are composed of two parts: a context and an offset. The context depicts which of the 9 register banks is being selected, and the offset is the register number of the selected bank. Whenever a read operation takes place, two operands are always read: the requested register and the register at the same offset - 1. Both of these values are passed to the register mapper which decides how to place the data onto the busses. The register file directly writes into the register specifed by the wordlines from the RBus during the write cycle. Writeback to the register file is inhibited if the WriteOk signal is not present. REGISTER DECODER Inputs: RegAddr, RegCxt Outputs: EvenWordLines, OddWordLines The register decoder converts the register address & context into the proper wordlines required to select the desired register(s). The decoder is combinatorial logic, and the resulting wordlines must be latched at each rising clock edge. Addresses must be presented to the decoder a half cycle before they are to be used so that the resulting wordlines can be latched on the clock edge. To decode addresses for a register file read they must be presented during the previous write, so that the wordlines can be latched at the start of the state in which they are to be used. REGISTER MAPPER Inputs: RE, RO, RBus, Dswap Outputs: D1, D2 The register mapper unit maps the data between the register file and the processors busses. During the read cycle the register file outputs of RE and RO are mapped onto the D1 and/or D2 data busses. The mapper must take into consideration the even/oddness of the register address so that the specified register is placed on D1 and the datum at (regaddr-1) is placed on D2. The datum bound for D1 & D2 can also be swapped by the Dswap flag of the microcode, so this must also be taken into consideration. REGISTER MULTIPLEXER Inputs: Opcode, IBufN, MuxBus, D2, uK Outputs: Regaddr, RegCxt, MuxBus, Arg=0, Arg=Arg2, FramesFull, FramesEmpty The register multiplexer section of the chip controls the sourcing of the register address and context signals, and also the movement of data to and from the MuxBus. It also contains several auxiliary registers of the machine such as: Arg, Arg2, TopCxt, BotCxt, & Tos. These registers can be sources to either the register decoder or the MuxBus. Tos Inputs: RegCxt, MuxBus Outputs: Tos, Tos', MuxBus This register is the pointer to the top of the execution stack. There are actually 8 Tos pointers, one for each register bank in the processor. The Tos being referenced relates to the current register context. The index into the Tos array is found from the current register context of the cycle Tos is being used (i.e. If Tos is used during a register read, then the RCxt is used to select what Tos value is used; and WCxt is used as the index during a register write). Tos can output its current value, or (during the write cycle) its current value +/- 1 (Tos'). It can set its new value to Tos' or the value on the MuxBus. Arg Inputs: MuxBus Outputs: Regaddr, RegCxt, Arg, Arg', MuxBus This 9 bit register is a general register used for loop counts & register indexing. It can output its current value and be set its next value to itself, its current value +/- 1 (Arg'), or the MuxBus. Arg2 Inputs: MuxBus Outputs: Regaddr, RegCxt, Arg2, Arg2', MuxBus This 9 bit register is a general register used for loop counts & register indexing. It can output its current value and be set its next value to itself, its current value +/- 1 (Arg2'), or the MuxBus. Opcode Outputs: MuxBus This latch in the RegMux contains the opcode of the currently executing Lisp instruction. It is reset whenever the execution of a new opcode begins (or rising edge of ReadState & NewOp). Opcode<4> Outputs: Regaddr, MuxBus This selection of the RegMux returns the lower 4 bits of the opcode latch. IBufN Outputs: Regaddr, MuxBus This RegMux selection selects the IBufN latch of the instruction buffer. This latch contains the byte following the opcode byte. It is latched at the same time that the opcode is latched so that its value will remain valid while processing an opcode. K Outputs: Regaddr, RegCxt, MuxBus This is the K field from the microinstruction. The RexMux can select this field to go out to the Regaddr, RegCxt, or MuxBus. EXECUTION UNITS The Execution units perform the data manipulation operations of the processor. They generally take the two data busses D1 & D2 as the inputs and return the result on the RBus. The execution units operate in parallel, but only the selected unit will return its results on the RBus. The three basic execution units are: arithmetic unit, logical unit, and shifter unit. Their operations are as follows: ALU Inputs: D1, D2, uEUop, & uTag Outputs: RBus, GreaterP, Overflow, Carry This unit performs the chips arithmetic operations. It can add or subtract (1's or 2's compliment) the operands on D1 & D2. The ordering of the operands is (D1 + D2) & (D1 - D2). The Carry, Overflow, and GreaterP bits are set to thier regular arithmetic meaning. Note that the GreaterP bit is only valid if a subtraction operation is performed. LU Inputs: D1, D2, uEUop, & uTag Outputs: RBus This unit performs the logical operations of the chip. It can Or, And, & Xor the operands on D1 & D2, and also Or D1 or D2 with 0 to effectively return D1 or D2. SHIFTER UNIT Inputs: D1, D2, MuxBus, uEUop, & uTag Outputs: RBus, ShifterOverflow This unit consists of a 64 bit shifter which is then shifted to form a 32 bit result. The upper word of the shifter comes from D2, the lower word from D1, and the shift amount is specified on the MuxBus. The physical shift is always a right shift. If an arithmetic shift is specified, then the upper word is filled with bits corresponding to the sign of the lower word instead of D2. One of the EUop bits is used to specify when the MuxBus shift amount should be complimented (for simulation of left shifts). The ShifterOverflow flag is set when any of the leftover bits on the upper side are not 0 (for logical or arithmetic shifts), or .... CONDITIONAL UNITS DATAPATH CONTITION CODES Inputs: D1, D2 Outputs: CondA These condition codes are the ones which are computed from the data on D1 & D2. They generally consist of operand type checking operations for the execution units such as: IntegerP, PointerP, etc. The desired condition is selected by the CondCode field of the microcode. REGMUX CONDITIONS Inputs: Arg=0, Arg=Arg2, FramesFull, FramesEmpty Outputs: CondB These conditions are output by the register mux & selected by the CondMux field of the microcode. EXECUTION UNIT RESULT CONDITIONS Inputs: GreaterP, Overflow, Carry, ShifterOverflow Outputs: CondC These conditions are generated by the execution units and memory system. The desired condition used is selected by the CondResult field of the microcode. CONDITION CODE UNIT Inputs: CondA, CondB, CondC Outputs: ConditionResult This unit ands the conditon results to determine the resulting condition of the microinstruction. MACRO INSTRUCTION FETCH UNIT PROGRAM COUNTER Inputs: ^OpLength, OpLength=0, WritePc, NewOp, TopCxt, RBus Outputs: Pc, PcFetchAddr The program counter contains the byte address of the currently executing Lisp opcode. During the rising edge of the Read cycle & NewOp the PC is updated to the value in NextPc (which is usually the address of the next opcode to execute). NextPc is set to the current PC + the OpLength of the current Lisp instruction. NextPc is computed using combinatorial logic, so that changing OpLength will change when the next Opcode is to fetched. Thus setting OpLength=0 causes the PC to remain the same for the next opcode fetch. A write to the PC will write to the RBus to the PC value, thus OpLength=0 must be set so that the computation of NextPc will result in the correct value of the PC being latched back into the PC. The PC actually represents an array of 8 different registers, one for each bank of frame registers. The TopCxt value is used to determine which of the PC elements is actually in use. INSTRUCTION FETCH & BUFFERS IBUF SHIFTER The IBuf shifter sets the IBufN and IBufData lines of the processor. The IBufN data is taken from the first byte of the IBufSData word, while the IBufData word is taken by masking the IBufSData word with an appropriate mask chosen by the OpLength. MICRO INSTRUCTION FETCH The fetch of the next microinstruction is dependent on the condition result of the current microinstruction, the precondition pla, and wether the next microinstruction is to start a new opcode. The microcode rom is divided into two sides, an A side and a B side. The microinstruction format is such that each microinstruction has two possible succeding address locations; one when the condition result is true and one when the condition result is false. The addresses found as the true jump cases in the microcode are addresses for the A side of the Rom, and false jumps correspond to the B side of the Rom. When a microinstruction is executing, both of its alternative jump locations are simultaniously fetched from the two different Rom sides. Thus when the condition result is ready, the correct microinstruction has already been fetched & is ready for decoding. In the simple case, the condition result chooses which of the two jump addresses is to be used as the address of next microinstruction. Under certial circumstances the address on the A side of the microinstruction does not contain the address to the next microinstruction, but instead contains a done bit to signify that the address of the next microinstruction on the A side should come from the opcode. Thus a Lisp opcode number corresponds directly to the physical location of where the microcode begins to handle that opcode. If a general precondition exists, the opcode is overridden by the start address of the precondition handler. This allows conditions such as interrupts and stack overflows to be handled without interrupting the normal microcode control flow. For Immediate preconditions, the address of the next microinstruction is forced to that of the precondition handler. Thus the immediate preconditions such as reset & page fault change the microcode flow and loose any state information to return. In the case of page faults the oplength must be set to 0 and the opcode re-started over again. GENERAL PRECONDITIONS Inputs: Reset, PageFault, StackRefill, RefCount Outputs: DoPrecondition, ForceNewOp, PreconditionStartAddr The Tamarin processor contains a precondition PLA which allows the normal control flow of the microcode to be interrupted when certian preconditions exist. These preconditions can alter the next microinstruction to be executed, so that special conditions (such as interrupts or page faults) can be handled in the microcode. There are two basic types of preconditions: normal and immediate. Normal preconditions only alter the microinstruction flow when a new opcode is to be executed. The normal preconditions alter the microinstruction fetch address during the fetch of a microinstruction for a new opcode to that of the precondition handler if the precondition is raised. Immediate preconditions alter the control flow of the microcode upon the next microinstruction fetch immediately after the condition is raised, thus the microcode to execute a particular opcode can be interrupted by one of these preconditions. Some of the normal preconditions are: StackRefill, RefCount, Refill PageFault, FramesFull, FramesEmpty, and Interrupt. The Immediate preconditions are: Reset and PageFault. MISC MICROCODE FIELDS VIRTUAL MEMORY SYSTEM VMM Table Lookup Inputs: Viraddr Outputs: @Viraddr, Fault, VMRefill, VirMatch, RealMatch The virtual memory system converts a virtual address into a physical address. The virtual memory address is the input to the VMM system. The virtual portion of the address (bits 26:10) is then compared to the 8 entry VMM table. If a match is found, then the corresponding physical address along with any corresponding page faults are returned to the memory system. If a table match is not found, then VMRefill is returned along with the address of the VM table entry to read. VMM Mux Inputs: @Viraddr, VMRefill, VirMatch, RealMatch Outputs: Raddr MEMORY SYSTEM Inputs: Raddr Outputs: Ras0-3, Cas, We SPECIAL REGISTERS TEMP1 REGISTER Inputs: RBus Outputs: D1 D2 This 34 bit special register is used by the microcode to hold temporary results. It can be read onto either D1 or D2 and is written from the RBus. MEMORY ADDRESS REGISTER Inputs: D1 Outputs: D1 This 34 bit register contains the address of the last memory access. It is written (from D1) whenever a memory access is initiated. Thus the page fault routine can read this register to determine what address caused the page fault. The register is read out onto D1. MICROINSTRUCTION FORMAT This section describes each field of the microinstruction and what it controls in the processor. Euop This field chooses which of the execution units is to place its results onto the RBus. There are four basic choices of execution units: none, arithmetic unit, logical unit, and shifter unit. The EUop is further decoded by the execution units to decide which operation is requested of the unit (i.e. add, subtract, etc). Tag This field chooses where the tag field of the result of the execution units comes from. It can come from the tag bits of D1 or D2, bits 7 & 6 of D2, or the system representation for an Integer. Cycle This field indicates what type of instruction cycle is to take place: Normal, Memory Read, or Memory Write. Memory read operations place the memory data on the RBus, so the EUop field should be none when a memory read is selected. Raddr This field selects what is to be used as the register address in the register file read operation. The register file is always read on every microinstruction, even if the datum is not used. The choices for this field are: Tos, Arg, Arg2, IBufN, Opcode AND 15, and K. The registers at the address specified and the address minus one are both fetched and given to the dswap unit. Dswap This bit is used to indicate when the two values fetched from the register file should be swapped before going out to the data bus. RCxt This field is the Read Context of the register file access. It indicates which of the banks in the register file is to be used for the register read. The choices for this field are: Cur, Next, Prev, Last, and K. Cur corresponds to the current top context. Waddr This field selects the register address to be written to from the RBus. Its choices are: none, Tos, Tos', Arg, Arg2, IBufN, Opcode AND 15, and K. WCxt This field is the Write Context used during the register file write cycle It indicates which of the banks in the register file is to be used for the register write. The choices for this field are: Cur, Next, Prev, Last, and K. Cur corresponds to the current top context. RD1addr This field selects where the D1 bus is to be driven from. Its choices are: the Register specified by the Raddr field, the IBufData word, the Memory Address Register, the MuxRead bus, the Temp1 register, the PC Fetch Address Register, or the constant 0. RD2addr This field selects where the D2 bus is to be driven from. Its choices are: the register at Raddr-1, the MuxRead bus, the Temp1 register, the current PC, and the constants Nil, T, Unbound, SymbolTypeBits, and 0. W2addr This field selects which of the special registers are to be written from the RBus. The choices are: none, Temp1, & PC. NewTopCxt This field indicates where the new value for the Top context will come from. Its choices are: Cur (no change), Next, Prev, and K. The top context indicates which of the stack frames in the machine is the current one. NewBotCxt This field indicates where the new value for the bottom context will come from. Its choices are: Cur (no change), Bot=In (bottom context is now in machine), Bot=Out (bottom context no longer in machine), and K. MuxRead This field indicates who drives the MuxBus during the Read cycle of the machine. Its choices are: Tos, Arg, Arg2, IBufN, Opcode, Opcode AND 15, and K. MuxWrite This field indicates who will drive the MuxBus during the write cycle of the machine. Its choices are: Tos, Arg, Arg2, IBufN, Opcode, Opcode AND 15, K and D2. Tos' This field indicates the what type of increment / decrement is desired for the Tos' register. It can be +1 or -1. NewTos This field indicates the next value for Tos. It can be: Tos, Tos', MuxRead, or MuxWrite. Arg' This field indicates the what type of increment / decrement is desired for the Arg' register. It can be +1 or -1. NewArg This field indicates the next value for Arg. It can be: Arg, Arg', MuxRead, or MuxWrite. Arg2' This field indicates the what type of increment / decrement is desired for the Arg2' register. It can be +1 or -1. NewArg2 This field indicates the next value for Arg2. It can be: Arg2, Arg2', MuxRead, or MuxWrite. K This is the constant field of the microcode used for small constants in computations. CondCode The condition code field is used to determine which of the condition codes is to be active. The result of the selected condition code is used by the microprocessor to select the next microinstruction and it affects the register writeback. The condition codes available are: True, Unbound, BoundP, StackP, IntegerP, FloatP, XTypeP, PointerP, IntegerPD1D2, NumberPD1D2, ConsP, D1=D2, D1#D2, CCodeP, D2=Int<8&D1=CCodeP, D2=Int<8&D1=Atom, CCodeP&~NLambdaStarP, FlagBitD2, D1<7x>=D2<7x>, D1<8>=D2<8>, MinIntD2, PointerPD2, IntegerPD1&PointerPD2, TrapOnReturnToD2, TrapOnExit, PosIntegerP, Arg=Arg2, Arg#Arg2, Arg=0, Arg#0, NoFault, FramesFull, and FramesAvail. ResultCond This field selects which of the EUop result condition codes is to be selected. The choices for this field are: True, Overflow, Carry, GreaterP, and ShifterOverflow. WriteT This flag indicates that the register file should only be written back to if the result of both of the condition code fields is true. WriteF This flag indicates that the register file should only be written back to if the result of both of the condition code fields is false. JumpT This field specifies the location of the microinstruction which is to be executed when the condition results are true. JumpF This field specifies the location of the microinstruction which is to be executed when the condition results are false. Misc This field is used to set various control functions of the microprocessor and to reset some of the conditional flags such as interrupt, .... ((D6(TEXTFONT 5 (CLASSIC 14) (TIMESROMAN 10) (CLASSIC 10))?1(DEFAULTFONT 1 (GACHA 10) (GACHA 8) (TERMINAL 8)) +       BMOBJ.GETFN32 _2%B&Kb,. K!~)] &1b!3c< gW0;K80    aB}x   sZsZt]V  wxaUz