Heading:qjk40(635)
Tamarin Software Tasksy756qjk40
Page Numbers: Yes  X: 527  Y: 10.5"qjk40
Inter-Office Memorandumz18592l4445y762\f5b
To	Distribution	Date	May 23, 1985z18592l4445d2998e21(0,65535)(1,4445)(5,11684)(6,14146)\f1 2f0t2 1t0 12t6 1f1t0 4f0t7 1t0
From	Alan Bell	Location	Palo Altoz18592l4445d2998y716e25\f1 4f0t2 1t0 9t6 1f1t0 8f0t7 1t0
Subject	Tamarin Software Tasks	Organization	PARC/ISLz18592l4445d2998e25\f1 7f0t2 1t0 22t6 1f1t0 12f0t7 1t0
XEROX       z18592l508y644e14(2116)\f2 5f0
Filed on: [Ivy]<ABell>Tamarin-SoftwareTasks.bravoe30
e10
This memo sketches out the software tasks of the Tamarin project.  It is intended as a starting point to be able to discuss the amount of work and the timing involved.  This describes tasks through the creation of the prototype machine and do not address any tasks required for productization.(635)
Software managemente20\b
The software aspects of the Tamarin project need to be managed.  The software implementers will need supervision.  Resource and schedule plans need to be created.  Interaction with the AISBU management needs to be maintained to communicate needs, expectations, and commitments.  A more complete version of this document needs to be created.e5\340b
System Definitione20\b
Many changes are being made in the low-level data structures and algorithms to accomdate the improved hardware components of Tamarin.  The algorithms and data-structures need to be outlined in enough detail to feel confident that the decisions are viable.  This definition can be divided into 2 parts: structures that the hardware knows about, and structures that support the hardware but that aren't directly used by the chip.  The opcodes are an example of the first.  The second is exemplified by the algorithm for handling reference count overflow.  The hashing function has to be outlined only in enough detail to believe that it is viable.e10
It is important that this be completed as soon as possible.  The detailed hardware design cannot be done until this phase is complete.  This will take the talents of a Lisp wizard - BVM.e10
	*	Define opcodes, internal data structures, algorithms for handling system tasks, eg. Garbage Collection, etc.  (This is in progress by AGB)l4896d2999e10
	*	Outline support structures - algorithms for stack, etc.
	*	Sketch code for support routines for stack, GC, etc.
System Verificatione20\b
There is a desire to verify in detail that the choices made in the system definition phase are viable.  Emulation of the system would verify the design with a great deal of confidence.  It may be possible to limit this aspect to a modest effort because of fast turnaround fabrication.  An emulator could be written in Lisp or in Dorado ( or DLion) microcode.  A detailed emulator would allow the Lisp system modifications to start before working hardware exists.e10
	*	Instruction set emulatore10
	*	Detailed support routine coding
Software Infrastructure for Hardware creatione20\b
Software needs to be written to support the hardware design.  The microcode work will have to be written in close interaction with myself (AGB).e10
	*	Microassemblere10
	*	Tamarin microcode
	*	Bootstrapping and tele-debugging software
Lisp system modificationse20\b
There are many changes required in the low-level Lisp system to support the changes that the Tamarin hardware entails.  This list attempts to capture some of the required tasks.  Many more will undoubtably be added.  This work can't be started until an emulator or working hardware exists.e10
	*	Compilere10
	*	Type systeme1
	*	Storage allocatione1
	*	Garbage collectione1
	*	Stack architecturee1
	*	CommonLisp enhancementse1
	*	Operating Systeme1
	*	Virtual memory supporte1
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