Overview

Tamarin is a project to build a VLSI-based Lisp system. It will contain custom hardware to enable it to run Lisp efficiently as well as being physically compact. This document provides an overview of the project and the machine.

The Artificial Intelligence Busness Unit has an aggressive effort underway to gain a substantial fraction of the market in AI hardware. The competition for this market is stiff. We need state-of-the-art hardware to be competitive. The hardware must have high cost-performance.

Likewise, the Intelligent Systems Lab of PARC needs to have high-performance hardware. To do leading research, the programming environment must be superior and the performance high.

The Lisp language has many special requirements. In order to run Lisp efficienctly, the supporting hardware must deal with these special requirements. Lisp has run on existing D-machine hardware (Dandelion, Dolphin, Daybreak, Dorado) but there have existed substantial mismatches between the language and the hardware. This has significantly reduced the performance of the system.

The initial Tamarin machine will aim toward high-cost performance with a medium performance machine at a low-cost and small size. Later machines, derived from the initial efforts will aim at really high performance.

The Tamarin machine will achieve this cost-performance combination by containing custom VLSI chips. These chips will not push the state of the art but rather depend on a high match with the Lisp languauge to achieve reasonable performance. This processor chip is expected to have about 50,000 transistor - much less than state-of-the-art chips like the 68020 or 80386.

Architecture

The machine will be built completely on one printed circuit board. It will contain three custom VLSI chips, 5 megabytes of memory, and a 8088 microprocessor. The custom chips are: Lisp processor, I/O controller, and bootstrap memory interface.

The custom VLSI Lisp processor will be a typical VonNeuman architecture with special features for Lisp. Details will be described later.

The I/O controller chip will interface to four ports. It will drive a black and white display with a resolution of 1024 x 800. It will have a keyboard input port. It will drive an Ethernet port. It will drive an industry standard periperal bus - the SCSI bus. This bus will contain a 50-100 Megabyte winchester disk drive and a floppy disk. The SCSI bus will allow other peripherals to be added as needed.

The Memory Interface chip is used to hook a 8088 microprocessor into the system. This microprocessor will be for initializing the system and for debugging the system during development. It will be idle after the system has been initialized.

Lisp Language Requirements

Mismatches have hindered the performance of Lisp on previous D-machine hardware. Some of these mismatches are described.

Word Size - Previous machines have had a 16 bit word size. Almost all quantities that Lisp deals with are longer than 16 bits. Tamarin will have a 40 bit word size. This change is expected to speed up the machine by almost a factor of 2.

Typed pointers - Lisp determines the type of a piece of data by the data itself. Most other languages know the type by the location the data is stored into. Therefore Lisp requires that all pointers contain information describing the type of the data. Tamarin reserves the top 8 bits of each pointer for this type information and for reference count information. The hardware will automatically trap operations performed on the wrong type of data.

Instruction Fetch Unit - The form of byte codes for Mesa is different than for Lisp. The Mesa instructions tend to be much shorter. The D-machine hardware has been optimized for these instructions. Tamarin has an instruction formatter that knows about the different forms of Lisp instructions so that most instructions can be executed in one microinstruction.

Hardware Stack - Lisp uses a very complicated call/return stack discipline. This has meant that the hardware stacks that exist on D-machines are not usable with Lisp. Tamarin includes a compatible hardware stack on chip. This stack will contain the four most recently used stack frames.

Close memory coupling - The D-machines have been based on TTL logic. They have required many components and therefore have had to have several PC boards to contain all the components. Because Tamarin is highly integrated, it will fit entirely on one PC board. This will allow the memory to run faster. The memory does not have to drive the extra load of a backplane.

Virtual Memory Mapping - The Dandelion (and Daybreak) does virtual memory mapping in software. Lisp does alot of memory access to random locations. Tamarin will put this virtual memory mapping in hardware.

Lisp Processor Architecture

By dealing with the mentioned mismatches, the basic processor can be kept simple. Specialized circuit techniques will be avoided. The internal clock will run at a slow rate compared to current industry standards. By including the system concepts, the overall performance will not be slowed down.

The processor chip is made up of several pieces.

Register file - This contains up to four stack frames with each frame consisting of 32 words.

Execution Unit - This acts on the data in the register file. It performs the arithmetic, logic, and shift operations. Before performing the requested operation, it checks the type of the data to ensure that operation is appropriate. For example, if an addition is attempted on a Lisp pointer, an error is raised.

Special registers - These registers are on the main internal bus to th eexecution unit. However, there are special inputs that affect these registers. The top of stack pointer and the program counter are examples.

Instruction Buffer - This buffers up to 40 bytes of instructions. It is refilled with 4 40bit words at a time. By using nibble mode memory chips, this can occur in about 500 ns.

Instruction Formatter - In Lisp, many instructions can be represented in several forms of different lengths. Jump instructions can 1,2 or 3 bytes long. The formatter makes all these varients look the same to the Microcode finite state machine.

Opcode PLA - This takes the opcode and determines the which format should be selected. It also tells the finite state machine where to start.

Microcode Finite State Machine - This contains the microcode to specifiy the actions for each bytecode instruction.