C0 W0 31 0 W1 32 1 A0 CoreName r R0 "XPD" W2 0 1 A1 CMosBPins 1 O0 A2 Cell 0 0 952 2488 1 O1 A3 PinOb0 952 2488 0 0 0 0 2 A4 SignalName r R1 "Pad" A5 layerOfPin A6 cmosB A7 ovg 0 0 952 2488 R2 "" 1017422166 0 0 1 A8 CoreGeometryPin a A8 2488 22296 2 W3 0 1 A1 1 O0 2488 23896 2 W4 0 1 A1 1 O0 2488 25496 2 W5 0 1 A1 1 O0 2488 27096 2 W6 0 1 A1 1 O0 2488 35096 2 W7 0 1 A1 1 O0 2488 36696 2 W8 0 1 A1 1 O0 2488 38296 2 W9 0 1 A1 1 O0 2488 39896 2 WA 0 1 A1 1 O0 2488 41496 2 WB 0 1 A1 1 O0 2488 43096 2 WC 0 1 A1 1 O0 2488 46296 2 WD 0 1 A1 1 O0 2488 47896 2 WE 0 1 A1 1 O0 2488 51096 2 WF 0 1 A1 1 O0 2488 52696 2 W10 0 1 A1 1 O0 4696 59048 0 W11 0 1 A1 1 O0 6296 59048 0 W12 0 1 A1 1 O0 7896 59048 0 W13 0 1 A1 1 O0 9496 59048 0 W14 0 1 A1 1 O0 12696 59048 0 W15 0 1 A1 1 O0 14296 59048 0 W16 0 1 A1 1 O0 15896 59048 0 W17 0 1 A1 1 O0 20696 59048 0 W18 0 1 A1 1 O0 22296 59048 0 W19 0 1 A1 1 O0 23896 59048 0 W1A 0 1 A1 1 O0 25496 59048 0 W1B 0 1 A1 1 O0 27096 59048 0 W1C 0 1 A1 1 O0 33496 59048 0 W1D 0 1 A1 1 O0 35096 59048 0 W1E 0 1 A1 1 O0 36696 59048 0 W1F 0 1 A1 1 O0 38296 59048 0 W20 0 1 A1 1 O0 39896 59048 0 W21 0 1 A1 1 O0 41496 59048 0 W22 2 1 A0 r R3 "XPDTAG" W23 0 1 A1 1 O0 2488 19096 2 W24 0 1 A1 1 O0 2488 20696 2 W25 6 1 A0 r R4 "XPDHI" W26 0 1 A1 1 O0 5640 2488 4 W27 0 1 A1 1 O0 2488 7896 2 W28 0 1 A1 1 O0 2488 9496 2 W29 0 1 A1 1 O0 2488 12696 2 W2A 0 1 A1 1 O0 2488 14296 2 W2B 0 1 A1 1 O0 2488 17496 2 W2C 16 1 A0 r R5 "XA" W2D 0 0 W2E 0 1 A1 1 O0 2488 54288 2 W2F 0 1 A1 1 O0 2488 55888 2 W30 0 1 A1 1 O0 59048 56848 6 W31 0 1 A1 1 O0 59048 55248 6 W32 0 1 A1 1 O0 59048 24848 6 W33 0 1 A1 1 O0 59048 20048 6 W34 0 1 A1 1 O0 59048 18448 6 W35 0 1 A1 1 O0 59048 15248 6 W36 0 1 A1 1 O0 55248 2488 4 W37 0 1 A1 1 O0 15248 2488 4 W38 0 1 A1 1 O0 8848 2488 4 W39 0 1 A1 1 O0 2488 4688 2 W3A 0 0 W3B 0 0 W3C 0 0 W3D 16 1 A0 r R6 "XD" W3E 0 1 A1 1 O0 46296 59048 0 W3F 0 1 A1 1 O0 47896 59048 0 W40 0 1 A1 1 O0 51096 59048 0 W41 0 1 A1 1 O0 52696 59048 0 W42 0 1 A1 1 O0 54296 59048 0 W43 0 1 A1 1 O0 55896 59048 0 W44 0 1 A1 1 O0 59048 53640 6 W45 0 1 A1 1 O0 59048 52040 6 W46 0 1 A1 1 O0 59048 48840 6 W47 0 1 A1 1 O0 59048 47240 6 W48 0 1 A1 1 O0 59048 44040 6 W49 0 1 A1 1 O0 59048 42440 6 W4A 0 1 A1 1 O0 59048 40840 6 W4B 0 1 A1 1 O0 59048 39240 6 W4C 0 1 A1 1 O0 59048 37640 6 W4D 0 1 A1 1 O0 59048 36040 6 W4E 12 1 A0 r R7 "XPA" W4F 0 1 A1 1 O2 A2 0 0 952 2488 1 O1 0 0 0 2 A4 r R1 A5 A6 A7 0 0 952 2488 R2 1017422166 0 0 1 A8 a A8 53640 2488 4 W50 0 1 A1 1 O2 52040 2488 4 W51 0 1 A1 1 O2 50440 2488 4 W52 0 1 A1 1 O2 48840 2488 4 W53 0 1 A1 1 O2 47240 2488 4 W54 0 1 A1 1 O2 45640 2488 4 W55 0 1 A1 1 O2 42440 2488 4 W56 0 1 A1 1 O2 40840 2488 4 W57 0 1 A1 1 O2 39240 2488 4 W58 0 1 A1 1 O2 37640 2488 4 W59 0 1 A1 1 O2 36040 2488 4 W5A 0 1 A1 1 O2 34440 2488 4 W5B 4 1 A0 r R8 "XRAS'" W5C 0 1 A1 1 O2 23240 2488 4 W5D 0 1 A1 1 O2 21640 2488 4 W5E 0 1 A1 1 O2 20040 2488 4 W5F 0 1 A1 1 O2 16840 2488 4 W60 0 2 A0 r R9 "PadGnd" A1 291 O3 A9 Rect 640 1600 A6 AA met 0 5968 60896 2 O4 A9 640 1600 A6 AB met2 0 5968 60896 2 O3 7568 60896 2 O4 7568 60896 2 O3 9168 60896 2 O4 9168 60896 2 O3 10768 60896 2 O4 10768 60896 2 O5 A9 1216 1600 A6 AA 0 12368 60320 2 O6 A9 1216 1600 A6 AB 0 12368 60320 2 O7 A2 0 0 952 2488 1 O1 0 0 0 2 A4 r R9 A5 A6 A7 0 0 952 2488 R2 1017422166 0 0 1 A8 a A8 11096 59048 0 O3 13968 60896 2 O4 13968 60896 2 O3 15568 60896 2 O4 15568 60896 2 O3 17168 60896 2 O4 17168 60896 2 O5 18768 60320 2 O6 18768 60320 2 O3 20368 60896 2 O4 20368 60896 2 O3 21968 60896 2 O4 21968 60896 2 O3 23568 60896 2 O4 23568 60896 2 O3 25168 60896 2 O4 25168 60896 2 O3 26768 60896 2 O4 26768 60896 2 O3 28368 60896 2 O4 28368 60896 2 O5 29968 60320 2 O6 29968 60320 2 O5 31568 60320 2 O6 31568 60320 2 O7 30296 59048 0 O5 33168 60320 2 O6 33168 60320 2 O3 34768 60896 2 O4 34768 60896 2 O3 36368 60896 2 O4 36368 60896 2 O3 37968 60896 2 O4 37968 60896 2 O3 39568 60896 2 O4 39568 60896 2 O3 41168 60896 2 O4 41168 60896 2 O3 42768 60896 2 O4 42768 60896 2 O5 44368 60320 2 O6 44368 60320 2 O3 45968 60896 2 O4 45968 60896 2 O3 47568 60896 2 O4 47568 60896 2 O3 49168 60896 2 O4 49168 60896 2 O5 50768 60320 2 O6 50768 60320 2 O7 49496 59048 0 O3 52368 60896 2 O4 52368 60896 2 O3 53968 60896 2 O4 53968 60896 2 O3 55568 60896 2 O4 55568 60896 2 O3 57168 60896 2 O4 57168 60896 2 O8 A9 1216 4368 A6 AB 0 60320 57168 0 O9 A9 1216 3800 A6 AB 0 60968 60320 2 OA A9 4368 1216 A6 AA 0 61536 57168 2 OA 57168 60320 0 O3 60896 55568 0 O4 60896 55568 0 O3 60896 53968 0 O4 60896 53968 0 O3 60896 52368 0 O4 60896 52368 0 O3 60896 50768 0 O4 60896 50768 0 O5 60320 49168 0 O6 60320 49168 0 O7 59048 50440 6 O3 60896 47568 0 O4 60896 47568 0 O3 60896 45968 0 O4 60896 45968 0 O5 60320 44368 0 O6 60320 44368 0 O3 60896 42768 0 O4 60896 42768 0 O3 60896 41168 0 O4 60896 41168 0 O3 60896 39568 0 O4 60896 39568 0 O3 60896 37968 0 O4 60896 37968 0 O3 60896 36368 0 O4 60896 36368 0 O3 60896 34768 0 O4 60896 34768 0 O3 60896 33168 0 O4 60896 33168 0 O5 60320 31568 0 O6 60320 31568 0 O5 60320 29968 0 O6 60320 29968 0 O7 59048 31240 6 O3 60896 28368 0 O4 60896 28368 0 O5 60320 26768 0 O6 60320 26768 0 O3 60896 25168 0 O4 60896 25168 0 O3 60896 23568 0 O4 60896 23568 0 O3 60896 21968 0 O4 60896 21968 0 O3 60896 20368 0 O4 60896 20368 0 O3 60896 18768 0 O4 60896 18768 0 O3 60896 17168 0 O4 60896 17168 0 O5 60320 15568 0 O6 60320 15568 0 O3 60896 13968 0 O4 60896 13968 0 O3 60896 12368 0 O4 60896 12368 0 O5 60320 10768 0 O6 60320 10768 0 O7 59048 12040 6 O3 60896 9168 0 O4 60896 9168 0 O3 60896 7568 0 O4 60896 7568 0 O3 60896 5968 0 O4 60896 5968 0 O3 60896 4368 0 O4 60896 4368 0 O8 57168 1216 6 O9 60320 568 0 OA 57168 0 0 OA 60320 4368 6 O5 55568 1216 6 O6 55568 1216 6 O3 53968 640 6 O4 53968 640 6 O3 52368 640 6 O4 52368 640 6 O3 50768 640 6 O4 50768 640 6 O3 49168 640 6 O4 49168 640 6 O3 47568 640 6 O4 47568 640 6 O3 45968 640 6 O4 45968 640 6 O3 44368 640 6 O4 44368 640 6 O5 42768 1216 6 O6 42768 1216 6 O3 41168 640 6 O4 41168 640 6 O3 39568 640 6 O4 39568 640 6 O3 37968 640 6 O4 37968 640 6 O3 36368 640 6 O4 36368 640 6 O3 34768 640 6 O4 34768 640 6 O3 33168 640 6 O4 33168 640 6 O5 31568 1216 6 O6 31568 1216 6 O5 29968 1216 6 O6 29968 1216 6 O7 31240 2488 4 O5 28368 1216 6 O6 28368 1216 6 O3 26768 640 6 O4 26768 640 6 O3 25168 640 6 O4 25168 640 6 O3 23568 640 6 O4 23568 640 6 O3 21968 640 6 O4 21968 640 6 O3 20368 640 6 O4 20368 640 6 O3 18768 640 6 O4 18768 640 6 O5 17168 1216 6 O6 17168 1216 6 O3 15568 640 6 O4 15568 640 6 O3 13968 640 6 O4 13968 640 6 O3 12368 640 6 O4 12368 640 6 O5 10768 1216 6 O6 10768 1216 6 O7 12040 2488 4 O3 9168 640 6 O4 9168 640 6 O3 7568 640 6 O4 7568 640 6 O3 5968 640 6 O4 5968 640 6 O3 4368 640 6 O4 4368 640 6 O8 1216 4368 4 O9 568 1216 6 OA 0 4368 6 OA 4368 1216 4 O3 640 5968 4 O4 640 5968 4 O3 640 7568 4 O4 640 7568 4 O3 640 9168 4 O4 640 9168 4 O3 640 10768 4 O4 640 10768 4 O5 1216 12368 4 O6 1216 12368 4 O7 2488 11096 2 O3 640 13968 4 O4 640 13968 4 O3 640 15568 4 O4 640 15568 4 O5 1216 17168 4 O6 1216 17168 4 O3 640 18768 4 O4 640 18768 4 O3 640 20368 4 O4 640 20368 4 O3 640 21968 4 O4 640 21968 4 O3 640 23568 4 O4 640 23568 4 O3 640 25168 4 O4 640 25168 4 O3 640 26768 4 O4 640 26768 4 O3 640 28368 4 O4 640 28368 4 O5 1216 29968 4 O6 1216 29968 4 O5 1216 31568 4 O6 1216 31568 4 O7 2488 30296 2 O3 640 33168 4 O4 640 33168 4 O5 1216 34768 4 O6 1216 34768 4 O3 640 36368 4 O4 640 36368 4 O3 640 37968 4 O4 640 37968 4 O3 640 39568 4 O4 640 39568 4 O3 640 41168 4 O4 640 41168 4 O3 640 42768 4 O4 640 42768 4 O3 640 44368 4 O4 640 44368 4 O5 1216 45968 4 O6 1216 45968 4 O3 640 47568 4 O4 640 47568 4 O3 640 49168 4 O4 640 49168 4 O5 1216 50768 4 O6 1216 50768 4 O7 2488 49496 2 O3 640 52368 4 O4 640 52368 4 O3 640 53968 4 O4 640 53968 4 O3 640 55568 4 O4 640 55568 4 O3 640 57168 4 O4 640 57168 4 O8 4368 60320 2 O9 1216 60968 4 OA 4368 61536 4 OA 1216 57168 2 W61 0 2 A0 r RA "PadVdd" A1 8 OB A2 0 0 952 2488 1 O1 0 0 0 2 A4 r RA A5 A6 A7 0 0 952 2488 R2 1017422166 0 0 1 A8 a A8 17496 59048 0 OB 43096 59048 0 OB 59048 45640 6 OB 59048 16840 6 OB 44040 2488 4 OB 18440 2488 4 OB 2488 15896 2 OB 2488 44696 2 W62 0 2 A0 r RB "Gnd" A1 5 OC A2 0 0 952 2488 1 O1 0 0 0 2 A4 r RB A5 A6 A7 0 0 952 2488 R2 1017422166 0 0 1 A8 a A8 31880 59048 0 OC 59048 32856 6 OC 56856 2488 4 OC 32856 2488 4 OC 2488 28680 2 W63 0 2 A0 r RC "Vdd" A1 4 OD A2 0 0 952 2488 1 O1 0 0 0 2 A4 r RC A5 A6 A7 0 0 952 2488 R2 1017422166 0 0 1 A8 a A8 28696 59048 0 OD 59048 28040 6 OD 29640 2488 4 OD 2488 33496 2 W64 0 2 A0 r RD "XCE'" A1 1 O0 19088 59048 0 W65 0 2 A0 r RE "XPDTP" A1 1 O0 44696 59048 0 W66 0 2 A0 r RF "XIOW'" A1 1 O0 59048 34448 6 W67 0 2 A0 r R10 "XCLOCK2" A1 1 O0 59048 29648 6 W68 0 2 A0 r R11 "XIOR'" A1 1 O0 59048 26448 6 W69 0 2 A0 r R12 "XIORDY" A1 1 O2 59048 23240 6 W6A 0 2 A0 r R13 "XHOSTRESET" A1 1 O0 59048 21648 6 W6B 0 2 A0 r R14 "XLPRESET" A1 1 OE A2 0 0 952 2488 1 O1 0 0 0 2 A4 r R1 A5 A6 A7 0 0 952 2488 R2 1017422166 0 0 1 A8 a A8 59048 13640 6 W6C 0 2 A0 r R15 "XHOLDA" A1 1 O0 59048 10448 6 W6D 0 2 A0 r R16 "XHOLD" A1 1 OE 59048 8840 6 W6E 0 2 A0 r R17 "XPIRQ" A1 1 O0 59048 7248 6 W6F 0 2 A0 r R18 "XXIRQ0" A1 1 OE 59048 5640 6 W70 0 2 A0 r R19 "XWENT'" A1 1 OE 28040 2488 4 W71 0 2 A0 r R1A "XWENW'" A1 1 OE 26440 2488 4 W72 0 2 A0 r R1B "XCAS'" A1 1 O2 24840 2488 4 W73 0 2 A0 r R1C "XRASX'" A1 1 O2 13640 2488 4 W74 0 2 A0 r R1D "XMEMRDY" A1 1 O0 10448 2488 4 W75 0 2 A0 r R1E "XPDWP" A1 1 O0 7240 2488 4 W76 0 2 A0 r R1F "XHINT" A1 1 OE 2488 6296 2 W77 0 2 A0 r R20 "XCLOCKOUT" A1 1 OE 2488 31896 2 4 A0 r R21 "WholeMiChip" AC PWCoreLayout OF AD Indirect 0 0 61536 61536 O10 A2 0 0 61536 61536 25 O11 AD -32 0 32832 42432 O12 A2 -32 0 32832 42432 23 O13 A2 0 0 32800 864 84 O14 A2 0 0 4720 832 2 O15 A2 0 0 4720 80 1 O16 A9 4720 80 A6 AA 0 0 0 0 2 A4 r RB AE InstanceName r RB 0 0 4720 80 R2 1059061760 0 0 0 0 0 0 0 O17 A2 0 0 4720 80 1 O16 0 0 0 2 A4 r RC AE r RC 0 0 4720 80 R2 1059061760 0 0 0 0 752 0 0 0 0 4720 832 R22 "MIInnerLeft1" 1031153506 0 1 0 0 0 0 0 O18 AD -16 0 128 856 O19 A2 -16 0 128 856 11 O1A A9 528 144 A6 AF nwel 0 128 328 2 1 A10 X r R23 "B" O1B A11 FlipText RB R24 "Xerox/TiogaFonts/Helvetica8" 2 0 32 48 0 1 A12 CDSatellitesGroupId i 58467 O1C A11 RC R24 2 0 32 760 0 1 A12 i 58465 O1D A9 80 32 A6 A13 nwelCont 0 16 792 0 1 A10 r R23 O1E A9 80 32 A6 A14 pwelCont 0 16 8 0 1 A10 r R23 O1F A15 C2SimpleCon A6 32 32 A6 A14 0 40 8 0 1 A10 r R23 O20 A15 A6 32 32 A6 A13 0 40 792 0 1 A10 r R23 O21 A9 80 80 A6 AA 0 16 752 0 4 A10 r R23 A4 r RC A12 i 58465 A16 SinixSatellites lor 1 RC O21 16 0 0 4 A10 r R23 A4 r RB A12 i 58467 A16 lor 1 RB O22 A9 32 832 A6 AB 0 40 0 0 3 A10 r R23 A12 i 58469 A16 lor 1 R25 "FeedIn" O23 A11 R25 R24 2 0 66 210 2 1 A12 i 58469 16 0 96 832 R26 "Feedthru.mask" 1048576000 0 1 1 A17 CDSatellitesOGroup i 74733 1 A18 CMosBExtractProc a A19 FakeExtract 4704 0 0 2 AE r R27 "WENT'-1" A1A StopEnumerateDeepPins a A1A O18 4784 0 0 2 AE r R28 "WENW'-1" A1A a A1A O18 4864 0 0 2 AE r R29 "PDWPout-1" A1A a A1A O18 4944 0 0 2 AE r R2A "PA10-1" A1A a A1A O24 AD -32 0 832 856 O25 A1B AbutX -32 0 832 856 1 1 O26 AD -32 0 832 856 O27 A2 -32 0 832 856 250 O28 A9 32 528 A6 AB 0 552 152 0 0 O29 A9 480 656 A6 AF 0 624 376 2 0 O2A A1C C2WellTrans A6 384 64 A6 A1D wpdif 0 504 400 2 0 O2B A9 16 80 A6 A1E pol 0 392 440 2 0 O2C A1F C2LWellTrans A6 80 368 A6 A1D 0 384 416 0 0 O2D A1C A6 368 64 A6 A1D 0 288 408 2 0 O2E A1C A6 160 64 A6 A1D 0 184 408 2 0 O2D 248 408 2 0 O2F A9 80 800 A6 AA 0 800 752 2 2 A12 i 58553 A16 lor 1 RC O2F 800 0 2 2 A12 i 58551 A16 lor 1 RB O22 24 0 0 2 A12 i 50649 A16 lor 1 R2B "CK" O30 A15 A6 32 32 A6 A20 ndif 1 A21 CDBringoverLibraryName r R2C "ramcontrol" 680 232 0 0 O31 A22 C2Trans A6 224 64 A6 A20 0 696 56 2 0 O32 A15 A6 32 32 A6 A1E 1 A21 r R2C 696 296 0 0 O33 A9 32 136 A6 A14 0 136 8 2 0 O34 A9 32 240 A6 A14 0 512 8 2 0 O35 A9 32 256 A6 AA 0 384 0 0 0 O1F 344 8 0 0 O1F 24 8 0 0 O1F 424 8 0 0 O2E 184 616 2 0 O36 A22 A6 96 64 A6 A20 0 184 224 2 0 O37 A23 C2PDifRect 48 48 A6 A1D 0 88 688 0 0 O38 A9 48 48 A6 A20 0 88 96 0 0 O39 A9 104 32 A6 A1E 0 56 344 0 0 O3A A23 16 128 A6 A1D 0 96 424 0 0 O3B A9 16 288 A6 A1E 0 144 280 0 0 O3C A9 32 80 A6 AB 0 200 376 2 1 A12 i 50679 O3D A9 16 32 A6 A1E 0 280 368 2 0 O3E A24 C2WellSimpleCon A6 32 32 A6 A1D 1 A21 r R2C 168 472 0 0 O3E 168 512 0 0 O3E 168 552 0 0 O3E 168 592 0 0 O32 296 104 0 0 O32 296 696 0 0 O31 760 56 2 0 O3F A23 80 144 A6 A1D 0 336 640 0 0 O3E 384 720 0 0 O3E 384 480 0 0 O3E 384 520 0 0 O3E 384 560 0 0 O40 A9 16 296 A6 A1E 0 528 264 0 0 O41 A9 16 56 A6 A1E 0 576 264 2 0 O2B 576 200 0 0 O2B 576 552 0 0 O42 A9 16 64 A6 A1E 0 360 552 2 0 O2B 296 552 0 0 O43 A9 16 112 A6 A1E 0 208 352 0 0 O44 A9 32 120 A6 A20 0 552 72 0 0 O3D 344 280 2 0 O45 A25 C2Via A6 32 32 A6 AB 0 216 312 0 0 O46 A9 24 32 A6 A1E 0 128 592 0 2 A12 i 51787 A16 lor 1 R2D "nc" O47 A11 R2B R24 2 0 24 766 0 1 A12 i 50649 O48 A9 16 48 A6 A1E 0 672 272 2 0 O49 A9 16 72 A6 A1E 0 624 272 0 0 O48 672 344 2 0 O4A A9 32 72 A6 AA 0 344 432 2 1 A12 i 50672 O4B A1C A6 56 80 A6 A1D 0 352 720 2 0 O4C A22 A6 56 80 A6 A20 0 352 56 2 0 O4D A9 48 120 A6 A20 0 336 72 0 0 O32 312 288 0 0 O4E A9 24 152 A6 AA 0 752 240 0 0 O3E 648 592 1 0 O3E 648 512 1 0 O3E 648 632 1 0 O3E 648 432 1 0 O3E 648 472 1 0 O3E 648 672 1 0 O3E 648 552 1 0 O3E 648 392 1 0 O4F A9 16 712 A6 A1E 0 720 56 0 0 O30 680 112 0 0 O50 A11 R2E "c" R24 2 0 128 382 0 0 O51 A11 R2D R24 2 0 128 606 0 1 A12 i 51787 O4A 560 416 2 1 A12 i 50540 O52 A11 R2F "D" R24 2 0 272 782 0 1 A12 i 50671 O32 96 592 0 0 O4A 128 696 2 0 O45 128 696 2 0 O3E 88 696 2 0 O30 96 256 0 0 O4A 24 344 0 0 O53 A9 32 88 A6 AA 0 720 296 2 0 O3E 680 632 0 0 O32 24 344 0 0 O45 24 384 0 0 O3E 680 552 0 0 O1F 744 8 0 0 O54 A23 32 384 A6 A1D 0 680 368 0 0 O55 A9 32 320 A6 AA 0 680 432 0 0 O3E 680 672 0 0 O56 A9 32 192 A6 AA 0 680 72 0 0 O3E 680 432 0 0 O3E 680 472 0 0 O3E 680 512 0 0 O45 648 296 0 0 O30 680 192 0 0 O30 680 152 0 0 O45 752 328 0 0 O30 744 208 0 0 O3E 744 392 0 0 O30 680 72 0 0 O3E 680 712 0 0 O3E 680 592 0 0 O57 A9 16 192 A6 A20 0 696 72 0 0 O58 A11 R30 "Q" R24 2 0 752 774 0 1 A12 i 50656 O59 A11 R31 "NQ" R24 2 0 664 774 0 1 A12 i 50657 O3E 96 472 0 0 O32 96 168 0 0 O45 96 136 6 0 O32 224 272 1 0 O5A A23 16 40 A6 A1D 0 320 648 0 0 O30 168 96 0 0 O3E 168 712 0 0 O3E 168 672 0 0 O3E 168 632 0 0 O3E 272 432 0 0 O32 248 376 0 0 O30 272 288 0 0 O3E 320 576 0 0 O30 320 224 0 0 O45 328 152 0 0 O32 312 432 0 0 O42 296 200 0 0 O5B A1C A6 56 64 A6 A1D 0 360 656 4 0 O45 328 648 0 0 O5C A9 16 80 A6 A20 0 272 240 0 0 O3D 328 264 2 0 O5D A9 16 40 A6 A20 0 320 144 0 0 O3E 336 752 0 0 O30 352 72 0 0 O30 168 136 0 0 O5E A9 32 184 A6 A20 0 384 72 0 0 O32 512 104 0 0 O5A 536 648 0 0 O30 384 144 0 0 O3E 384 680 0 0 O3E 384 640 0 0 O3E 384 600 0 0 O3E 488 416 0 0 O30 488 288 0 0 O3E 536 576 0 0 O30 536 224 0 0 O45 544 152 0 0 O32 528 416 0 0 O42 512 200 0 0 O5C 488 240 0 0 O3D 544 264 2 0 O5D 536 144 0 0 O3E 552 752 0 0 O30 552 40 0 0 O30 384 224 0 0 O30 384 184 0 0 O3E 96 424 0 0 O3E 96 520 0 0 O3A 112 424 0 0 O3E 744 552 0 0 O3E 744 672 0 0 O3E 744 472 0 0 O3E 744 432 0 0 O3E 744 632 0 0 O3E 744 512 0 0 O3E 744 592 0 0 O30 744 168 0 0 O30 744 128 0 0 O5F A9 24 192 A6 A20 0 752 72 0 0 O30 648 128 1 0 O30 648 168 1 0 O30 648 208 1 0 O60 A9 32 576 A6 AA 0 616 128 0 0 O5F 640 72 1 0 O61 A9 32 312 A6 AA 0 744 392 0 0 O62 A9 32 112 A6 AA 0 744 128 0 0 O63 A11 R32 "s" R24 2 0 496 342 0 1 A12 i 51791 O64 A9 32 152 A6 AA 0 488 288 0 2 A12 i 51791 A16 lor 1 R32 O4A 344 288 2 0 O32 512 696 0 0 O65 A23 32 144 A6 A1D 0 552 640 0 0 O5B 576 656 4 0 O45 544 648 0 0 O66 A22 A6 56 64 A6 A20 0 576 240 4 0 O3D 224 352 2 0 O45 168 376 0 0 O2B 512 552 0 0 O41 576 552 2 0 O67 A9 16 128 A6 A1E 0 440 280 2 0 O68 A9 16 96 A6 A1E 0 360 200 0 0 O69 A9 24 72 A6 AA 0 200 272 0 0 O6A A9 32 48 A6 AB 0 264 312 2 0 O68 192 272 0 0 O6B A11 R33 "m" R24 2 0 320 390 0 1 A12 i 51793 O2B 360 552 0 0 O6C A23 32 280 A6 A1D 0 384 480 0 0 O6D A9 32 280 A6 AA 0 384 480 0 0 O6E A1C A6 424 64 A6 A1D 0 696 352 2 0 O6E 760 352 2 0 O6F A23 24 392 A6 A1D 0 640 368 1 0 O6F 752 368 0 0 O4C 568 56 2 0 O66 360 240 4 0 O4E 304 104 0 0 O4E 520 104 0 0 O4B 568 728 2 0 O4E 520 576 0 0 O4E 304 576 0 0 O70 A23 32 288 A6 A1D 0 168 472 0 0 O71 A9 32 288 A6 AA 0 168 472 0 0 O30 168 176 0 0 O72 A9 32 248 A6 AA 0 168 0 0 0 O73 A9 16 368 A6 A1E 0 248 384 0 0 O30 168 216 0 0 O74 A9 16 264 A6 A1E 0 248 8 0 0 O31 288 56 2 0 O31 248 56 2 0 O75 A9 32 192 A6 A20 0 168 72 0 0 O76 A9 16 232 A6 A1E 0 480 352 2 0 O77 A22 A6 232 64 A6 A20 0 504 56 2 0 O77 464 56 2 0 O78 A9 16 40 A6 A1E 0 464 776 0 0 O2B 464 288 0 0 O79 A9 16 120 A6 A1E 0 320 432 0 0 O28 336 152 0 0 O7A A9 32 176 A6 AA 0 312 288 0 2 A12 i 51793 A16 lor 1 R33 O7B A9 16 192 A6 A1E 0 144 8 0 0 O79 264 8 2 0 O46 128 168 0 2 A12 i 51785 A16 lor 1 R2D O51 128 174 0 1 A12 i 51785 O76 144 592 0 0 O7C A9 16 336 A6 A1E 0 480 808 2 0 O30 56 136 6 0 O4A 56 136 6 0 O7D A22 A6 104 64 A6 A20 0 184 56 2 0 O7E A9 32 456 A6 AA 0 96 168 0 1 A12 i 50655 O7F A9 32 624 A6 AB 0 96 104 0 0 O80 A9 24 80 A6 AA 0 248 384 2 0 O1F 664 8 0 0 O20 24 792 0 0 O81 A9 32 136 A6 A13 0 136 792 2 0 O22 664 0 0 2 A12 i 50657 A16 lor 1 R31 O82 A9 32 176 A6 A14 0 800 8 2 0 O1F 664 8 0 0 O22 744 0 0 2 A12 i 50656 A16 lor 1 R30 O83 A9 32 184 A6 A13 0 800 792 2 0 O20 664 792 0 0 O22 264 832 5 2 A12 i 50671 A16 lor 1 R2F O20 744 792 0 0 O1B 544 16 0 1 A12 i 58551 O1C 512 792 0 1 A12 i 58553 O84 A9 528 216 A6 AF 0 832 328 2 0 O85 A9 32 104 A6 A1E 0 640 272 2 0 0 0 800 832 R34 "ff.mask" 1048576000 0 1 1 A17 i 74742 1 A18 a A19 0 1 A18 a A19 5040 0 0 2 AE r R35 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 5840 0 0 2 AE r R36 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1" A1A a A1A O24 6640 0 0 2 AE r R37 "/0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1*1" A1A a A1A O24 7440 0 0 2 AE r R38 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1" A1A a A1A O86 AD -32 0 192 856 O87 A1B -32 0 192 856 1 1 O88 AD -8 0 216 856 O89 A2 -8 0 216 856 74 O8A A9 528 224 A6 AF 0 216 328 2 1 A10 r R23 O8B A9 160 80 A6 AA 0 24 0 0 4 A10 r R23 A4 r RB A12 i 58497 A16 lor 1 RB O1F 48 8 0 1 A10 r R23 O1E 24 8 0 1 A10 r R23 O22 48 0 0 3 A10 r R23 A12 i 58493 A16 lor 1 R39 "I" O8C A11 R3A "X" R24 2 0 136 288 0 1 A12 i 58495 O8D A11 R39 R24 2 0 56 280 0 1 A12 i 58493 O1C 80 792 0 1 A12 i 58491 O20 128 792 0 1 A10 r R23 O1D 104 792 0 1 A10 r R23 O45 128 376 0 0 O45 48 376 0 0 O8E A9 32 32 A6 AB 0 80 0 2 2 A4 r R39 A26 Export a A27 TRUE O8F A9 32 80 A6 AA 0 24 752 0 2 A4 r RC A26 a A27 O90 A9 24 144 A6 AA 0 128 248 0 0 O30 128 232 0 0 O91 A9 32 48 A6 AA 0 128 224 0 0 O30 128 184 0 0 O91 128 176 0 0 O30 128 136 0 0 O91 128 128 0 0 O30 48 232 0 0 O91 48 224 0 0 O30 48 184 0 0 O91 48 176 0 0 O30 48 136 0 0 O91 48 128 0 0 O30 48 88 0 0 O91 48 80 0 0 O3E 128 424 0 0 O3E 128 472 0 0 O92 A9 48 32 A6 AA 0 160 464 2 0 O3E 128 520 0 0 O92 160 512 2 0 O3E 128 568 0 0 O92 160 560 2 0 O3E 128 616 0 0 O92 160 608 2 0 O3E 128 664 0 0 O92 160 656 2 0 O3E 48 472 0 0 O92 80 464 2 0 O3E 48 520 0 0 O92 80 512 2 0 O3E 48 568 0 0 O92 80 560 2 0 O3E 48 616 0 0 O92 80 608 2 0 O3E 48 664 0 0 O92 80 656 2 0 O3E 48 712 0 0 O92 80 704 2 0 O1F 128 8 0 1 A10 r R23 O1E 104 8 0 1 A10 r R23 O41 96 288 0 1 A10 r R3B "TN" O31 136 64 2 1 A10 r R3B O78 96 312 0 1 A10 r R3C "TP" O93 A9 40 192 A6 A20 0 40 80 0 1 A10 r R3B O93 128 80 0 1 A10 r R3B O94 A1C A6 428 64 A6 A1D 0 136 352 2 1 A10 r R3C O32 68 312 0 1 A10 r R3D "T" O20 48 792 0 1 A10 r R23 O95 A9 40 32 A6 A1E 0 64 312 0 1 A10 r R3D O96 A9 24 96 A6 AA 0 56 312 0 1 A10 r R3D O92 160 368 2 0 O92 160 416 2 0 O97 A23 32 396 A6 A1D 0 136 368 0 1 A10 r R3C O97 40 368 0 1 A10 r R3C O1D 24 792 0 1 A10 r R23 O8B 24 752 0 4 A10 r R23 A4 r RC A12 i 58491 A16 lor 1 RC O22 128 0 0 3 A10 r R23 A12 i 58495 A16 lor 1 R3A O8F 24 0 0 2 A4 r RB A26 a A27 O8E 160 0 2 2 A4 r R3A A26 a A27 O1B 88 48 0 1 A12 i 58497 24 0 184 832 R3E "C2IV00A.mask" 1048576000 0 1 2 A28 PinOrder r R3F "I X Vdd Gnd" A17 i 74740 1 A18 a A19 0 1 A18 a A19 8240 0 0 2 AE r R40 "/0(MiChip)/6(AddrCtl)/14(Decoder)/4(Inv)" A1A a A1A O86 8400 0 0 2 AE r R41 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv9" A1A a A1A O98 AD -32 0 352 864 O99 A1B -32 0 352 864 1 1 O9A AD -8 0 376 864 O9B A2 -8 0 376 864 125 O9C A9 320 80 A6 AA 0 24 0 0 4 A10 r R23 A4 r RB A12 i 59108 A16 lor 1 RB O9D A9 536 384 A6 AF 0 376 328 2 1 A10 r R23 O8C 304 280 0 1 A12 i 59106 O9E A11 R42 "I-C" R24 2 0 208 280 0 1 A12 i 59104 O9F A11 R43 "I-B" R24 2 0 128 280 0 1 A12 i 59102 OA0 A11 R44 "I-A" R24 2 0 48 280 0 1 A12 i 59100 O1C 160 800 0 1 A12 i 59098 O1D 264 792 0 1 A10 r R23 O1D 24 792 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1E 24 8 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O20 48 792 0 1 A10 r R23 O91 48 368 0 1 A10 r R3D OA1 A9 24 56 A6 AA 0 56 312 0 1 A10 r R3D O32 68 312 0 1 A10 r R3D OA2 A23 24 396 A6 A1D 0 136 368 0 1 A10 r R3C O94 136 352 2 1 A10 r R3C O93 128 80 0 1 A10 r R3B O93 40 80 0 1 A10 r R3B O78 96 312 0 1 A10 r R3C O31 136 64 2 1 A10 r R3B O41 96 288 0 1 A10 r R3B O1D 104 792 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1E 104 8 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O20 128 792 0 1 A10 r R23 O91 128 368 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O32 148 312 0 1 A10 r R3D OA2 216 368 0 1 A10 r R3C OA2 128 368 0 1 A10 r R3C O94 216 352 2 1 A10 r R3C O93 208 80 0 1 A10 r R3B O93 120 80 0 1 A10 r R3B O78 176 312 0 1 A10 r R3C O31 216 64 2 1 A10 r R3B O41 176 288 0 1 A10 r R3B O1D 184 792 0 1 A10 r R23 O95 224 312 0 1 A10 r R3D O1E 184 8 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O20 208 792 0 1 A10 r R23 O91 208 368 0 1 A10 r R3D OA1 216 312 0 1 A10 r R3D O32 228 312 0 1 A10 r R3D OA2 208 368 0 1 A10 r R3C O94 296 352 2 1 A10 r R3C O93 288 80 0 1 A10 r R3B O93 200 80 0 1 A10 r R3B O78 256 312 0 1 A10 r R3C O31 296 64 2 1 A10 r R3B O41 256 288 0 1 A10 r R3B O1E 264 8 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O20 288 792 0 1 A10 r R23 O92 80 704 2 0 O3E 48 712 0 0 O92 80 656 2 0 O3E 48 664 0 0 O92 80 608 2 0 O3E 48 616 0 0 O92 80 560 2 0 O3E 48 568 0 0 O92 80 512 2 0 O3E 48 520 0 0 O92 80 464 2 0 O3E 48 472 0 0 O92 320 656 2 0 O3E 288 664 0 0 O92 320 608 2 0 O3E 288 616 0 0 O92 320 560 2 0 O3E 288 568 0 0 O92 320 512 2 0 O3E 288 520 0 0 O92 320 464 2 0 O3E 288 472 0 0 O92 320 416 2 0 O3E 288 424 0 0 O91 48 80 0 0 O30 48 88 0 0 O91 48 128 0 0 O30 48 136 0 0 O91 48 176 0 0 O30 48 184 0 0 O91 48 224 0 0 O30 48 232 0 0 O91 128 128 0 0 O30 128 136 0 0 O91 128 176 0 0 O30 128 184 0 0 O91 128 224 0 0 O30 128 232 0 0 O91 208 80 0 0 O30 208 88 0 0 O91 208 128 0 0 O30 208 136 0 0 O91 208 176 0 0 O30 208 184 0 0 O91 288 128 0 0 O30 288 136 0 0 O91 288 176 0 0 O30 288 184 0 0 O91 288 224 0 0 O30 288 232 0 0 OA3 A9 176 24 A6 AA 0 136 248 0 0 O90 288 248 0 0 O92 80 368 2 0 O45 48 376 0 0 O92 160 368 2 0 O45 128 376 0 0 O92 240 368 2 0 O45 208 376 0 0 O92 320 368 2 0 O45 288 376 0 0 O97 40 368 0 1 A10 r R3C O97 296 368 0 1 A10 r R3C O9C 24 752 0 4 A10 r R23 A4 r RC A12 i 59098 A16 lor 1 RC O22 48 0 0 3 A10 r R23 A12 i 59100 A16 lor 1 R44 O22 128 0 0 3 A10 r R23 A12 i 59102 A16 lor 1 R43 O22 208 0 0 3 A10 r R23 A12 i 59104 A16 lor 1 R42 O22 288 0 0 3 A10 r R23 A12 i 59106 A16 lor 1 R3A O1B 160 16 0 1 A12 i 59108 24 0 344 832 R45 "C2NO03A.mask" 1048576000 0 1 2 A28 r R46 "I-A I-B I-C X Vdd Gnd" A17 i 74739 1 A18 a A19 0 1 A18 a A19 8560 0 0 2 AE r R47 "/0(MiChip)/6(AddrCtl)/14(Decoder)/1(NormalizedNor3)/0(Nor3)" A1A a A1A OA4 AD -32 0 432 856 OA5 A1B -32 0 432 856 1 1 OA6 AD -8 0 456 856 OA7 A2 -8 0 456 856 163 OA8 A9 400 80 A6 AA 0 24 0 0 4 A10 r R23 A4 r RB A12 i 59281 A16 lor 1 RB OA8 24 752 0 4 A10 r R23 A4 r RC A12 i 59279 A16 lor 1 RC O1D 104 792 0 1 A10 r R23 O1D 184 792 0 1 A10 r R23 OA9 A9 528 464 A6 AF 0 456 328 2 1 A10 r R23 O1D 24 792 0 1 A10 r R23 O22 368 0 0 3 A10 r R23 A12 i 59254 A16 lor 1 R3A O22 288 0 0 3 A10 r R23 A12 i 59252 A16 lor 1 R2F OAA A9 336 24 A6 AA 0 56 248 0 0 O22 208 0 0 3 A10 r R23 A12 i 59250 A16 lor 1 R48 "C" O22 128 0 0 3 A10 r R23 A12 i 59248 A16 lor 1 R23 O31 216 64 2 1 A10 r R3B O22 48 0 0 3 A10 r R23 A12 i 59246 A16 lor 1 R49 "A" O95 64 312 0 1 A10 r R3D O1E 24 8 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O20 48 792 0 1 A10 r R23 O91 48 368 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O32 68 312 0 1 A10 r R3D OA2 136 368 0 1 A10 r R3C O94 136 352 2 1 A10 r R3C O93 128 80 0 1 A10 r R3B O93 40 80 0 1 A10 r R3B O78 96 312 0 1 A10 r R3C O31 136 64 2 1 A10 r R3B O41 96 288 0 1 A10 r R3B O95 144 312 0 1 A10 r R3D O1E 104 8 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O20 128 792 0 1 A10 r R23 O91 128 368 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O32 148 312 0 1 A10 r R3D OA2 216 368 0 1 A10 r R3C OA2 128 368 0 1 A10 r R3C O94 216 352 2 1 A10 r R3C O93 208 80 0 1 A10 r R3B O93 120 80 0 1 A10 r R3B O78 176 312 0 1 A10 r R3C O41 176 288 0 1 A10 r R3B O95 224 312 0 1 A10 r R3D O1E 184 8 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O20 208 792 0 1 A10 r R23 O91 208 368 0 1 A10 r R3D OA1 216 312 0 1 A10 r R3D O32 228 312 0 1 A10 r R3D OA2 296 368 0 1 A10 r R3C OA2 208 368 0 1 A10 r R3C O94 296 352 2 1 A10 r R3C O93 288 80 0 1 A10 r R3B O93 200 80 0 1 A10 r R3B O78 256 312 0 1 A10 r R3C O31 296 64 2 1 A10 r R3B O41 256 288 0 1 A10 r R3B O95 304 312 0 1 A10 r R3D O1E 264 8 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O20 288 792 0 1 A10 r R23 O91 288 368 0 1 A10 r R3D OA1 296 312 0 1 A10 r R3D O32 308 312 0 1 A10 r R3D OA2 288 368 0 1 A10 r R3C O94 376 352 2 1 A10 r R3C O93 368 80 0 1 A10 r R3B O93 280 80 0 1 A10 r R3B O78 336 312 0 1 A10 r R3C O31 376 64 2 1 A10 r R3B O41 336 288 0 1 A10 r R3B O1D 344 792 0 1 A10 r R23 O1E 344 8 0 1 A10 r R23 O1F 368 8 0 1 A10 r R23 O20 368 792 0 1 A10 r R23 O92 80 656 2 0 O3E 48 664 0 0 O92 80 608 2 0 O3E 48 616 0 0 O92 80 560 2 0 O3E 48 568 0 0 O92 80 512 2 0 O3E 48 520 0 0 O92 80 464 2 0 O3E 48 472 0 0 O92 160 704 2 0 O3E 128 712 0 0 O92 160 656 2 0 O3E 128 664 0 0 O92 160 608 2 0 O3E 128 616 0 0 O92 160 560 2 0 O3E 128 568 0 0 O92 160 512 2 0 O3E 128 520 0 0 O92 240 656 2 0 O3E 208 664 0 0 O92 240 608 2 0 O3E 208 616 0 0 O92 240 560 2 0 O3E 208 568 0 0 O92 240 512 2 0 O3E 208 520 0 0 O92 240 464 2 0 O3E 208 472 0 0 O92 320 608 2 0 O3E 288 616 0 0 O92 320 560 2 0 O3E 288 568 0 0 O92 320 512 2 0 O3E 288 520 0 0 O92 320 464 2 0 O3E 288 472 0 0 O92 400 656 2 0 O3E 368 664 0 0 O92 400 608 2 0 O3E 368 616 0 0 O92 400 560 2 0 O3E 368 568 0 0 O92 400 512 2 0 O3E 368 520 0 0 OA3 56 464 0 0 OA3 216 680 0 0 OAB A9 96 24 A6 AA 0 296 464 0 0 O90 376 344 0 0 O91 48 128 0 0 O30 48 136 0 0 O91 48 176 0 0 O30 48 184 0 0 O91 48 224 0 0 O30 48 232 0 0 O91 208 80 0 0 O30 208 88 0 0 O91 208 128 0 0 O30 208 136 0 0 O91 208 176 0 0 O30 208 184 0 0 O91 368 128 0 0 O30 368 136 0 0 O91 368 176 0 0 O30 368 184 0 0 O91 368 224 0 0 O30 368 232 0 0 O96 376 248 0 0 O92 80 368 2 0 O45 48 376 0 0 O92 160 368 2 0 O45 128 376 0 0 O92 240 368 2 0 O45 208 376 0 0 O92 320 368 2 0 O45 288 376 0 0 O92 400 368 2 0 O45 368 376 0 0 O97 40 368 0 1 A10 r R3C O97 376 368 0 1 A10 r R3C OAC A11 R49 R24 2 0 48 280 0 1 A12 i 59246 OAD A11 R23 R24 2 0 128 280 0 1 A12 i 59248 OAE A11 R48 R24 2 0 208 280 0 1 A12 i 59250 O52 288 280 0 1 A12 i 59252 O8C 368 280 0 1 A12 i 59254 O1D 264 792 0 1 A10 r R23 O1C 168 792 0 1 A12 i 59279 O1B 248 16 0 1 A12 i 59281 24 0 424 832 R4A "a22o2i.mask" 1048576000 0 1 2 A28 r R4B "A B C D X Vdd Gnd" A17 i 74746 1 A18 a A19 0 1 A18 a A19 8880 0 0 2 AE r R4C "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1" A1A a A1A O24 9280 0 0 2 AE r R4D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1" A1A a A1A OAF AD -32 0 272 856 OB0 A1B -32 0 272 856 1 1 OB1 AD -8 0 296 856 OB2 A2 -8 0 296 856 100 OB3 A9 528 304 A6 AF 0 296 328 2 1 A10 r R23 O94 136 352 2 1 A10 r R3C O22 208 0 0 3 A10 r R23 A12 i 58611 A16 lor 1 R3A O22 128 0 0 3 A10 r R23 A12 i 58609 A16 lor 1 R43 O22 48 0 0 3 A10 r R23 A12 i 58607 A16 lor 1 R44 O1D 24 792 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1E 24 8 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O20 48 792 0 1 A10 r R23 O91 48 368 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O32 68 312 0 1 A10 r R3D OA2 136 368 0 1 A10 r R3C O93 128 80 0 1 A10 r R3B O93 40 80 0 1 A10 r R3B O78 96 312 0 1 A10 r R3C O31 136 64 2 1 A10 r R3B O41 96 288 0 1 A10 r R3B O1D 104 792 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1E 104 8 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O20 128 792 0 1 A10 r R23 O91 128 368 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O32 148 312 0 1 A10 r R3D OA2 128 368 0 1 A10 r R3C O94 216 352 2 1 A10 r R3C O93 208 80 0 1 A10 r R3B O93 120 80 0 1 A10 r R3B O78 176 312 0 1 A10 r R3C O31 216 64 2 1 A10 r R3B O41 176 288 0 1 A10 r R3B O1D 184 792 0 1 A10 r R23 O1E 184 8 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O20 208 792 0 1 A10 r R23 O92 80 656 2 0 O3E 48 664 0 0 O92 80 608 2 0 O3E 48 616 0 0 O92 80 560 2 0 O3E 48 568 0 0 O92 80 512 2 0 O3E 48 520 0 0 O92 80 464 2 0 O3E 48 472 0 0 O92 160 704 2 0 O3E 128 712 0 0 O92 160 656 2 0 O3E 128 664 0 0 O92 160 608 2 0 O3E 128 616 0 0 O92 160 560 2 0 O3E 128 568 0 0 O92 160 512 2 0 O3E 128 520 0 0 O92 240 656 2 0 O3E 208 664 0 0 O92 240 608 2 0 O3E 208 616 0 0 O92 240 560 2 0 O3E 208 568 0 0 O92 240 512 2 0 O3E 208 520 0 0 O92 240 464 2 0 O3E 208 472 0 0 OB4 A9 184 24 A6 AA 0 56 464 0 0 O90 216 344 0 0 O91 48 80 0 0 O30 48 88 0 0 O91 48 128 0 0 O30 48 136 0 0 O91 48 176 0 0 O30 48 184 0 0 O91 48 224 0 0 O30 48 232 0 0 O91 208 128 0 0 O30 208 136 0 0 O91 208 176 0 0 O30 208 184 0 0 O91 208 224 0 0 O30 208 232 0 0 O90 208 248 0 0 O92 80 368 2 0 O45 48 376 0 0 O92 160 368 2 0 O45 128 376 0 0 O92 240 368 2 0 O45 208 376 0 0 O97 40 368 0 1 A10 r R3C O97 216 368 0 1 A10 r R3C OA0 48 280 0 1 A12 i 58607 O9F 128 280 0 1 A12 i 58609 O8C 216 280 0 1 A12 i 58611 O1C 120 768 0 1 A12 i 58613 O1B 112 48 0 1 A12 i 58615 OB5 A9 240 80 A6 AA 0 24 0 0 4 A10 r R23 A4 r RB A12 i 58615 A16 lor 1 RB OB5 24 752 0 4 A10 r R23 A4 r RC A12 i 58613 A16 lor 1 RC 24 0 264 832 R4E "C2NA02A.mask" 1048576000 0 1 2 A28 r R4F "I-A I-B X Vdd Gnd" A17 i 74743 1 A18 a A19 0 1 A18 a A19 10080 0 0 2 AE r R50 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/5/6/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 10304 0 0 2 AE r R51 "RASX'-1" A1A a A1A O98 10400 0 0 2 AE r R52 "/0(MiChip)/6(AddrCtl)/14(Decoder)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O86 10720 0 0 2 AE r R53 "/0(MiChip)/6(AddrCtl)/14(Decoder)/7(Inv)" A1A a A1A O86 10880 0 0 2 AE r R54 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/2/1(Inv)*1" A1A a A1A O86 11040 0 0 2 AE r R55 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/3/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/4/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/5/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/2/0(Inv)*1*1*1*1" A1A a A1A O86 11200 0 0 2 AE r R56 "/0(MiChip)/0(RasDecode)/8(DecoderS)/9(Inv)" A1A a A1A O86 11360 0 0 2 AE r R57 "/0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1*1" A1A a A1A O18 11504 0 0 2 AE r R58 "RAS0'-1" A1A a A1A O98 11600 0 0 2 AE r R59 "/0(MiChip)/0(RasDecode)/8(DecoderS)/1(NormalizedNor3)/0(Nor3)" A1A a A1A O18 11904 0 0 2 AE r R5A "PDin0-1" A1A a A1A O18 11984 0 0 2 AE r R5B "PA4-1" A1A a A1A O86 12080 0 0 2 AE r R5C "/0(MiChip)/6(AddrCtl)/14(Decoder)/5(Inv)" A1A a A1A OB6 AD -32 0 512 856 OB7 A1B -32 0 512 856 1 1 OB8 AD -8 0 536 856 OB9 A2 -8 0 536 856 144 O7A 128 528 0 0 O94 216 352 2 1 A10 r R3C OA2 136 368 0 1 A10 r R3C O22 128 0 0 3 A10 r R23 A12 i 59235 A16 lor 1 R44 O7A 288 528 0 0 OA2 288 368 0 1 A10 r R3C OA2 296 368 0 1 A10 r R3C OBA A9 528 544 A6 AF 0 536 328 2 1 A10 r R23 OBB A9 480 80 A6 AA 0 24 0 0 4 A10 r R23 A4 r RB A12 i 59239 A16 lor 1 RB O8C 448 280 0 1 A12 i 59237 OA0 128 280 0 1 A12 i 59235 O9F 48 280 0 1 A12 i 59233 O1C 248 792 0 1 A12 i 59231 O97 40 368 0 1 A10 r R3C O45 48 376 0 0 O94 136 352 2 1 A10 r R3C OA2 128 368 0 1 A10 r R3C O3E 448 664 0 0 O3E 448 712 0 0 O3E 448 616 0 0 OBC A9 144 32 A6 AA 0 480 616 2 0 O3E 208 664 0 0 OA2 208 368 0 1 A10 r R3C O31 376 64 2 1 A10 r R3B O93 448 80 0 1 A10 r R3B O53 288 184 0 0 O93 280 80 0 1 A10 r R3B O93 288 80 0 1 A10 r R3B OBD A9 192 24 A6 AA 0 288 184 0 0 O93 360 80 0 1 A10 r R3B OBE A9 112 24 A6 AA 0 368 248 0 0 O93 368 80 0 1 A10 r R3B O94 296 352 2 1 A10 r R3C OAB 136 528 0 0 O3E 128 528 0 0 O94 376 352 2 1 A10 r R3C O94 456 352 2 1 A10 r R3C O45 208 376 0 0 O96 456 248 0 0 OB4 56 248 0 0 O30 448 184 0 0 O30 368 232 0 0 O30 288 232 0 0 O30 288 184 0 0 O30 208 184 0 0 O91 208 176 0 0 O30 208 136 0 0 O91 208 128 0 0 O30 208 88 0 0 O91 208 80 0 0 O30 48 184 0 0 OBF A9 24 112 A6 AA 0 296 344 0 0 OBF 136 344 0 0 OC0 A9 24 160 A6 AA 0 376 344 0 0 OC0 56 344 0 0 O3E 288 528 0 0 O45 208 528 0 0 O3E 208 712 0 0 O3E 128 576 0 0 O20 448 792 0 1 A10 r R23 O1F 448 8 0 1 A10 r R23 O1E 424 8 0 1 A10 r R23 O1D 424 792 0 1 A10 r R23 O78 416 312 0 1 A10 r R3C OA2 368 368 0 1 A10 r R3C O32 388 312 0 1 A10 r R3D OA1 376 312 0 1 A10 r R3D O20 368 792 0 1 A10 r R23 O1F 368 8 0 1 A10 r R23 O1E 344 8 0 1 A10 r R23 O95 384 312 0 1 A10 r R3D O1D 344 792 0 1 A10 r R23 O78 336 312 0 1 A10 r R3C OA2 376 368 0 1 A10 r R3C O32 308 312 0 1 A10 r R3D OA1 296 312 0 1 A10 r R3D O20 288 792 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O1E 264 8 0 1 A10 r R23 O95 304 312 0 1 A10 r R3D O1D 264 792 0 1 A10 r R23 O31 296 64 2 1 A10 r R3B O78 256 312 0 1 A10 r R3C O93 200 80 0 1 A10 r R3B O32 228 312 0 1 A10 r R3D O20 208 792 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O1E 184 8 0 1 A10 r R23 O95 224 312 0 1 A10 r R3D O31 216 64 2 1 A10 r R3B O78 176 312 0 1 A10 r R3C O93 120 80 0 1 A10 r R3B O93 208 80 0 1 A10 r R3B O32 148 312 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O20 48 792 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O1E 104 8 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1D 104 792 0 1 A10 r R23 O31 136 64 2 1 A10 r R3B O78 96 312 0 1 A10 r R3C O93 128 80 0 1 A10 r R3B O32 68 312 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O20 128 792 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O1E 24 8 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1D 24 792 0 1 A10 r R23 OC1 A9 24 208 A6 AA 0 456 344 0 0 OB4 136 432 0 0 OC2 A9 344 24 A6 AA 0 56 480 0 0 O3E 288 576 0 0 OB4 296 528 0 0 OC0 216 248 0 0 OC3 A9 32 184 A6 AB 0 208 376 0 1 A10 r R23 O93 40 80 0 1 A10 r R3B O30 48 232 0 0 O53 48 184 0 0 O41 96 288 0 1 A10 r R3B O41 176 288 0 1 A10 r R3B O41 256 288 0 1 A10 r R3B O41 336 288 0 1 A10 r R3B O41 416 288 0 1 A10 r R3B O3E 208 616 0 0 OBC 240 616 2 0 OBC 80 616 2 0 O3E 48 616 0 0 O3E 48 712 0 0 O3E 48 664 0 0 O97 456 368 0 1 A10 r R3C O45 448 376 0 0 O45 128 376 0 0 O1D 184 792 0 1 A10 r R23 OBB 24 752 0 4 A10 r R23 A4 r RC A12 i 59231 A16 lor 1 RC O22 48 0 0 3 A10 r R23 A12 i 59233 A16 lor 1 R43 O31 456 64 2 1 A10 r R3B O22 448 0 0 3 A10 r R23 A12 i 59237 A16 lor 1 R3A O1B 240 16 0 1 A12 i 59239 O3E 288 624 0 0 O3E 288 672 0 0 O3E 128 624 0 0 O3E 128 672 0 0 24 0 504 832 R5D "C2XN02A.mask" 1048576000 0 1 2 A28 r R4F A17 i 74749 1 A18 a A19 0 1 A18 a A19 12240 0 0 2 AE r R5E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1" A1A a A1A OC4 AD -32 0 352 856 OC5 A1B -32 0 352 856 1 1 OC6 AD -8 0 376 856 OC7 A2 -8 0 376 856 135 O9C 24 0 0 4 A10 r R23 A4 r RB A12 i 59330 A16 lor 1 RB O22 288 0 0 3 A10 r R23 A12 i 59328 A16 lor 1 R3A O22 208 0 0 3 A10 r R23 A12 i 59326 A16 lor 1 R48 O22 128 0 0 3 A10 r R23 A12 i 59324 A16 lor 1 R23 O22 48 0 0 3 A10 r R23 A12 i 59322 A16 lor 1 R49 O9C 24 752 0 4 A10 r R23 A4 r RC A12 i 59320 A16 lor 1 RC OC8 A9 528 384 A6 AF 0 376 328 2 1 A10 r R23 O1D 24 792 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1E 24 8 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O20 48 792 0 1 A10 r R23 O91 48 368 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O32 68 312 0 1 A10 r R3D OA2 136 368 0 1 A10 r R3C O94 136 352 2 1 A10 r R3C O93 128 80 0 1 A10 r R3B O93 40 80 0 1 A10 r R3B O78 96 312 0 1 A10 r R3C O31 136 64 2 1 A10 r R3B O41 96 288 0 1 A10 r R3B O1D 104 792 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1E 104 8 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O20 128 792 0 1 A10 r R23 O91 128 368 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O32 148 312 0 1 A10 r R3D OA2 216 368 0 1 A10 r R3C OA2 128 368 0 1 A10 r R3C O94 216 352 2 1 A10 r R3C O93 208 80 0 1 A10 r R3B O93 120 80 0 1 A10 r R3B O78 176 312 0 1 A10 r R3C O31 216 64 2 1 A10 r R3B O41 176 288 0 1 A10 r R3B O1D 184 792 0 1 A10 r R23 O95 224 312 0 1 A10 r R3D O1E 184 8 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O20 208 792 0 1 A10 r R23 O91 208 368 0 1 A10 r R3D OA1 216 312 0 1 A10 r R3D O32 228 312 0 1 A10 r R3D OA2 208 368 0 1 A10 r R3C O94 296 352 2 1 A10 r R3C O93 288 80 0 1 A10 r R3B O93 200 80 0 1 A10 r R3B O78 256 312 0 1 A10 r R3C O31 296 64 2 1 A10 r R3B O41 256 288 0 1 A10 r R3B O1D 264 792 0 1 A10 r R23 O1E 264 8 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O20 288 792 0 1 A10 r R23 O92 80 656 2 0 O3E 48 664 0 0 O92 80 608 2 0 O3E 48 616 0 0 O92 80 560 2 0 O3E 48 568 0 0 O92 80 512 2 0 O3E 48 520 0 0 O92 80 464 2 0 O3E 48 472 0 0 O92 160 704 2 0 O3E 128 712 0 0 O92 160 656 2 0 O3E 128 664 0 0 O92 160 608 2 0 O3E 128 616 0 0 O92 160 560 2 0 O3E 128 568 0 0 O92 160 512 2 0 O3E 128 520 0 0 O92 240 656 2 0 O3E 208 664 0 0 O92 240 608 2 0 O3E 208 616 0 0 O92 240 560 2 0 O3E 208 568 0 0 O92 240 512 2 0 O3E 208 520 0 0 O92 240 464 2 0 O3E 208 472 0 0 O92 320 656 2 0 O3E 288 664 0 0 O92 320 608 2 0 O3E 288 616 0 0 O92 320 560 2 0 O3E 288 568 0 0 O92 320 512 2 0 O3E 288 520 0 0 O92 320 464 2 0 O3E 288 472 0 0 OA3 56 464 0 0 O90 296 344 0 0 O91 48 128 0 0 O30 48 136 0 0 O91 48 176 0 0 O30 48 184 0 0 O91 48 224 0 0 O30 48 232 0 0 O91 208 80 0 0 O30 208 88 0 0 O91 208 128 0 0 O30 208 136 0 0 O91 208 176 0 0 O30 208 184 0 0 O91 288 128 0 0 O30 288 136 0 0 O91 288 176 0 0 O30 288 184 0 0 O91 288 224 0 0 O30 288 232 0 0 OC9 A9 256 24 A6 AA 0 56 248 0 0 O96 296 248 0 0 O92 80 368 2 0 O45 48 376 0 0 O92 160 368 2 0 O45 128 376 0 0 O92 240 368 2 0 O45 208 376 0 0 O92 320 368 2 0 O45 288 376 0 0 O97 40 368 0 1 A10 r R3C O97 296 368 0 1 A10 r R3C O1C 168 800 0 1 A12 i 59320 OAC 48 280 0 1 A12 i 59322 OAD 128 280 0 1 A12 i 59324 OAE 208 280 0 1 A12 i 59326 O8C 288 280 0 1 A12 i 59328 O1B 168 16 0 1 A12 i 59330 24 0 344 832 R5F "a21o2i.mask" 1048576000 0 1 2 A28 r R60 "A B C X Vdd Gnd" A17 i 74738 1 A18 a A19 0 1 A18 a A19 12720 0 0 2 AE r R61 "/0(MiChip)/0(RasDecode)/2(A21o2i)*1" A1A a A1A OB6 13040 0 0 2 AE r R62 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1" A1A a A1A O18 13504 0 0 2 AE r R63 "A11-1" A1A a A1A O18 13584 0 0 2 AE r R64 "CAS'-1" A1A a A1A O18 13664 0 0 2 AE r R65 "A10-1" A1A a A1A O98 13760 0 0 2 AE r R66 "/0(MiChip)/0(RasDecode)/8(DecoderS)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O18 14064 0 0 2 AE r R67 "PA7-1" A1A a A1A O18 14144 0 0 2 AE r R68 "PA9-1" A1A a A1A O18 14224 0 0 2 AE r R69 "PA8-1" A1A a A1A OAF 14320 0 0 2 AE r R6A "/0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 14544 0 0 2 AE r R6B "PDout0-1" A1A a A1A O18 14624 0 0 2 AE r R6C "RAS3'-1" A1A a A1A O18 14704 0 0 2 AE r R6D "A9-1" A1A a A1A O86 14800 0 0 2 AE r R6E "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/1(Inv)" A1A a A1A OCA AD -32 0 272 856 OCB A1B -32 0 272 856 1 1 OCC AD -8 0 296 856 OCD A2 -8 0 296 856 99 OB5 24 752 0 4 A10 r R23 A4 r RC A12 i 59074 A16 lor 1 RC OB5 24 0 0 4 A10 r R23 A4 r RB A12 i 59072 A16 lor 1 RB O22 208 0 0 3 A10 r R23 A12 i 59070 A16 lor 1 R3A O22 128 0 0 3 A10 r R23 A12 i 59068 A16 lor 1 R43 OA0 48 280 0 1 A12 i 59066 O22 48 0 0 3 A10 r R23 A12 i 59066 A16 lor 1 R44 OB3 296 328 2 1 A10 r R23 O97 216 368 0 1 A10 r R3C O92 240 464 2 0 O3E 208 472 0 0 O97 40 368 0 1 A10 r R3C O1D 24 792 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1E 24 8 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O20 48 792 0 1 A10 r R23 O91 48 368 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O32 68 312 0 1 A10 r R3D OA2 136 368 0 1 A10 r R3C O94 136 352 2 1 A10 r R3C O93 128 80 0 1 A10 r R3B O93 40 80 0 1 A10 r R3B O78 96 312 0 1 A10 r R3C O31 136 64 2 1 A10 r R3B O41 96 288 0 1 A10 r R3B O1D 104 792 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1E 104 8 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O20 128 792 0 1 A10 r R23 O91 128 368 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O32 148 312 0 1 A10 r R3D OA2 128 368 0 1 A10 r R3C O94 216 352 2 1 A10 r R3C O93 208 80 0 1 A10 r R3B O93 120 80 0 1 A10 r R3B O78 176 312 0 1 A10 r R3C O31 216 64 2 1 A10 r R3B O41 176 288 0 1 A10 r R3B O1D 184 792 0 1 A10 r R23 O1E 184 8 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O20 208 792 0 1 A10 r R23 O92 80 704 2 0 O3E 48 712 0 0 O92 80 656 2 0 O3E 48 664 0 0 O92 80 608 2 0 O3E 48 616 0 0 O92 80 560 2 0 O3E 48 568 0 0 O92 80 512 2 0 O3E 48 520 0 0 O92 80 464 2 0 O3E 48 472 0 0 O92 240 656 2 0 O3E 208 664 0 0 O92 240 608 2 0 O3E 208 616 0 0 O92 240 560 2 0 O3E 208 568 0 0 O92 240 512 2 0 O3E 208 520 0 0 O92 240 416 2 0 O3E 208 424 0 0 O92 240 368 2 0 O3E 208 376 0 0 O91 48 80 0 0 O30 48 88 0 0 O91 48 128 0 0 O30 48 136 0 0 O91 48 176 0 0 O30 48 184 0 0 O91 48 224 0 0 O30 48 232 0 0 O91 128 128 0 0 O30 128 136 0 0 O91 128 176 0 0 O30 128 184 0 0 O91 128 224 0 0 O30 128 232 0 0 O91 208 80 0 0 O30 208 88 0 0 O91 208 128 0 0 O30 208 136 0 0 O91 208 224 0 0 O45 208 232 0 0 OAB 136 248 0 0 O90 208 248 0 0 O92 80 368 2 0 O45 48 376 0 0 O92 160 368 2 0 O45 128 376 0 0 O9F 128 280 0 1 A12 i 59068 O8C 224 280 0 1 A12 i 59070 O1B 88 16 0 1 A12 i 59072 O1C 168 800 0 1 A12 i 59074 24 0 264 832 R6F "C2NO02A.mask" 1048576000 0 1 2 A28 r R4F A17 i 74745 1 A18 a A19 0 1 A18 a A19 14960 0 0 2 AE r R70 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/3/2(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A OA4 15200 0 0 2 AE r R71 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1" A1A a A1A O86 15600 0 0 2 AE r R72 "/0(MiChip)/3(AddrMux)/2(Inv)*1" A1A a A1A O86 15760 0 0 2 AE r R73 "/0(MiChip)/3(AddrMux)/0(Inv)*1" A1A a A1A O98 15920 0 0 2 AE r R74 "/0(MiChip)/0(RasDecode)/8(DecoderS)/5(NormalizedNor3)/0(Nor3)" A1A a A1A O86 16240 0 0 2 AE r R75 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1" A1A a A1A OA4 16400 0 0 2 AE r R76 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1" A1A a A1A OC4 16800 0 0 2 AE r R77 "/0(MiChip)/0(RasDecode)/6(A21o2i)*1" A1A a A1A O86 17120 0 0 2 AE r R78 "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)/3(Inv)" A1A a A1A O86 17280 0 0 2 AE r R79 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1" A1A a A1A OCE AD -32 0 352 856 OCF A1B -32 0 352 856 1 1 OD0 AD -8 0 376 856 OD1 A2 -8 0 376 856 143 OC8 376 328 2 1 A10 r R23 O1B 168 40 0 1 A12 i 58542 O9C 24 0 0 4 A10 r R23 A4 r RB A12 i 58542 A16 lor 1 RB O22 288 0 0 3 A10 r R23 A12 i 58538 A16 lor 1 R3A O90 288 248 0 0 O22 208 0 0 3 A10 r R23 A12 i 58536 A16 lor 1 R7A "NEN" O22 128 0 0 3 A10 r R23 A12 i 58534 A16 lor 1 R7B "EN" O22 48 0 0 3 A10 r R23 A12 i 58532 A16 lor 1 R39 OD2 A23 16 384 A6 A1D 0 40 368 0 0 OD3 A23 16 376 A6 A1D 0 312 376 0 0 OD4 A9 16 24 A6 A1E 0 256 288 0 0 OD5 A23 24 380 A6 A1D 0 208 376 0 1 A10 r R3C OD5 216 376 0 1 A10 r R3C OD5 296 376 0 1 A10 r R3C OD6 A1C A6 420 64 A6 A1D 0 136 352 2 1 A10 r R3C OD7 A1C A6 412 64 A6 A1D 0 216 360 2 1 A10 r R3C O80 216 336 0 1 A10 r R3D OD7 296 360 2 1 A10 r R3C OD8 A9 24 120 A6 AA 0 256 280 2 0 O32 228 280 0 1 A10 r R3D O31 216 64 2 1 A10 r R3B O93 208 80 0 1 A10 r R3B O3D 256 336 0 1 A10 r R3C O68 192 768 2 0 O31 296 64 2 1 A10 r R3B O45 48 376 0 0 O92 80 368 2 0 O92 160 368 2 0 O45 288 312 0 0 O30 208 160 0 0 O91 208 152 0 0 O30 208 112 0 0 O91 208 104 0 0 O30 128 136 0 0 O91 128 128 0 0 O30 128 88 0 0 O91 128 80 0 0 OBD 48 200 0 0 O30 48 160 0 0 O91 48 152 0 0 O30 48 112 0 0 O91 48 104 0 0 O30 320 208 1 0 O91 320 200 1 0 O30 320 160 1 0 O91 320 152 1 0 O30 320 112 1 0 O91 320 104 1 0 O91 288 656 0 0 O3E 288 424 0 0 O92 320 416 2 0 O3E 288 472 0 0 O92 320 464 2 0 O3E 288 520 0 0 O92 320 512 2 0 O3E 288 568 0 0 O92 320 560 2 0 O3E 288 616 0 0 O92 320 608 2 0 O3E 208 448 0 0 O92 240 440 2 0 O3E 208 496 0 0 O92 240 488 2 0 O3E 208 544 0 0 O92 240 536 2 0 O3E 208 592 0 0 O92 240 584 2 0 O3E 208 640 0 0 O92 240 632 2 0 O3E 208 688 0 0 O92 240 680 2 0 O3E 128 520 0 0 O92 160 512 2 0 O3E 128 568 0 0 O92 160 560 2 0 O3E 128 616 0 0 O92 160 608 2 0 O3E 128 664 0 0 O92 160 656 2 0 O3E 128 712 0 0 OA3 56 440 0 0 O3E 48 448 0 0 O92 80 440 2 0 O3E 48 496 0 0 O92 80 488 2 0 O3E 48 544 0 0 O92 80 536 2 0 O3E 48 592 0 0 O92 80 584 2 0 O3E 48 640 0 0 O92 80 632 2 0 O3E 48 688 0 0 O92 80 680 2 0 O20 288 792 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O1E 264 8 0 1 A10 r R23 O1D 264 792 0 1 A10 r R23 O32 228 336 0 1 A10 r R3D O20 208 792 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O1E 184 8 0 1 A10 r R23 O1D 184 792 0 1 A10 r R23 O93 120 80 0 1 A10 r R3B O20 128 792 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O1D 104 792 0 1 A10 r R23 O41 96 288 0 1 A10 r R3B O31 136 64 2 1 A10 r R3B O78 96 312 0 1 A10 r R3C O93 40 80 0 1 A10 r R3B O93 128 80 0 1 A10 r R3B O32 68 312 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O91 48 368 0 1 A10 r R3D O20 48 792 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O1E 24 8 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1D 24 792 0 1 A10 r R23 O93 328 80 1 1 A10 r R3B O93 48 80 0 1 A10 r R3B O91 128 368 0 1 A10 r R3D O45 208 384 0 0 O3E 288 376 0 0 O45 288 664 0 0 O45 128 376 0 0 O68 192 56 2 0 O92 160 704 2 0 OD9 A23 24 388 A6 A1D 0 136 368 0 1 A10 r R3C OD9 128 368 0 1 A10 r R3C OD9 48 368 0 1 A10 r R3C O95 232 336 0 1 A10 r R3D ODA A9 24 88 A6 AA 0 136 280 0 0 O92 320 376 2 0 O68 192 344 2 0 O68 192 280 2 0 O8D 56 280 0 1 A12 i 58532 ODB A11 R7B R24 2 0 120 312 0 1 A12 i 58534 ODC A11 R7A R24 2 0 200 320 0 1 A12 i 58536 O8C 296 288 0 1 A12 i 58538 O1C 168 800 0 1 A12 i 58540 O1E 104 8 0 1 A10 r R23 O9C 24 752 0 4 A10 r R23 A4 r RC A12 i 58540 A16 lor 1 RC 24 0 344 832 R7C "C2BD02A.mask" 1048576000 0 1 2 A28 r R7D "EN NEN I X Vdd Gnd" A17 i 74748 1 A18 a A19 0 1 A18 a A19 17440 0 0 2 AE r R7E "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver9" A1A a A1A O86 17760 0 0 2 AE r R7F "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1" A1A a A1A O86 17920 0 0 2 AE r R80 "/0(MiChip)/6(AddrCtl)/10(Decoder)/7(Inv)" A1A a A1A OCE 18080 0 0 2 AE r R81 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver8" A1A a A1A OC4 18400 0 0 2 AE r R82 "/0(MiChip)/0(RasDecode)/7(A21o2i)*1" A1A a A1A OCE 18720 0 0 2 AE r R83 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver10" A1A a A1A O86 19040 0 0 2 AE r R84 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/3//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/3/0(Inv)*1*1" A1A a A1A O86 19200 0 0 2 AE r R85 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv10" A1A a A1A OCE 19360 0 0 2 AE r R86 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver10" A1A a A1A ODD AD -32 0 512 856 ODE A1B -32 0 512 856 1 1 ODF AD -8 0 536 856 OE0 A2 -8 0 536 856 172 OBB 24 0 0 4 A10 r R23 A4 r RB A12 i 59198 A16 lor 1 RB O8C 448 280 0 1 A12 i 59196 OA0 128 280 0 1 A12 i 59194 O9F 48 280 0 1 A12 i 59192 O97 456 368 0 1 A10 r R3C O97 40 368 0 1 A10 r R3C O31 376 64 2 1 A10 r R3B O3E 288 664 0 0 OBD 288 680 0 0 O3E 288 616 0 0 O30 288 232 0 0 O30 288 184 0 0 O30 288 136 0 0 OA2 288 368 0 1 A10 r R3C OE1 A9 32 232 A6 AB 0 208 376 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1F 128 8 0 1 A10 r R23 O20 128 792 0 1 A10 r R23 O91 48 368 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O32 68 312 0 1 A10 r R3D OA2 136 368 0 1 A10 r R3C O94 136 352 2 1 A10 r R3C O93 128 80 0 1 A10 r R3B O93 40 80 0 1 A10 r R3B O78 96 312 0 1 A10 r R3C O41 96 288 0 1 A10 r R3B O1D 104 792 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1E 104 8 0 1 A10 r R23 O20 48 792 0 1 A10 r R23 O91 128 368 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O32 148 312 0 1 A10 r R3D OA2 216 368 0 1 A10 r R3C OA2 128 368 0 1 A10 r R3C O94 216 352 2 1 A10 r R3C O93 208 80 0 1 A10 r R3B O93 120 80 0 1 A10 r R3B O78 176 312 0 1 A10 r R3C O31 216 64 2 1 A10 r R3B O41 176 288 0 1 A10 r R3B O95 224 312 0 1 A10 r R3D O1E 184 8 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O20 208 792 0 1 A10 r R23 O91 208 368 0 1 A10 r R3D OA1 216 312 0 1 A10 r R3D O32 228 312 0 1 A10 r R3D OA2 296 368 0 1 A10 r R3C OA2 208 368 0 1 A10 r R3C O94 296 352 2 1 A10 r R3C O93 288 80 0 1 A10 r R3B O93 200 80 0 1 A10 r R3B O78 256 312 0 1 A10 r R3C O31 296 64 2 1 A10 r R3B O41 256 288 0 1 A10 r R3B O95 304 312 0 1 A10 r R3D O1E 264 8 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O20 288 792 0 1 A10 r R23 OA1 296 312 0 1 A10 r R3D O32 308 312 0 1 A10 r R3D OA2 376 368 0 1 A10 r R3C O94 376 352 2 1 A10 r R3C O93 368 80 0 1 A10 r R3B O93 280 80 0 1 A10 r R3B O78 336 312 0 1 A10 r R3C O41 336 288 0 1 A10 r R3B O1D 344 792 0 1 A10 r R23 O95 384 312 0 1 A10 r R3D O1E 344 8 0 1 A10 r R23 O1F 368 8 0 1 A10 r R23 O20 368 792 0 1 A10 r R23 OA1 376 312 0 1 A10 r R3D O32 388 312 0 1 A10 r R3D OA2 368 368 0 1 A10 r R3C O94 456 352 2 1 A10 r R3C O93 448 80 0 1 A10 r R3B O93 360 80 0 1 A10 r R3B O78 416 312 0 1 A10 r R3C O31 456 64 2 1 A10 r R3B O41 416 288 0 1 A10 r R3B O1D 424 792 0 1 A10 r R23 O1E 424 8 0 1 A10 r R23 O1F 448 8 0 1 A10 r R23 O20 448 792 0 1 A10 r R23 O92 80 656 2 0 O3E 48 664 0 0 O92 80 608 2 0 O3E 48 616 0 0 O92 80 560 2 0 O3E 48 568 0 0 O92 240 704 2 0 O3E 208 712 0 0 O92 240 656 2 0 O3E 208 664 0 0 O91 208 560 0 0 O45 208 568 0 0 O92 320 656 2 0 O92 320 608 2 0 O92 400 608 2 0 O3E 368 616 0 0 O92 400 560 2 0 O3E 368 568 0 0 O92 480 656 2 0 O3E 448 664 0 0 O92 480 608 2 0 O3E 448 616 0 0 OA3 56 560 0 0 OAB 376 560 0 0 OE2 A9 24 240 A6 AA 0 456 344 0 0 OC2 56 512 0 0 OE3 A9 24 192 A6 AA 0 56 344 0 0 OE3 376 344 0 0 OB4 136 464 0 0 O90 136 344 0 0 O90 296 344 0 0 O91 48 80 0 0 O30 48 88 0 0 O91 48 128 0 0 O30 48 136 0 0 O91 48 176 0 0 O30 48 184 0 0 O91 48 224 0 0 O30 48 232 0 0 O91 128 128 0 0 O30 128 136 0 0 O91 128 176 0 0 O30 128 184 0 0 O91 128 224 0 0 O30 128 232 0 0 O91 208 80 0 0 O30 208 88 0 0 O91 208 128 0 0 O30 208 136 0 0 O91 208 176 0 0 O30 208 184 0 0 O91 288 128 0 0 O91 288 176 0 0 O91 288 224 0 0 O91 448 80 0 0 O30 448 88 0 0 O91 448 128 0 0 O30 448 136 0 0 O91 448 176 0 0 O30 448 184 0 0 OE4 A9 104 24 A6 AA 0 136 248 0 0 OB4 296 248 0 0 O96 216 248 0 0 O96 456 248 0 0 O92 80 368 2 0 O45 48 376 0 0 O92 160 368 2 0 O45 128 376 0 0 O92 240 368 2 0 O45 208 376 0 0 O92 480 368 2 0 O45 448 376 0 0 O1D 24 792 0 1 A10 r R23 OBA 536 328 2 1 A10 r R23 O1D 184 792 0 1 A10 r R23 O1D 264 792 0 1 A10 r R23 OBB 24 752 0 4 A10 r R23 A4 r RC A12 i 59190 A16 lor 1 RC O1C 248 800 0 1 A12 i 59190 O22 48 0 0 3 A10 r R23 A12 i 59192 A16 lor 1 R43 O31 136 64 2 1 A10 r R3B O22 128 0 0 3 A10 r R23 A12 i 59194 A16 lor 1 R44 O22 448 0 0 3 A10 r R23 A12 i 59196 A16 lor 1 R3A O1E 24 8 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O1B 248 16 0 1 A12 i 59198 24 0 504 832 R87 "C2XR02A.mask" 1048576000 0 1 2 A28 r R4F A17 i 74750 1 A18 a A19 0 1 A18 a A19 19680 0 0 2 AE r R88 "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 20160 0 0 2 AE r R89 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OAF 20960 0 0 2 AE r R8A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/3/6/1(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O86 21200 0 0 2 AE r R8B "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv8" A1A a A1A O86 21360 0 0 2 AE r R8C "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1" A1A a A1A OCA 21520 0 0 2 AE r R8D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O98 21760 0 0 2 AE r R8E "/0(MiChip)/6(AddrCtl)/10(Decoder)/1(NormalizedNor3)/0(Nor3)" A1A a A1A O86 22080 0 0 2 AE r R8F "/0(MiChip)/6(AddrCtl)/10(Decoder)/5(Inv)" A1A a A1A O98 22240 0 0 2 AE r R90 "/0(MiChip)/6(AddrCtl)/10(Decoder)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O86 22560 0 0 2 AE r R91 "/0(MiChip)/6(AddrCtl)/10(Decoder)/6(Inv)" A1A a A1A O86 22720 0 0 2 AE r R92 "/0(MiChip)/6(AddrCtl)/10(Decoder)/4(Inv)" A1A a A1A O98 22880 0 0 2 AE r R93 "/0(MiChip)/6(AddrCtl)/10(Decoder)/3(NormalizedNor3)/0(Nor3)" A1A a A1A OA4 23200 0 0 2 AE r R94 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1" A1A a A1A O24 23600 0 0 2 AE r R95 "/0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1*1*1*1*1*1*1" A1A a A1A OA4 24400 0 0 2 AE r R96 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1" A1A a A1A O86 24800 0 0 2 AE r R97 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv11" A1A a A1A OB6 24960 0 0 2 AE r R98 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1*1*1*1" A1A a A1A OA4 25440 0 0 2 AE r R99 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1*1*1*1" A1A a A1A O24 25840 0 0 2 AE r R9A "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple11//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple10//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple9//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple8//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple7//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 26640 0 0 2 AE r R9B "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 26800 0 0 2 AE r R9C "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1*1*1*1" A1A a A1A OA4 27600 0 0 2 AE r R9D "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1" A1A a A1A OE5 A2 0 0 4800 832 2 OE6 A2 0 0 4800 80 1 OE7 A9 4800 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 4800 80 R2 1059061760 0 0 0 0 0 0 0 OE8 A2 0 0 4800 80 1 OE7 0 0 0 2 A4 r RC AE r RC 0 0 4800 80 R2 1059061760 0 0 0 0 752 0 0 0 0 4800 832 R9E "MIInnerRight1" 1031153506 0 1 0 28000 0 0 0 0 0 32800 832 R9F "MIInnerIntRow1" 1030556027 0 0 0 0 0 0 1 AE r RA0 "Row1" OE9 A29 Routing 0 0 32800 2656 120 0 0 32800 2656 9 2 AE r RA1 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.nLoad" A4 r RA1 OEA A9 16592 32 A6 AA 0 9064 928 O45 14424 928 O45 9064 928 O45 15384 928 O45 25624 928 OEB A9 32 960 A6 AB 0 25624 0 OEC A9 32 1728 A6 AB 0 14424 928 OEB 15384 0 OEB 9064 0 7 2 AE r RA2 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][3]" A4 r RA2 OED A9 10032 32 A6 AA 0 11064 32 O45 19144 32 O45 11064 32 O45 21064 32 OEE A9 32 64 A6 AB 0 21064 0 OEE 19144 0 OEE 11064 0 5 2 AE r RA3 "/0(MiChip)/3(AddrMux)*1.In1[4]" A4 r RA3 OEF A9 11952 32 A6 AA 0 11464 1568 O45 11464 1568 O45 23384 1568 OF0 A9 32 1600 A6 AB 0 23384 0 OF1 A9 32 1088 A6 AB 0 11464 1568 5 2 AE r RA4 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][4]" A4 r RA4 OF2 A9 512 32 A6 AA 0 14584 2272 O45 14584 2272 O45 15064 2272 OF3 A9 32 2304 A6 AB 0 15064 0 OF4 A9 32 384 A6 AB 0 14584 2272 5 2 AE r RA5 "/0(MiChip)*1.RASX" A4 r RA5 OF5 A9 1552 32 A6 AA 0 12504 992 O45 12504 992 O45 14024 992 OF6 A9 32 1024 A6 AB 0 14024 0 OF7 A9 32 1664 A6 AB 0 12504 992 5 2 AE r RA6 "PA9" A4 r RA6 OF8 A9 5232 32 A6 AA 0 14184 992 O45 14184 992 O45 19384 992 OF7 19384 992 OF6 14184 0 9 2 AE r RA7 "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nAd[0]" A4 r RA7 OF9 A9 4592 32 A6 AA 0 18024 96 O45 21784 96 O45 18024 96 O45 22264 96 O45 22584 96 OFA A9 32 128 A6 AB 0 22584 0 OFA 21784 0 OFA 22264 0 OFA 18024 0 3 2 AE r RA8 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[10]" A4 r RA8 OFB A9 112 32 A6 AB 0 19304 32 OEE 19384 0 OEE 19304 0 7 2 AE r RA9 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][5]" A4 r RA9 OFC A9 4752 32 A6 AA 0 10264 1248 O45 14184 1248 O45 10264 1248 O45 14984 1248 OFD A9 32 1280 A6 AB 0 14984 0 OFE A9 32 1408 A6 AB 0 14184 1248 OFD 10264 0 5 2 AE r RAA "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2).[1]" A4 r RAA OFF A9 2032 32 A6 AA 0 13464 1504 O45 13464 1504 O45 15464 1504 O100 A9 32 1536 A6 AB 0 15464 0 O100 13464 0 5 2 AE r RAB "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21).[2]" A4 r RAB O101 A9 2192 32 A6 AA 0 21384 544 O45 21384 544 O45 23544 544 O102 A9 32 576 A6 AB 0 23544 0 O102 21384 0 9 2 AE r RAC "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nAd[1]" A4 r RAC O103 A9 592 32 A6 AA 0 22184 992 O45 22344 992 O45 22184 992 O45 22664 992 O45 22744 992 OF6 22744 0 OF6 22344 0 OF7 22664 992 OF6 22184 0 5 2 AE r RAD "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2).[2]" A4 r RAD O104 A9 6032 32 A6 AA 0 9544 1120 O45 9544 1120 O45 15544 1120 O105 A9 32 1152 A6 AB 0 15544 0 O105 9544 0 5 2 AE r RAE "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2).[1]" A4 r RAE O106 A9 3552 32 A6 AA 0 9144 224 O45 9144 224 O45 12664 224 O107 A9 32 256 A6 AB 0 12664 0 O107 9144 0 5 2 AE r RAF "/0(MiChip)/2(MemCtlA)*1.S2" A4 r RAF O108 A9 2352 32 A6 AA 0 7304 288 O45 7304 288 O45 9624 288 O109 A9 32 2368 A6 AB 0 9624 288 O10A A9 32 320 A6 AB 0 7304 0 5 2 AE r RB0 "PA10" A4 r RB0 O10B A9 1712 32 A6 AA 0 3304 352 O45 3304 352 O45 4984 352 OF4 4984 0 OF3 3304 352 5 2 AE r RB1 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2).[2]" A4 r RB1 OF5 7704 416 O45 7704 416 O45 9224 416 O10C A9 32 448 A6 AB 0 9224 0 O10C 7704 0 7 2 AE r RB2 "/0(MiChip)/0(RasDecode)/8(DecoderS)*1.nAd[0]" A4 r RB2 O101 11624 2464 O45 12024 2464 O45 11624 2464 O45 13784 2464 O10D A9 32 2496 A6 AB 0 13784 0 O10E A9 32 192 A6 AB 0 12024 2464 O10D 11624 0 3 2 AE r RB3 "/0(MiChip)/0(RasDecode)/8(DecoderS)*1.nnAd[0]" A4 r RB3 OFB 15864 32 OEE 15944 0 O10F A9 32 2624 A6 AB 0 15864 32 5 2 AE r RB4 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21).[2]" A4 r RB4 O110 A9 6992 32 A6 AA 0 17784 288 O45 17784 288 O45 24744 288 O10A 24744 0 O10A 17784 0 5 2 AE r RB5 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[10]" A4 r RB5 O111 A9 1312 32 A6 AA 0 18744 224 O45 18744 224 O45 20024 224 O112 A9 32 2432 A6 AB 0 20024 224 O107 18744 0 5 2 AE r RB6 "PDout0" A4 r RB6 O113 A9 7392 32 A6 AA 0 14584 1312 O45 14584 1312 O45 21944 1312 O114 A9 32 1344 A6 AB 0 21944 1312 O114 14584 0 7 2 AE r RB7 "/0(MiChip)/0(RasDecode)/8(DecoderS)*1.nnAd[2]" A4 r RB7 O115 A9 4512 32 A6 AA 0 11624 2528 O45 11784 2528 O45 11624 2528 O45 16104 2528 O116 A9 32 2560 A6 AB 0 16104 0 O116 11784 0 OFA 11624 2528 5 2 AE r RB8 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2).[6]" A4 r RB8 O117 A9 2112 32 A6 AA 0 13144 1376 O45 13144 1376 O45 15224 1376 OFD 15224 1376 OFE 13144 0 5 2 AE r RB9 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2).[1]" A4 r RB9 O118 A9 352 32 A6 AA 0 25384 608 O45 25384 608 O45 25704 608 O119 A9 32 640 A6 AB 0 25704 0 O119 25384 0 9 2 AE r RBA "/0(MiChip)/0(RasDecode)/8(DecoderS)*1.nAd[1]" A4 r RBA O11A A9 4352 32 A6 AA 0 11704 416 O45 13864 416 O45 11704 416 O45 15944 416 O45 16024 416 O10C 16024 0 O10C 13864 0 O11B A9 32 2240 A6 AB 0 15944 416 O10C 11704 0 5 2 AE r RBB "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2).[6]" A4 r RBB O11C A9 1152 32 A6 AA 0 12344 1952 O45 12344 1952 O45 13464 1952 O11D A9 32 704 A6 AB 0 13464 1952 O11E A9 32 1984 A6 AB 0 12344 0 5 2 AE r RBC "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2).[2]" A4 r RBC O111 25784 352 O45 25784 352 O45 27064 352 OF4 27064 0 OF4 25784 0 7 2 AE r RBD "Dout5" A4 r RBD O11F A9 1392 32 A6 AA 0 18264 1120 O45 18984 1120 O45 18264 1120 O45 19624 1120 O105 19624 0 O105 18984 0 O100 18264 1120 9 2 AE r RBE "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nEnable" A4 r RBE O11C 21944 1120 O45 22424 1120 O45 21944 1120 O45 22744 1120 O45 23064 1120 O105 23064 0 O105 22424 0 O100 22744 1120 O105 21944 0 7 2 AE r RBF "/0(MiChip)/0(RasDecode)/8(DecoderS)*1.nAd[2]" A4 r RBF O120 A9 2672 32 A6 AA 0 11304 1824 O45 11544 1824 O45 11304 1824 O45 13944 1824 O121 A9 32 1856 A6 AB 0 13944 0 O22 11544 1824 O121 11304 0 5 2 AE r RC0 "Din11" A4 r RC0 O10B 4424 32 O45 4424 32 O45 6104 32 OEE 6104 0 O10F 4424 32 7 2 AE r RC1 "A1" A4 r RC1 OED 12104 1696 O45 14824 1696 O45 12104 1696 O45 22104 1696 OEC 22104 0 OEB 14824 1696 OEC 12104 0 5 2 AE r RC2 "Dout6" A4 r RC2 O122 A9 5792 32 A6 AA 0 11944 288 O45 11944 288 O45 17704 288 O10A 17704 0 O109 11944 288 7 2 AE r RC3 "A2" A4 r RC3 O123 A9 17976 24 A6 AA 0 0 100 O45 10744 96 O45 16424 96 O45 17944 96 O124 A9 32 124 A6 AB 0 17944 0 O124 10744 0 O124 16424 0 5 2 AE r RC4 "/0(MiChip)/3(AddrMux)*1.In1[9]" A4 r RC4 OEF 16584 160 O45 16584 160 O45 28504 160 O10D 28504 160 O10E 16584 0 5 2 AE r RC5 "RASX'" A4 r RC5 O125 A9 2752 32 A6 AA 0 10344 1376 O45 10344 1376 O45 13064 1376 OFD 13064 1376 OFE 10344 0 5 2 AE r RC6 "A10" A4 r RC6 O126 A9 5872 32 A6 AA 0 13704 1440 O45 13704 1440 O45 19544 1440 O127 A9 32 1216 A6 AB 0 19544 1440 O128 A9 32 1472 A6 AB 0 13704 0 5 2 AE r RC7 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2).[6]" A4 r RC7 O129 A9 3392 32 A6 AA 0 21704 608 O45 21704 608 O45 25064 608 O119 25064 0 O119 21704 0 5 2 AE r RC8 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[9]" A4 r RC8 O12A A9 1952 32 A6 AA 0 6584 800 O45 6584 800 O45 8504 800 O22 8504 0 O121 6584 800 11 2 AE r RC9 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)*1.decoded[0]" A4 r RC9 O12B A9 11232 32 A6 AA 0 16504 416 O45 22264 416 O45 24504 416 O45 16504 416 O45 23304 416 O45 27704 416 O10C 27704 0 O11B 22264 416 O10C 23304 0 O10C 24504 0 O10C 16504 0 5 2 AE r RCA "Din4" A4 r RCA O12C A9 8512 32 A6 AA 0 17624 672 O45 17624 672 O45 26104 672 O11D 26104 0 O11E 17624 672 5 2 AE r RCB "Din5" A4 r RCB O125 20424 224 O45 20424 224 O45 23144 224 O112 23144 224 O107 20424 0 5 2 AE r RCC "Dout7" A4 r RCC O129 14984 2464 O45 14984 2464 O45 18344 2464 O10D 18344 0 O10E 14984 2464 11 2 AE r RCD "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)*1.decoded[1]" A4 r RCD O12B 16664 1184 O45 22424 1184 O45 24664 1184 O45 16664 1184 O45 23464 1184 O45 27864 1184 O127 27864 0 O128 22424 1184 O127 23464 0 O127 24664 0 O127 16664 0 5 2 AE r RCE "A7" A4 r RCE OFF 23224 96 O45 23224 96 O45 25224 96 O116 25224 96 OFA 23224 0 5 2 AE r RCF "Din6" A4 r RCF O12D A9 5712 32 A6 AA 0 5304 2336 O45 5304 2336 O45 10984 2336 O10A 10984 2336 O109 5304 0 5 2 AE r RD0 "A8" A4 r RD0 O12E A9 752 32 A6 AA 0 24424 736 O45 24424 736 O45 25144 736 O12F A9 32 1920 A6 AB 0 25144 736 O130 A9 32 768 A6 AB 0 24424 0 5 2 AE r RD1 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21).[2]" A4 r RD1 O131 A9 3472 32 A6 AA 0 17304 1504 O45 17304 1504 O45 20744 1504 O105 20744 1504 O100 17304 0 5 2 AE r RD2 "A11" A4 r RD2 O132 A9 5952 32 A6 AA 0 13544 2080 O45 13544 2080 O45 19464 2080 O102 19464 2080 O133 A9 32 2112 A6 AB 0 13544 0 5 2 AE r RD3 "A9" A4 r RD3 O134 A9 3152 32 A6 AA 0 14744 544 O45 14744 544 O45 17864 544 O133 17864 544 O102 14744 0 3 2 AE r RD4 "/0(MiChip)/0(RasDecode)*1.RasN[1]" A4 r RD4 O135 A9 32 24 A6 AB 0 18424 36 O136 A9 32 60 A6 AB 0 18424 0 O137 A9 32 2620 A6 AB 0 18424 36 7 2 AE r RD5 "/0(MiChip)*1.LdAddrHi[0]" A4 r RD5 O138 A9 16192 32 A6 AA 0 5864 736 O45 21064 736 O45 5864 736 O45 22024 736 O130 22024 0 O12F 21064 736 O130 5864 0 5 2 AE r RD6 "/0(MiChip)/0(RasDecode)*1.RasN[2]" A4 r RD6 O139 A9 672 32 A6 AA 0 16184 672 O45 16184 672 O45 16824 672 O11D 16824 0 O11D 16184 0 5 2 AE r RD7 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[6]" A4 r RD7 OF2 21144 32 O45 21144 32 O45 21624 32 OEE 21624 0 OEE 21144 0 9 2 AE r RD8 "/0(MiChip)*1.RasRF" A4 r RD8 O12D 12904 2016 O45 15464 2016 O45 12904 2016 O45 16984 2016 O45 18584 2016 O13A A9 32 2048 A6 AB 0 18584 0 O119 15464 2016 O13A 16984 0 O13A 12904 0 5 2 AE r RD9 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[7]" A4 r RD9 O120 8504 1184 O45 8504 1184 O45 11144 1184 O127 11144 0 O128 8504 1184 5 2 AE r RDA "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[6][1]" A4 r RDA O13B A9 2432 32 A6 AA 0 8584 2272 O45 8584 2272 O45 10984 2272 OF3 10984 0 OF4 8584 2272 11 2 AE r RDB "/0(MiChip)*1.LdAddrHi[1]" A4 r RDB O13C A9 14272 32 A6 AA 0 4584 480 O45 8824 480 O45 18184 480 O45 4584 480 O45 17544 480 O45 18824 480 O13D A9 32 512 A6 AB 0 18824 0 O13D 8824 0 O13D 17544 0 O13D 18184 0 O13E A9 32 2176 A6 AB 0 4584 480 5 2 AE r RDC "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21).[2]" A4 r RDC O111 26664 288 O45 26664 288 O45 27944 288 O10A 27944 0 O10A 26664 0 5 2 AE r RDD "CAS'" A4 r RDD O13F A9 6672 32 A6 AA 0 13624 1952 O45 13624 1952 O45 20264 1952 O11D 20264 1952 O11E 13624 0 5 2 AE r RDE "/0(MiChip)/0(RasDecode)*1.RasN[6]" A4 r RDE O140 A9 912 32 A6 AA 0 11864 2016 O45 11864 2016 O45 12744 2016 O13A 12744 0 O13A 11864 0 9 2 AE r RDF "/0(MiChip)/6(AddrCtl)/14(Decoder)*1.nAd[0]" A4 r RDF O141 A9 2272 32 A6 AA 0 8584 2208 O45 10104 2208 O45 8584 2208 O45 10424 2208 O45 10824 2208 O11B 10824 0 O10C 10104 2208 O11B 10424 0 O11B 8584 0 5 2 AE r RE0 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncount" A4 r RE0 O142 A9 6512 32 A6 AA 0 15064 2336 O45 15064 2336 O45 21544 2336 O109 21544 0 O10A 15064 2336 5 2 AE r RE1 "/0(MiChip)/2(MemCtlA)/17(fsm2i)*1.[4]" A4 r RE1 O143 A9 1232 32 A6 AA 0 13224 800 O45 13224 800 O45 14424 800 O22 14424 0 O121 13224 800 9 2 AE r RE2 "/0(MiChip)/6(AddrCtl)/14(Decoder)*1.nAd[1]" A4 r RE2 O144 A9 3952 32 A6 AA 0 8264 1504 O45 10344 1504 O45 8264 1504 O45 10504 1504 O45 12184 1504 O100 12184 0 O105 10344 1504 O100 10504 0 O100 8264 0 5 2 AE r RE3 "PDWPout" A4 r RE3 O10B 3224 224 O45 3224 224 O45 4904 224 O107 4904 0 O112 3224 224 5 2 AE r RE4 "/0(MiChip)/4(RefreshCtr)*1.[1][10]" A4 r RE4 O145 A9 4112 32 A6 AA 0 8184 992 O45 8184 992 O45 12264 992 OF6 12264 0 OF6 8184 0 5 2 AE r RE5 "/0(MiChip)/2(MemCtlA)*1.C3" A4 r RE5 O146 A9 4192 32 A6 AA 0 20104 1440 O45 20104 1440 O45 24264 1440 O128 24264 0 O127 20104 1440 5 2 AE r RE6 "PDin0" A4 r RE6 O115 11944 160 O45 11944 160 O45 16424 160 O10D 16424 160 O10E 11944 0 5 2 AE r RE7 "/0(MiChip)/4(RefreshCtr)*1.[1][11]" A4 r RE7 O147 A9 3072 32 A6 AA 0 10024 800 O45 10024 800 O45 13064 800 O22 13064 0 O22 10024 0 5 2 AE r RE8 "/0(MiChip)/4(RefreshCtr)*1.[8][10]" A4 r RE8 O148 A9 4672 32 A6 AA 0 20824 352 O45 20824 352 O45 25464 352 OF4 25464 0 OF4 20824 0 5 2 AE r RE9 "/0(MiChip)/4(RefreshCtr)*1.[1][6]" A4 r RE9 O149 A9 2592 32 A6 AA 0 24984 224 O45 24984 224 O45 27544 224 O107 27544 0 O107 24984 0 5 2 AE r REA "RAS0'" A4 r REA O14A A9 4032 32 A6 AA 0 11544 1184 O45 11544 1184 O45 15544 1184 O128 15544 1184 O127 11544 0 7 2 AE r REB "/0(MiChip)/6(AddrCtl)/14(Decoder)*1.nnAd[1]" A4 r REB O14B A9 992 32 A6 AA 0 8344 1120 O45 8664 1120 O45 8344 1120 O45 9304 1120 O100 9304 1120 O105 8664 0 O105 8344 0 5 2 AE r REC "RAS3'" A4 r REC OF9 14664 2208 O45 14664 2208 O45 19224 2208 O10C 19224 2208 O11B 14664 0 5 2 AE r RED "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[8][2]" A4 r RED O14C A9 4272 32 A6 AA 0 10904 1760 O45 10904 1760 O45 15144 1760 O14D A9 32 1792 A6 AB 0 15144 0 O14D 10904 0 5 2 AE r REE "LPRESET" A4 r REE O14E A9 8832 32 A6 AA 0 11384 1888 O45 11384 1888 O45 20184 1888 O130 20184 1888 O12F 11384 0 5 2 AE r REF "WENT'" A4 r REF O144 4744 1248 O45 4744 1248 O45 8664 1248 OFE 8664 1248 OFD 4744 0 7 2 AE r RC A4 r RC O14F A9 7792 32 A6 AA 0 8024 672 O45 15624 672 O45 8024 672 O45 15784 672 O11D 15784 0 O11D 15624 0 O11E 8024 672 7 2 AE r RF0 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv).nEnable" A4 r RF0 O150 A9 10992 32 A6 AA 0 14904 800 O45 19544 800 O45 14904 800 O45 25864 800 O121 25864 800 O22 19544 0 O22 14904 0 5 2 AE r RF1 "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)*1.[5]" A4 r RF1 O147 17064 1376 O45 17064 1376 O45 20104 1376 OFE 20104 0 OFD 17064 1376 7 2 AE r RF2 "/0(MiChip)*1.LdRefCtr[0]" A4 r RF2 O151 A9 15152 32 A6 AA 0 5064 352 O45 5784 352 O45 5064 352 O45 20184 352 OF4 20184 0 OF3 5784 352 OF4 5064 0 5 2 AE r RF3 "/0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)*1.[4]" A4 r RF3 O152 A9 7632 32 A6 AA 0 6904 544 O45 6904 544 O45 14504 544 O102 14504 0 O102 6904 0 5 2 AE r RF4 "/0(MiChip)/4(RefreshCtr)*1.Output[6]" A4 r RF4 O129 24104 544 O45 24104 544 O45 27464 544 O102 27464 0 O133 24104 544 5 2 AE r RF5 "/0(MiChip)/4(RefreshCtr)*1.[8][14]" A4 r RF5 O14C 8904 1440 O45 8904 1440 O45 13144 1440 O127 13144 1440 O128 8904 0 5 2 AE r RF6 "WENW'" A4 r RF6 OFC 4824 1312 O45 4824 1312 O45 9544 1312 O114 9544 1312 O114 4824 0 5 2 AE r RF7 "/0(MiChip)/4(RefreshCtr)*1.[8][9]" A4 r RF7 O11F 4344 288 O45 4344 288 O45 5704 288 O10A 5704 0 O109 4344 288 7 2 AE r RF8 "/0(MiChip)*1.LdRefCtr[1]" A4 r RF8 O153 A9 8992 32 A6 AA 0 10504 1632 O45 14824 1632 O45 10504 1632 O45 19464 1632 OF7 19464 0 OF7 14824 0 OF6 10504 1632 5 2 AE r RF9 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21).[2]" A4 r RF9 OF2 16264 1376 O45 16264 1376 O45 16744 1376 OFE 16744 0 OFE 16264 0 5 2 AE r RFA "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[11]" A4 r RFA O143 23704 224 O45 23704 224 O45 24904 224 O107 24904 0 O112 23704 224 5 2 AE r RFB "/0(MiChip)/4(RefreshCtr)*1.[8][15]" A4 r RFB O154 A9 9792 32 A6 AA 0 15224 1248 O45 15224 1248 O45 24984 1248 OFE 24984 1248 OFD 15224 0 5 2 AE r RFC "/0(MiChip)/4(RefreshCtr)*1.Output[7]" A4 r RFC O155 A9 7232 32 A6 AA 0 13784 2592 O45 13784 2592 O45 20984 2592 O10F 20984 0 OEE 13784 2592 5 2 AE r RFD "/0(MiChip)/4(RefreshCtr)*1.[3][10]" A4 r RFD O10B 19224 480 O45 19224 480 O45 20904 480 O13D 20904 0 O13D 19224 0 9 2 AE r RFE "/0(MiChip)*1.[16]" A4 r RFE O12D 12824 224 O45 18504 224 O45 12824 224 O45 16904 224 O112 18504 224 O107 18504 0 O107 16904 0 O112 18504 224 O107 12824 0 3 2 AE r RFF "/0(MiChip)/3(AddrMux)*1.In0[0]" A4 r RFF OFB 27544 288 O10A 27624 0 O109 27544 288 7 2 AE r R100 "/0(MiChip)*1.RASn[2]" A4 r R100 O156 A9 7072 32 A6 AA 0 4184 160 O45 6584 160 O45 4184 160 O45 11224 160 O10E 11224 0 O10E 6584 0 O10D 4184 160 5 2 AE r R101 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[9][1]" A4 r R101 O12E 18344 2528 O45 18344 2528 O45 19064 2528 O116 19064 0 OFA 18344 2528 7 2 AE r R102 "/0(MiChip)/6(AddrCtl)/14(Decoder)*1.nEnable" A4 r R102 O157 A9 1872 32 A6 AA 0 8744 2400 O45 10424 2400 O45 8744 2400 O45 10584 2400 O112 10584 0 O107 10424 2400 O112 8744 0 13 2 AE r R103 "/0(MiChip)*1.[27][2]" A4 r R103 O158 A9 20192 32 A6 AA 0 6664 864 O45 7464 864 O45 14904 864 O45 6664 864 O45 23624 864 O45 9304 864 O45 26824 864 O159 A9 32 896 A6 AB 0 26824 0 O159 7464 0 O159 9304 0 O14D 14904 864 O159 23624 0 O159 6664 0 5 2 AE r R104 "PA4" A4 r R104 OF8 12024 2400 O45 12024 2400 O45 17224 2400 O107 17224 2400 O112 12024 0 5 2 AE r R105 "/0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)*1.[7]" A4 r R105 O15A A9 2912 32 A6 AA 0 11464 1312 O45 11464 1312 O45 14344 1312 O114 14344 0 O114 11464 0 5 2 AE r R106 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[14]" A4 r R106 O13B 17304 1760 O45 17304 1760 O45 19704 1760 O14D 19704 0 O159 17304 1760 5 2 AE r R107 "/0(MiChip)/3(AddrMux)*1.In1[0]" A4 r R107 O15B A9 2512 32 A6 AA 0 25304 96 O45 25304 96 O45 27784 96 OFA 27784 0 O116 25304 96 5 2 AE r R108 "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)*1.nAd[0]" A4 r R108 O15C A9 272 32 A6 AA 0 16984 2272 O45 16984 2272 O45 17224 2272 OF3 17224 0 OF4 16984 2272 5 2 AE r R109 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[8]" A4 r R109 O15D A9 3232 32 A6 AA 0 18104 544 O45 18104 544 O45 21304 544 O102 21304 0 O102 18104 0 9 2 AE r R10A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.load" A4 r R10A OEA 8984 1056 O45 14504 1056 O45 8984 1056 O45 15304 1056 O45 25544 1056 OF1 25544 0 OF0 14504 1056 OF1 15304 0 OF1 8984 0 3 2 AE r R10B "/0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)*1.[4]" A4 r R10B O15E A9 192 32 A6 AB 0 23864 32 O10F 24024 32 OEE 23864 0 5 2 AE r R10C "/0(MiChip)/4(RefreshCtr)*1.Output[10]" A4 r R10C O117 8104 32 O45 8104 32 O45 10184 32 OEE 10184 0 OEE 8104 0 7 2 AE r R10D "/0(MiChip)*1.LdStatus[0]" A4 r R10D O12D 23144 32 O45 25864 32 O45 23144 32 O45 28824 32 O10F 28824 32 OEE 25864 0 OEE 23144 0 5 2 AE r R10E "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[9]" A4 r R10E O10B 15784 1120 O45 15784 1120 O45 17464 1120 O105 17464 0 O100 15784 1120 5 2 AE r R10F "/0(MiChip)/4(RefreshCtr)*1.[3][9]" A4 r R10F O120 5784 224 O45 5784 224 O45 8424 224 O107 8424 0 O107 5784 0 7 2 AE r R110 "/0(MiChip)/4(RefreshCtr)*1.Output[11]" A4 r R110 O15F A9 3632 32 A6 AA 0 9944 2144 O45 10104 2144 O45 9944 2144 O45 13544 2144 O13D 13544 2144 O13E 10104 0 O13E 9944 0 5 2 AE r R111 "PA7" A4 r R111 O160 A9 8032 32 A6 AA 0 14104 1824 O45 14104 1824 O45 22104 1824 O22 22104 1824 O121 14104 0 9 2 AE r R112 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv).nEnable" A4 r R112 O13C 4664 608 O45 17624 608 O45 4664 608 O45 18264 608 O45 18904 608 O119 18904 0 O119 17624 0 O119 18264 0 O13A 4664 608 5 2 AE r R113 "/0(MiChip)/7(StatusReg)*1.[14][8]" A4 r R113 O161 A9 1792 32 A6 AA 0 24824 288 O45 24824 288 O45 26584 288 O10A 26584 0 O10A 24824 0 7 2 AE r R114 "/0(MiChip)/3(AddrMux)*1.In1[3]" A4 r R114 O162 A9 5552 32 A6 AA 0 21224 480 O45 24584 480 O45 21224 480 O45 26744 480 O13E 26744 480 O13D 24584 0 O13D 21224 0 7 2 AE r R115 "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nnAd[0]" A4 r R115 O118 22584 736 O45 22664 736 O45 22584 736 O45 22904 736 O130 22904 0 O130 22664 0 O12F 22584 736 5 2 AE r R116 "PA8" A4 r R116 O148 14264 2144 O45 14264 2144 O45 18904 2144 O13D 18904 2144 O13E 14264 0 7 2 AE r R117 "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nnAd[1]" A4 r R117 O11C 21864 32 O45 22824 32 O45 21864 32 O45 22984 32 OEE 22984 0 OEE 22824 0 OEE 21864 0 0 0 832 0 1 AE r R118 "MIInnerChan2" O163 A2 0 0 32800 864 105 O164 A2 0 0 3200 832 2 O165 A2 0 0 3200 80 1 O166 A9 3200 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 3200 80 R2 1059061760 0 0 0 0 0 0 0 O167 A2 0 0 3200 80 1 O166 0 0 0 2 A4 r RC AE r RC 0 0 3200 80 R2 1059061760 0 0 0 0 752 0 0 0 0 3200 832 R119 "MIInnerLeft2" 1031153506 0 1 0 0 0 0 0 O18 3184 0 0 2 AE r R11A "PDWPout-2" A1A a A1A O18 3264 0 0 2 AE r R11B "PA10-2" A1A a A1A O24 3360 0 0 2 AE r R11C "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 4160 0 0 2 AE r R11D "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv4" A1A a A1A O18 4304 0 0 2 AE r R11E "/0(MiChip)/4(RefreshCtr)*1.[8][9]-2" A1A a A1A O18 4384 0 0 2 AE r R11F "Din11-2" A1A a A1A OCE 4480 0 0 2 AE r R120 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver4" A1A a A1A O24 4800 0 0 2 AE r R121 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1" A1A a A1A O86 5600 0 0 2 AE r R122 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv15" A1A a A1A O24 5760 0 0 2 AE r R123 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 6544 0 0 2 AE r R124 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[9]-2" A1A a A1A ODD 6640 0 0 2 AE r R125 "/0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 7120 0 0 2 AE r R126 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv3" A1A a A1A OCE 7280 0 0 2 AE r R127 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver3" A1A a A1A OCE 7600 0 0 2 AE r R128 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver15" A1A a A1A O168 AD -32 0 352 856 O169 A1B -32 0 352 856 1 1 O16A AD -8 0 376 856 O16B A2 -8 0 376 856 130 O9C 24 0 0 4 A10 r R23 A4 r RB A12 i 59038 A16 lor 1 RB O9C 24 752 0 4 A10 r R23 A4 r RC A12 i 59036 A16 lor 1 RC OC8 376 328 2 1 A10 r R23 O22 288 0 0 3 A10 r R23 A12 i 59034 A16 lor 1 R3A O22 128 0 0 3 A10 r R23 A12 i 59032 A16 lor 1 R44 O22 48 0 0 3 A10 r R23 A12 i 59030 A16 lor 1 R43 O1D 24 792 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1E 24 8 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O20 128 792 0 1 A10 r R23 O91 48 368 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O32 68 312 0 1 A10 r R3D OA2 136 368 0 1 A10 r R3C O94 136 352 2 1 A10 r R3C O93 128 80 0 1 A10 r R3B O93 40 80 0 1 A10 r R3B O78 96 312 0 1 A10 r R3C O31 136 64 2 1 A10 r R3B O41 96 288 0 1 A10 r R3B O1D 104 792 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1E 104 8 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O20 48 792 0 1 A10 r R23 O91 128 368 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O32 148 312 0 1 A10 r R3D OA2 216 368 0 1 A10 r R3C OA2 128 368 0 1 A10 r R3C O94 216 352 2 1 A10 r R3C O93 208 80 0 1 A10 r R3B O93 120 80 0 1 A10 r R3B O78 176 312 0 1 A10 r R3C O31 216 64 2 1 A10 r R3B O41 176 288 0 1 A10 r R3B O1D 184 792 0 1 A10 r R23 O95 224 312 0 1 A10 r R3D O1E 184 8 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O20 208 792 0 1 A10 r R23 OA1 216 312 0 1 A10 r R3D O32 228 312 0 1 A10 r R3D OA2 208 368 0 1 A10 r R3C O94 296 352 2 1 A10 r R3C O93 288 80 0 1 A10 r R3B O93 200 80 0 1 A10 r R3B O78 256 312 0 1 A10 r R3C O31 296 64 2 1 A10 r R3B O41 256 288 0 1 A10 r R3B O1D 264 792 0 1 A10 r R23 O1E 264 8 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O20 288 792 0 1 A10 r R23 O92 80 704 2 0 O3E 48 712 0 0 O92 80 656 2 0 O3E 48 664 0 0 O92 80 608 2 0 O3E 48 616 0 0 O92 80 560 2 0 O3E 48 568 0 0 O92 80 512 2 0 O3E 48 520 0 0 O92 80 464 2 0 O3E 48 472 0 0 O92 160 656 2 0 O3E 128 664 0 0 O92 160 608 2 0 O3E 128 616 0 0 O92 160 560 2 0 O3E 128 568 0 0 O92 160 512 2 0 O3E 128 520 0 0 O92 160 464 2 0 O3E 128 472 0 0 O92 240 704 2 0 O3E 208 712 0 0 O92 240 656 2 0 O3E 208 664 0 0 O92 240 608 2 0 O3E 208 616 0 0 O92 240 560 2 0 O3E 208 568 0 0 O92 320 656 2 0 O3E 288 664 0 0 O92 320 608 2 0 O3E 288 616 0 0 O92 320 560 2 0 O3E 288 568 0 0 O92 320 512 2 0 O3E 288 520 0 0 O92 320 464 2 0 O3E 288 472 0 0 OE4 136 464 0 0 O90 216 344 0 0 O91 48 128 0 0 O30 48 136 0 0 O91 48 176 0 0 O30 48 184 0 0 O91 48 224 0 0 O30 48 232 0 0 O91 208 80 0 0 O30 208 88 0 0 O91 208 128 0 0 O30 208 136 0 0 O91 288 128 0 0 O30 288 136 0 0 O91 288 176 0 0 O30 288 184 0 0 O91 288 224 0 0 O30 288 232 0 0 OB4 56 248 0 0 O96 216 248 0 0 O96 296 248 0 0 O92 80 368 2 0 O45 48 376 0 0 O92 160 368 2 0 O45 128 376 0 0 O92 320 368 2 0 O45 288 376 0 0 O97 40 368 0 1 A10 r R3C O16C A9 24 176 A6 AA 0 296 312 0 0 O97 296 368 0 1 A10 r R3C O9F 48 280 0 1 A12 i 59030 OA0 128 280 0 1 A12 i 59032 O8C 288 280 0 1 A12 i 59034 O1C 168 800 0 1 A12 i 59036 O1B 160 16 0 1 A12 i 59038 24 0 344 832 R129 "C2AN02A.mask" 1048576000 0 1 2 A28 r R4F A17 i 74744 1 A18 a A19 0 1 A18 a A19 7920 0 0 2 AE r R12A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/13(counterUpCtrl2)/4(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O16D AD -32 0 272 856 O16E A1B -32 0 272 856 1 1 O16F AD -8 0 296 856 O170 A2 -8 0 296 856 99 OB3 296 328 2 1 A10 r R23 O22 208 0 0 3 A10 r R23 A12 i 58521 A16 lor 1 R3A O8C 216 288 0 1 A12 i 58521 O8D 56 288 0 1 A12 i 58519 O1C 120 776 0 1 A12 i 58517 O92 80 368 2 0 O45 208 376 0 0 O80 136 312 0 1 A10 r R3D OA2 128 368 0 1 A10 r R3C O1D 24 792 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O20 48 792 0 1 A10 r R23 OA1 56 312 0 1 A10 r R3D O32 68 312 0 1 A10 r R3D OA2 136 368 0 1 A10 r R3C O94 136 352 2 1 A10 r R3C O93 128 80 0 1 A10 r R3B O93 40 80 0 1 A10 r R3B O78 96 312 0 1 A10 r R3C O41 96 288 0 1 A10 r R3B O1D 104 792 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1E 104 8 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O20 128 792 0 1 A10 r R23 O32 148 312 0 1 A10 r R3D O94 216 352 2 1 A10 r R3C O93 208 80 0 1 A10 r R3B O93 120 80 0 1 A10 r R3B O78 176 312 0 1 A10 r R3C O31 216 64 2 1 A10 r R3B O41 176 288 0 1 A10 r R3B O1D 184 792 0 1 A10 r R23 O1E 184 8 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O20 208 792 0 1 A10 r R23 O92 80 704 2 0 O3E 48 712 0 0 O92 80 656 2 0 O3E 48 664 0 0 O92 80 608 2 0 O3E 48 616 0 0 O92 80 560 2 0 O3E 48 568 0 0 O92 80 512 2 0 O3E 48 520 0 0 O92 80 464 2 0 O3E 48 472 0 0 O92 160 656 2 0 O3E 128 664 0 0 O92 160 608 2 0 O3E 128 616 0 0 O92 160 560 2 0 O3E 128 568 0 0 O92 160 512 2 0 O3E 128 520 0 0 O92 160 464 2 0 O3E 128 472 0 0 O92 240 704 2 0 O3E 208 712 0 0 O92 240 656 2 0 O3E 208 664 0 0 O92 240 608 2 0 O3E 208 616 0 0 O92 240 560 2 0 O3E 208 568 0 0 OAB 136 464 0 0 OAB 56 368 0 0 O90 216 344 0 0 O91 48 80 0 0 O30 48 88 0 0 O91 48 128 0 0 O30 48 136 0 0 O91 48 176 0 0 O30 48 184 0 0 O91 48 224 0 0 O30 48 232 0 0 O91 128 128 0 0 O30 128 136 0 0 O91 128 176 0 0 O30 128 184 0 0 O91 128 224 0 0 O30 128 232 0 0 O91 208 80 0 0 O30 208 88 0 0 O91 208 128 0 0 O30 208 136 0 0 OAB 136 248 0 0 O90 208 248 0 0 O45 48 376 0 0 O97 216 368 0 1 A10 r R3C O97 40 368 0 1 A10 r R3C OB5 24 752 0 4 A10 r R23 A4 r RC A12 i 58517 A16 lor 1 RC O31 136 64 2 1 A10 r R3B O22 48 0 0 3 A10 r R23 A12 i 58519 A16 lor 1 R39 O1E 24 8 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O1B 120 48 0 1 A12 i 58523 OB5 24 0 0 4 A10 r R23 A4 r RB A12 i 58523 A16 lor 1 RB 24 0 264 832 R12B "C2IV00B.mask" 1048576000 0 1 2 A28 r R3F A17 i 74741 1 A18 a A19 0 1 A18 a A19 8240 0 0 2 AE r R12C "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/13(counterUpCtrl2)/2(B)/Buffer0" A1A a A1A O18 8464 0 0 2 AE r R12D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[7]-2" A1A a A1A O18 8544 0 0 2 AE r R12E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[6][1]-2" A1A a A1A O18 8624 0 0 2 AE r R12F "WENT'-2" A1A a A1A ODD 8720 0 0 2 AE r R130 "/0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O98 9200 0 0 2 AE r R131 "/0(MiChip)/6(AddrCtl)/14(Decoder)/3(NormalizedNor3)/0(Nor3)" A1A a A1A O18 9504 0 0 2 AE r R132 "WENW'-2" A1A a A1A O86 9600 0 0 2 AE r R133 "/0(MiChip)/2(MemCtlA)/19(fsmc1)/0(Decoder)/4(Inv)" A1A a A1A O86 9760 0 0 2 AE r R134 "/0(MiChip)/2(MemCtlA)/19(fsmc1)/0(Decoder)/2(Inv)" A1A a A1A O86 9920 0 0 2 AE r R135 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/0(Inv)*1*1*1*1*1*1" A1A a A1A O86 10080 0 0 2 AE r R136 "/0(MiChip)/6(AddrCtl)/14(Decoder)/6(Inv)" A1A a A1A O98 10240 0 0 2 AE r R137 "/0(MiChip)/6(AddrCtl)/14(Decoder)/2(NormalizedNor3)/0(Nor3)" A1A a A1A O86 10560 0 0 2 AE r R138 "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)/2(Inv)" A1A a A1A O24 10720 0 0 2 AE r R139 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 11520 0 0 2 AE r R13A "/0(MiChip)/0(RasDecode)/8(DecoderS)/8(Inv)" A1A a A1A OCA 11680 0 0 2 AE r R13B "/0(MiChip)/2(MemCtlA)/23(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 11904 0 0 2 AE r R13C "Dout6-2" A1A a A1A O18 11984 0 0 2 AE r R13D "/0(MiChip)/0(RasDecode)/8(DecoderS)*1.nAd[0]-2" A1A a A1A OCA 12080 0 0 2 AE r R13E "/0(MiChip)/2(MemCtlA)/19(fsmc1)/0(Decoder)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O86 12320 0 0 2 AE r R13F "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/1(Inv)*1" A1A a A1A OC4 12480 0 0 2 AE r R140 "/0(MiChip)/0(RasDecode)/1(A21o2i)*1" A1A a A1A O171 AD -32 0 352 856 O172 A1B -32 0 352 856 1 1 O173 AD -8 0 376 856 O174 A2 -8 0 376 856 130 O9C 24 0 0 4 A10 r R23 A4 r RB A12 i 59142 A16 lor 1 RB O22 288 0 0 3 A10 r R23 A12 i 59140 A16 lor 1 R3A O31 296 64 2 1 A10 r R3B O22 128 0 0 3 A10 r R23 A12 i 59138 A16 lor 1 R44 O22 48 0 0 3 A10 r R23 A12 i 59136 A16 lor 1 R43 O9C 24 752 0 4 A10 r R23 A4 r RC A12 i 59134 A16 lor 1 RC OC8 376 328 2 1 A10 r R23 O97 40 368 0 1 A10 r R3C O97 296 368 0 1 A10 r R3C O45 288 376 0 0 O92 320 368 2 0 O45 128 376 0 0 O92 160 368 2 0 O45 48 376 0 0 O92 80 368 2 0 O96 296 248 0 0 O96 216 248 0 0 OE4 136 248 0 0 O30 288 232 0 0 O91 288 224 0 0 O30 288 184 0 0 O91 288 176 0 0 O30 288 136 0 0 O91 288 128 0 0 O30 208 184 0 0 O91 208 176 0 0 O30 208 136 0 0 O91 208 128 0 0 O30 208 88 0 0 O91 208 80 0 0 O30 128 232 0 0 O91 128 224 0 0 O30 128 184 0 0 O91 128 176 0 0 O30 128 136 0 0 O91 128 128 0 0 O30 48 232 0 0 O91 48 224 0 0 O30 48 184 0 0 O91 48 176 0 0 O30 48 136 0 0 O91 48 128 0 0 O30 48 88 0 0 O91 48 80 0 0 O16C 296 312 0 0 OB4 56 464 0 0 O3E 288 472 0 0 O92 320 464 2 0 O3E 288 520 0 0 O92 320 512 2 0 O3E 288 568 0 0 O92 320 560 2 0 O3E 288 616 0 0 O92 320 608 2 0 O3E 288 664 0 0 O92 320 656 2 0 O3E 208 520 0 0 O92 240 512 2 0 O3E 208 568 0 0 O92 240 560 2 0 O3E 208 616 0 0 O92 240 608 2 0 O3E 208 664 0 0 O92 240 656 2 0 O3E 208 712 0 0 O92 240 704 2 0 O3E 48 472 0 0 O92 80 464 2 0 O3E 48 520 0 0 O92 80 512 2 0 O3E 48 568 0 0 O92 80 560 2 0 O3E 48 616 0 0 O92 80 608 2 0 O3E 48 664 0 0 O92 80 656 2 0 O20 288 792 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O1E 264 8 0 1 A10 r R23 O1D 264 792 0 1 A10 r R23 O41 256 288 0 1 A10 r R3B O78 256 312 0 1 A10 r R3C O93 200 80 0 1 A10 r R3B O93 288 80 0 1 A10 r R3B O94 296 352 2 1 A10 r R3C O32 228 312 0 1 A10 r R3D OA1 216 312 0 1 A10 r R3D O20 208 792 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O1E 184 8 0 1 A10 r R23 O95 224 312 0 1 A10 r R3D O1D 184 792 0 1 A10 r R23 O41 176 288 0 1 A10 r R3B O31 216 64 2 1 A10 r R3B O78 176 312 0 1 A10 r R3C O93 120 80 0 1 A10 r R3B O93 208 80 0 1 A10 r R3B O94 216 352 2 1 A10 r R3C OA2 128 368 0 1 A10 r R3C OA2 216 368 0 1 A10 r R3C O32 148 312 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O91 128 368 0 1 A10 r R3D O20 48 792 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O1E 104 8 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1D 104 792 0 1 A10 r R23 O41 96 288 0 1 A10 r R3B O31 136 64 2 1 A10 r R3B O78 96 312 0 1 A10 r R3C O93 40 80 0 1 A10 r R3B O93 128 80 0 1 A10 r R3B O94 136 352 2 1 A10 r R3C OA2 136 368 0 1 A10 r R3C O32 68 312 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O91 48 368 0 1 A10 r R3D O20 128 792 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O1E 24 8 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1D 24 792 0 1 A10 r R23 O90 216 344 0 0 OA2 208 368 0 1 A10 r R3C O1C 168 800 0 1 A12 i 59134 O9F 48 280 0 1 A12 i 59136 OA0 128 280 0 1 A12 i 59138 O8C 288 280 0 1 A12 i 59140 O1B 160 16 0 1 A12 i 59142 24 0 344 832 R141 "C2OR02A.mask" 1048576000 0 1 2 A28 r R4F A17 i 74737 1 A18 a A19 0 1 A18 a A19 12800 0 0 2 AE r R142 "/0(MiChip)/0(RasDecode)/0(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O18 13104 0 0 2 AE r R143 "/0(MiChip)/4(RefreshCtr)*1.[8][14]-2" A1A a A1A O18 13184 0 0 2 AE r R144 "/0(MiChip)/2(MemCtlA)/17(fsm2i)*1.[4]-2" A1A a A1A OCA 13280 0 0 2 AE r R145 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A OAF 13520 0 0 2 AE r R146 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/5/6/1(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 13744 0 0 2 AE r R147 "/0(MiChip)/4(RefreshCtr)*1.Output[7]-2" A1A a A1A O86 13840 0 0 2 AE r R148 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/3/0(Inv)*1" A1A a A1A O86 14000 0 0 2 AE r R149 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv5" A1A a A1A OCA 14160 0 0 2 AE r R14A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/3/1(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 14384 0 0 2 AE r R14B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.nLoad-2" A1A a A1A O18 14464 0 0 2 AE r R14C "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.load-2" A1A a A1A O18 14544 0 0 2 AE r R14D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][4]-2" A1A a A1A O86 14640 0 0 2 AE r R14E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/5/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/2/0(Inv)*1*1" A1A a A1A O18 14784 0 0 2 AE r R14F "A1-2" A1A a A1A O18 14864 0 0 2 AE r R150 "/0(MiChip)*1.[27][2]-2" A1A a A1A O18 14944 0 0 2 AE r R151 "Dout7-2" A1A a A1A OCA 15040 0 0 2 AE r R152 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A OC4 15280 0 0 2 AE r R153 "/0(MiChip)/0(RasDecode)/5(A21o2i)*1" A1A a A1A O86 15600 0 0 2 AE r R154 "/0(MiChip)/0(RasDecode)/8(DecoderS)/10(Inv)" A1A a A1A O18 15744 0 0 2 AE r R155 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[9]-2" A1A a A1A O98 15840 0 0 2 AE r R156 "/0(MiChip)/0(RasDecode)/8(DecoderS)/4(NormalizedNor3)/0(Nor3)" A1A a A1A O24 16160 0 0 2 AE r R157 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 16944 0 0 2 AE r R158 "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)*1.nAd[0]-2" A1A a A1A O18 17024 0 0 2 AE r R159 "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)*1.[5]-2" A1A a A1A O86 17120 0 0 2 AE r R15A "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1" A1A a A1A O18 17264 0 0 2 AE r R15B "/0(MiChip)/5(DataMux)/12(ParGen)*1.[14]-2" A1A a A1A O16D 17360 0 0 2 AE r R15C "/0(MiChip)/2(MemCtlA)/13(B)//0(MiChip)/1(ClockGen)/2(B)//0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer1" A1A a A1A O18 17584 0 0 2 AE r R15D "Din4-2" A1A a A1A O86 17680 0 0 2 AE r R15E "/0(MiChip)/2(MemCtlA)/19(fsmc1)/0(Decoder)/3(Inv)" A1A a A1A OA4 17840 0 0 2 AE r R15F "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1" A1A a A1A O18 18224 0 0 2 AE r R160 "Dout5-2" A1A a A1A O18 18304 0 0 2 AE r R161 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[9][1]-2" A1A a A1A O18 18384 0 0 2 AE r R162 "/0(MiChip)/0(RasDecode)*1.RasN[1]-2" A1A a A1A O168 18480 0 0 2 AE r R163 "/0(MiChip)/2(MemCtlA)/3(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O86 18800 0 0 2 AE r R164 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1" A1A a A1A OC4 18960 0 0 2 AE r R165 "/0(MiChip)/0(RasDecode)/9(A21o2i)*1" A1A a A1A O86 19280 0 0 2 AE r R166 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1" A1A a A1A O98 19440 0 0 2 AE r R167 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5)/2(NormalizedNor3)/0(Nor3)" A1A a A1A O86 19760 0 0 2 AE r R168 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/2/0(Inv)*1" A1A a A1A O86 19920 0 0 2 AE r R169 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv10" A1A a A1A O98 20080 0 0 2 AE r R16A "/0(MiChip)/2(MemCtlA)/7(ffrs1)/1(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A OA4 20400 0 0 2 AE r R16B "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1" A1A a A1A OCA 20800 0 0 2 AE r R16C "/0(MiChip)/2(MemCtlA)/7(ffrs1)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O24 21040 0 0 2 AE r R16D "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1" A1A a A1A O86 21840 0 0 2 AE r R16E "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 22000 0 0 2 AE r R16F "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1" A1A a A1A OA4 22160 0 0 2 AE r R170 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1" A1A a A1A O98 22560 0 0 2 AE r R171 "/0(MiChip)/6(AddrCtl)/10(Decoder)/2(NormalizedNor3)/0(Nor3)" A1A a A1A O24 22880 0 0 2 AE r R172 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 23680 0 0 2 AE r R173 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver11" A1A a A1A O18 23984 0 0 2 AE r R174 "/0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)*1.[4]-2" A1A a A1A O18 24064 0 0 2 AE r R175 "/0(MiChip)/4(RefreshCtr)*1.Output[6]-2" A1A a A1A O86 24160 0 0 2 AE r R176 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv7" A1A a A1A O24 24320 0 0 2 AE r R177 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 25104 0 0 2 AE r R178 "A8-2" A1A a A1A O18 25184 0 0 2 AE r R179 "A7-2" A1A a A1A O18 25264 0 0 2 AE r R17A "/0(MiChip)/3(AddrMux)*1.In1[0]-2" A1A a A1A O86 25360 0 0 2 AE r R17B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0(counterCLP2NL)/0(Inv)*1" A1A a A1A O86 25520 0 0 2 AE r R17C "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv15" A1A a A1A OCE 25680 0 0 2 AE r R17D "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver15" A1A a A1A O24 26000 0 0 2 AE r R17E "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1" A1A a A1A O24 26800 0 0 2 AE r R17F "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 27600 0 0 2 AE r R180 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/3/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/4/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/5/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/2/0(Inv)*1*1*1*1*1*1*1" A1A a A1A O24 27760 0 0 2 AE r R181 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCA 28560 0 0 2 AE r R182 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O24 28800 0 0 2 AE r R183 "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O175 A2 0 0 3200 832 2 O176 A2 0 0 3200 80 1 O166 0 0 0 2 A4 r RB AE r RB 0 0 3200 80 R2 1059061760 0 0 0 0 0 0 0 O177 A2 0 0 3200 80 1 O166 0 0 0 2 A4 r RC AE r RC 0 0 3200 80 R2 1059061760 0 0 0 0 752 0 0 0 0 3200 832 R184 "MIInnerRight2" 1031153506 0 1 0 29600 0 0 0 0 0 32800 832 R185 "MIInnerIntRow2" 1030556027 0 0 0 0 3488 0 1 AE r R186 "Row2" O178 A29 0 0 32800 2592 140 0 0 32800 2592 5 2 AE r RA1 A4 r RA1 O156 7384 1952 O45 7384 1952 O45 14424 1952 O11E 14424 0 O119 7384 1952 5 2 AE r R187 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21).[2]" A4 r R187 OF2 22024 608 O45 22024 608 O45 22504 608 O119 22504 0 O119 22024 0 5 2 AE r RA3 A4 r RA3 OF9 11464 1696 O45 11464 1696 O45 16024 1696 O159 16024 1696 OEC 11464 0 5 2 AE r RA4 A4 r RA4 O11C 14584 672 O45 14584 672 O45 15704 672 O12F 15704 672 O11D 14584 0 7 2 AE r RA5 A4 r RA5 O101 11784 992 O45 12504 992 O45 11784 992 O45 13944 992 OF0 13944 992 OF6 12504 0 OF6 11784 0 5 2 AE r R188 "/0(MiChip)/5(DataMux)*1.[28][0]" A4 r R188 O179 A9 8912 32 A6 AA 0 4104 2208 O45 4104 2208 O45 12984 2208 OF4 12984 2208 O11B 4104 0 5 2 AE r R189 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[5]" A4 r R189 OF5 14104 2208 O45 14104 2208 O45 15624 2208 OF4 15624 2208 O11B 14104 0 5 2 AE r R18A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][4]" A4 r R18A O143 14344 96 O45 14344 96 O45 15544 96 O10D 15544 96 OFA 14344 0 7 2 AE r R18B "/0(MiChip)/3(AddrMux)*1.In1[5]" A4 r R18B O17A A9 3712 32 A6 AA 0 19944 32 O45 22344 32 O45 19944 32 O45 23624 32 OEE 23624 0 OEE 22344 0 OEE 19944 0 5 2 AE r R18C "/0(MiChip)*1.[49]" A4 r R18C O12E 4904 32 O45 4904 32 O45 5624 32 OEE 5624 0 O116 4904 32 7 2 AE r R18D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][5]" A4 r R18D O17B A9 1072 32 A6 AA 0 13624 416 O45 13944 416 O45 13624 416 O45 14664 416 O10C 14664 0 O10C 13944 0 O10C 13624 0 5 2 AE r RB0 A4 r RB0 O14B 2344 2528 O45 2344 2528 O45 3304 2528 O116 3304 0 OEE 2344 2528 11 2 AE r RB2 A4 r RB2 O17C A9 7712 32 A6 AA 0 9384 2144 O45 12024 2144 O45 16184 2144 O45 9384 2144 O45 15064 2144 O45 17064 2144 O10C 17064 2144 O13E 12024 0 O10C 15064 2144 O10C 16184 2144 O10C 9384 2144 9 2 AE r RB3 A4 r RB3 O17D A9 5152 32 A6 AA 0 15144 1376 O45 15864 1376 O45 15144 1376 O45 19064 1376 O45 20264 1376 O127 20264 1376 OFE 15864 0 O127 19064 1376 O127 15144 1376 16 2 AE r R18E "/0(MiChip)/0(RasDecode)/8(DecoderS)*1.nnAd[1]" A4 r R18E O145 16264 1440 O45 16408 1440 O45 19144 1440 O45 16264 1440 O45 17144 1440 O45 20344 1440 O105 20344 1440 O17E A9 32 1376 A6 AB 0 16408 96 O105 17144 1440 O105 19144 1440 O105 16264 1440 O17F A9 736 32 A6 AA 0 15704 96 O45 15704 96 O45 16408 96 O17E 16408 96 OFA 15704 0 5 2 AE r R18F "Dout4" A4 r R18F O12D 23944 96 O45 23944 96 O45 29624 96 O10D 29624 96 OFA 23944 0 5 2 AE r R190 "/0(MiChip)/2(MemCtlA)*1.iHoldA" A4 r R190 O162 17704 96 O45 17704 96 O45 23224 96 O10D 23224 96 OFA 17704 0 3 2 AE r R191 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[3]" A4 r R191 OFB 7224 32 OEE 7304 0 OEE 7224 0 5 2 AE r RB6 A4 r RB6 O149 21944 288 O45 21944 288 O45 24504 288 OF3 24504 288 O10A 21944 0 7 2 AE r RB7 A4 r RB7 O152 11624 480 O45 17224 480 O45 11624 480 O45 19224 480 O133 19224 480 O133 17224 480 O13D 11624 0 5 2 AE r R192 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2).[6]" A4 r R192 O103 28744 160 O45 28744 160 O45 29304 160 O112 29304 160 O10E 28744 0 5 2 AE r R193 "/0(MiChip)/2(MemCtlA)*1.sCAS" A4 r R193 O141 20904 1696 O45 20904 1696 O45 23144 1696 O159 23144 1696 OEC 20904 0 7 2 AE r RBA A4 r RBA O11C 15624 416 O45 15944 416 O45 15624 416 O45 16744 416 O13E 16744 416 O10C 15944 0 O10C 15624 0 5 2 AE r R194 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[10]" A4 r R194 O118 13384 96 O45 13384 96 O45 13704 96 OFA 13704 0 OFA 13384 0 5 2 AE r RBD A4 r RBD O13B 18264 1696 O45 18264 1696 O45 20664 1696 O159 20664 1696 OEC 18264 0 5 2 AE r RBE A4 r RBE O111 22744 608 O45 22744 608 O45 24024 608 O11E 24024 608 O119 22744 0 9 2 AE r RBF A4 r RBF O179 11544 1504 O45 16024 1504 O45 11544 1504 O45 16344 1504 O45 20424 1504 OF1 20424 1504 O100 16024 0 OF1 16344 1504 O100 11544 0 5 2 AE r RC0 A4 r RC0 OF5 4424 96 O45 4424 96 O45 5944 96 O10D 5944 96 OFA 4424 0 5 2 AE r R195 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21).[2]" A4 r R195 O17B 17144 416 O45 17144 416 O45 18184 416 O10C 18184 0 O10C 17144 0 5 2 AE r RC1 A4 r RC1 O180 A9 432 32 A6 AA 0 14824 416 O45 14824 416 O45 15224 416 O13E 15224 416 O10C 14824 0 7 2 AE r R196 "Din0" A4 r R196 O181 A9 22672 32 A6 AA 0 4424 352 O45 24584 352 O45 4424 352 O45 27064 352 OF4 27064 0 OF4 24584 0 O11B 4424 352 5 2 AE r R197 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[11]" A4 r R197 O180 14744 800 O45 14744 800 O45 15144 800 O22 15144 0 O22 14744 0 5 2 AE r RC2 A4 r RC2 O182 A9 5312 32 A6 AA 0 6664 928 O45 6664 928 O45 11944 928 OEB 11944 0 OF7 6664 928 3 2 AE r RC4 A4 r RC4 OFB 28424 32 OEE 28504 0 O116 28424 32 7 2 AE r R198 "Din1" A4 r R198 O183 A9 8352 32 A6 AA 0 19704 2272 O45 27864 2272 O45 19704 2272 O45 28024 2272 OF3 28024 0 O10A 27864 2272 O10A 19704 2272 5 2 AE r R199 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[1]" A4 r R199 O14B 27704 32 O45 27704 32 O45 28664 32 OEE 28664 0 OEE 27704 0 5 2 AE r RC6 A4 r RC6 O140 19544 480 O45 19544 480 O45 20424 480 O13D 20424 0 O13D 19544 0 5 2 AE r RC8 A4 r RC8 O184 A9 192 32 A6 AA 0 6424 96 O45 6424 96 O45 6584 96 OFA 6584 0 O10D 6424 96 5 2 AE r R19A "Din12" A4 r R19A OFC 6024 2272 O45 6024 2272 O45 10744 2272 O10A 10744 2272 OF3 6024 0 11 2 AE r RC9 A4 r RC9 O185 A9 11792 32 A6 AA 0 12424 864 O45 17944 864 O45 22264 864 O45 12424 864 O45 20504 864 O45 24184 864 OEC 24184 864 O159 17944 0 O159 20504 0 O159 22264 0 O159 12424 0 7 2 AE r RCA A4 r RCA O104 11624 2272 O45 12584 2272 O45 11624 2272 O45 17624 2272 OF3 17624 0 O10A 12584 2272 O10A 11624 2272 5 2 AE r R19B "A6" A4 r R19B O11A 22184 2208 O45 22184 2208 O45 26504 2208 OF4 26504 2208 O11B 22184 0 3 2 AE r RCC A4 r RCC O135 14984 36 O136 14984 0 O186 A9 32 2556 A6 AB 0 14984 36 5 2 AE r RCB A4 r RCB O15D 23144 480 O45 23144 480 O45 26344 480 O133 26344 480 O13D 23144 0 9 2 AE r RCD A4 r RCD O187 A9 6272 32 A6 AA 0 18104 800 O45 20664 800 O45 18104 800 O45 22424 800 O45 24344 800 O14D 24344 800 O22 20664 0 O22 22424 0 O22 18104 0 5 2 AE r RCE A4 r RCE O108 25224 224 O45 25224 224 O45 27544 224 O109 27544 224 O107 25224 0 3 2 AE r R19C "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[15]" A4 r R19C OFB 25624 32 OEE 25704 0 OEE 25624 0 3 2 AE r RCF A4 r RCF O188 A9 352 32 A6 AB 0 10984 32 O116 11304 32 OEE 10984 0 5 2 AE r R19D "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nnAd[0]" A4 r R19D O15C 10424 1696 O45 10424 1696 O45 10664 1696 OEC 10664 0 O159 10424 1696 5 2 AE r RD0 A4 r RD0 O141 25144 288 O45 25144 288 O45 27384 288 OF3 27384 288 O10A 25144 0 5 2 AE r R19E "/0(MiChip)/0(RasDecode)*1.RasN[0]" A4 r R19E O118 18984 928 O45 18984 928 O45 19304 928 OF7 19304 928 OEB 18984 0 5 2 AE r R19F "Din7" A4 r R19F O189 A9 7872 32 A6 AA 0 18424 2144 O45 18424 2144 O45 26264 2144 O13E 26264 0 O10C 18424 2144 5 2 AE r RD3 A4 r RD3 O161 17864 2272 O45 17864 2272 O45 19624 2272 OF3 19624 0 OF3 17864 0 5 2 AE r R1A0 "Din13" A4 r R1A0 OEA 5064 288 O45 5064 288 O45 21624 288 OF3 21624 288 O10A 5064 0 5 2 AE r R1A1 "Din8" A4 r R1A1 O18A A9 8672 32 A6 AA 0 21304 2528 O45 21304 2528 O45 29944 2528 OEE 29944 2528 O116 21304 0 5 2 AE r RD4 A4 r RD4 O117 18424 1568 O45 18424 1568 O45 20504 1568 OF6 20504 1568 OF0 18424 0 17 2 AE r RD5 A4 r RD5 O18B A9 22992 32 A6 AA 0 4824 160 O45 10744 160 O45 22904 160 O45 26024 160 O45 4824 160 O45 26824 160 O45 24904 160 O45 21064 160 O45 27784 160 O10E 27784 0 O10E 10744 0 O10E 21064 0 O10E 22904 0 O112 24904 160 O10E 26024 0 O10E 26824 0 O10E 4824 0 11 2 AE r RD8 A4 r RD8 O187 12904 1248 O45 14584 1248 O45 18744 1248 O45 12904 1248 O45 15464 1248 O45 19144 1248 OFD 19144 0 O114 14584 1248 OFD 15464 0 OFD 18744 0 OFD 12904 0 5 2 AE r R1A2 "/0(MiChip)/0(RasDecode)*1.RasN[3]" A4 r R1A2 O18C A9 832 32 A6 AA 0 15304 1952 O45 15304 1952 O45 16104 1952 O11E 16104 0 O11E 15304 0 3 2 AE r RD9 A4 r RD9 OFB 8504 2016 O102 8584 2016 O13A 8504 0 5 2 AE r RDA A4 r RDA O184 8584 1632 O45 8584 1632 O45 8744 1632 OEB 8744 1632 OF7 8584 0 11 2 AE r RDB A4 r RDB O18D A9 24912 32 A6 AA 0 4584 2336 O45 6104 2336 O45 22744 2336 O45 4584 2336 O45 13224 2336 O45 29464 2336 O107 29464 2336 O107 6104 2336 O107 13224 2336 O107 22744 2336 O109 4584 0 5 2 AE r RDD A4 r RDD O12E 20264 992 O45 20264 992 O45 20984 992 OF6 20984 0 OF6 20264 0 5 2 AE r R1A3 "Din15" A4 r R1A3 O18E A9 1472 32 A6 AA 0 29064 32 O45 29064 32 O45 30504 32 O116 30504 32 OEE 29064 0 13 2 AE r RE0 A4 r RE0 O158 8424 2080 O45 8504 2080 O45 15064 2080 O45 8424 2080 O45 23784 2080 O45 13304 2080 O45 28584 2080 O133 28584 0 O13D 8504 2080 O133 13304 0 O133 15064 0 O13D 23784 2080 O133 8424 0 5 2 AE r R1A4 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21).[2]" A4 r R1A4 O18F A9 3312 32 A6 AA 0 18584 2208 O45 18584 2208 O45 21864 2208 O11B 21864 0 OF4 18584 2208 5 2 AE r RE1 A4 r RE1 O11C 13224 800 O45 13224 800 O45 14344 800 O14D 14344 800 O22 13224 0 5 2 AE r R1A5 "Dout11" A4 r R1A5 O12E 4024 32 O45 4024 32 O45 4744 32 OEE 4744 0 O116 4024 32 5 2 AE r RE3 A4 r RE3 O14B 2264 96 O45 2264 96 O45 3224 96 OFA 3224 0 O10D 2264 96 5 2 AE r R1A6 "Dout12" A4 r R1A6 O111 6264 2528 O45 6264 2528 O45 7544 2528 O116 7544 0 OEE 6264 2528 7 2 AE r R1A7 "/0(MiChip)/2(MemCtlA)/19(fsmc1)/0(Decoder)*1.nAd[0]" A4 r R1A7 O160 9784 224 O45 12104 224 O45 9784 224 O45 17784 224 O107 17784 0 O107 12104 0 O107 9784 0 7 2 AE r R1A8 "/0(MiChip)/2(MemCtlA)*1.[3]" A4 r R1A8 O12E 16664 96 O45 16824 96 O45 16664 96 O45 17384 96 OFA 17384 0 O10D 16824 96 O10D 16664 96 11 2 AE r R1A9 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv).nEnable" A4 r R1A9 O190 A9 16112 32 A6 AA 0 7784 1824 O45 10024 1824 O45 14904 1824 O45 7784 1824 O45 12344 1824 O45 23864 1824 O121 23864 0 O130 10024 1824 O130 12344 1824 O130 14904 1824 O121 7784 0 5 2 AE r R1AA "/0(MiChip)/2(MemCtlA)*1.RefCy" A4 r R1AA O149 18584 608 O45 18584 608 O45 21144 608 O11E 21144 608 O119 18584 0 5 2 AE r R1AB "/0(MiChip)/2(MemCtlA)*1.C1" A4 r R1AB O11F 11704 96 O45 11704 96 O45 13064 96 O10D 13064 96 OFA 11704 0 5 2 AE r RE5 A4 r RE5 O11C 18984 992 O45 18984 992 O45 20104 992 OF6 20104 0 OF0 18984 992 5 2 AE r R1AC "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[7][1]" A4 r R1AC O12D 19784 1952 O45 19784 1952 O45 25464 1952 O11E 25464 0 O11E 19784 0 3 2 AE r R1AD "/0(MiChip)/0(RasDecode)*1.[9]" A4 r R1AD OFB 12744 32 OEE 12824 0 OEE 12744 0 5 2 AE r R1AE "/0(MiChip)/5(DataMux)*1.[15][2]" A4 r R1AE O139 8824 1184 O45 8824 1184 O45 9464 1184 OFE 9464 1184 O127 8824 0 5 2 AE r R1AF "/0(MiChip)/2(MemCtlA)*1.[53]" A4 r R1AF O12D 12264 928 O45 12264 928 O45 17944 928 OF7 17944 928 OEB 12264 0 5 2 AE r R1B0 "/0(MiChip)/5(DataMux)*1.[15][3]" A4 r R1B0 O17A 8744 1248 O45 8744 1248 O45 12424 1248 O114 12424 1248 OFD 8744 0 5 2 AE r R1B1 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two" A4 r R1B1 O11F 19704 928 O45 19704 928 O45 21064 928 OF7 21064 928 OEB 19704 0 5 2 AE r R1B2 "/0(MiChip)/5(DataMux)*1.[15][5]" A4 r R1B2 OF8 8824 1376 O45 8824 1376 O45 14024 1376 OFE 14024 0 O127 8824 1376 7 2 AE r R1B3 "/0(MiChip)/6(AddrCtl)/14(Decoder)*1.nnAd[0]" A4 r R1B3 O17B 9224 96 O45 10184 96 O45 9224 96 O45 10264 96 OFA 10264 0 OFA 10184 0 OFA 9224 0 5 2 AE r REE A4 r REE O191 A9 4432 32 A6 AA 0 20184 416 O45 20184 416 O45 24584 416 O13E 24584 416 O10C 20184 0 5 2 AE r REF A4 r REF O192 A9 6832 32 A6 AA 0 8664 1568 O45 8664 1568 O45 15464 1568 OF6 15464 1568 OF0 8664 0 9 2 AE r R1B4 "/0(MiChip)*1.DatLatClk" A4 r R1B4 O193 A9 13792 32 A6 AA 0 2424 608 O45 3224 608 O45 2424 608 O45 3384 608 O45 16184 608 O119 16184 0 O11E 3224 608 O119 3384 0 O11E 2424 608 7 2 AE r RC A4 r RC O194 A9 8592 32 A6 AA 0 8024 2528 O45 15944 2528 O45 8024 2528 O45 16584 2528 OEE 16584 2528 OEE 15944 2528 O116 8024 0 5 2 AE r R1B5 "/0(MiChip)*1.SelR/C'" A4 r R1B5 OF2 11864 416 O45 11864 416 O45 12344 416 O10C 12344 0 O10C 11864 0 9 2 AE r RF0 A4 r RF0 O195 A9 19312 32 A6 AA 0 6584 2016 O45 7464 2016 O45 6584 2016 O45 22504 2016 O45 25864 2016 O13A 25864 0 O13A 7464 0 O102 22504 2016 O102 6584 2016 7 2 AE r R1B6 "/0(MiChip)*1.RASn[0]" A4 r R1B6 O14A 5544 1696 O45 9304 1696 O45 5544 1696 O45 9544 1696 O159 9544 1696 O159 9304 1696 OEC 5544 0 5 2 AE r RF1 A4 r RF1 O10B 17064 1952 O45 17064 1952 O45 18744 1952 O119 18744 1952 O11E 17064 0 13 2 AE r RF2 A4 r RF2 O196 A9 18592 32 A6 AA 0 5784 736 O45 11384 736 O45 21384 736 O45 5784 736 O45 22824 736 O45 19464 736 O45 24344 736 O130 24344 0 O121 11384 736 O121 19464 736 O121 21384 736 O130 22824 0 O130 5784 0 5 2 AE r RF4 A4 r RF4 O197 A9 1632 32 A6 AA 0 24104 608 O45 24104 608 O45 25704 608 O11E 25704 608 O119 24104 0 3 2 AE r R1B7 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/13(counterUpCtrl2).[6]" A4 r R1B7 OFB 8184 32 OEE 8264 0 OEE 8184 0 5 2 AE r RF5 A4 r RF5 O110 13144 1184 O45 13144 1184 O45 20104 1184 OFE 20104 1184 O127 13144 0 5 2 AE r RF6 A4 r RF6 O198 A9 6352 32 A6 AA 0 9544 1632 O45 9544 1632 O45 15864 1632 OEB 15864 1632 OF7 9544 0 5 2 AE r R1B8 "/0(MiChip)/2(MemCtlA)/19(fsmc1)/0(Decoder)*1.nnAd[0]" A4 r R1B8 O118 9864 416 O45 9864 416 O45 10184 416 O13E 10184 416 O10C 9864 0 5 2 AE r RF7 A4 r RF7 O15C 4104 2400 O45 4104 2400 O45 4344 2400 O112 4344 0 O10E 4104 2400 5 2 AE r R1B9 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[4]" A4 r R1B9 O15C 4264 2528 O45 4264 2528 O45 4504 2528 O116 4504 0 O116 4264 0 7 2 AE r RB A4 r RB O199 A9 12752 32 A6 AA 0 12664 1056 O45 20984 1056 O45 12664 1056 O45 25384 1056 OF1 25384 0 O100 20984 1056 OF1 12664 0 11 2 AE r RF8 A4 r RF8 O195 6504 1888 O45 7384 1888 O45 22424 1888 O45 6504 1888 O45 10504 1888 O45 25784 1888 O12F 25784 0 O12F 7384 0 O12F 10504 0 O11D 22424 1888 O11D 6504 1888 5 2 AE r RFC A4 r RFC O19A A9 5472 32 A6 AA 0 8344 32 O45 8344 32 O45 13784 32 OEE 13784 0 O116 8344 32 11 2 AE r RFE A4 r RFE O142 12584 1312 O45 14504 1312 O45 18504 1312 O45 12584 1312 O45 15384 1312 O45 19064 1312 O114 19064 0 OFD 14504 1312 O114 15384 0 O114 18504 0 O114 12584 0 3 2 AE r RFF A4 r RFF OFB 27464 32 OEE 27544 0 O116 27464 32 5 2 AE r R101 A4 r R101 O17B 18344 416 O45 18344 416 O45 19384 416 O13E 19384 416 O10C 18344 0 7 2 AE r R1BA "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[9][2]" A4 r R1BA O104 13864 32 O45 14264 32 O45 13864 32 O45 19864 32 OEE 19864 0 OEE 14264 0 OEE 13864 0 7 2 AE r R102 A4 r R102 O148 9384 1440 O45 10424 1440 O45 9384 1440 O45 14024 1440 O105 14024 1440 O128 10424 0 O128 9384 0 5 2 AE r R1BB "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[15]" A4 r R1BB O12A 5704 32 O45 5704 32 O45 7624 32 OEE 7624 0 OEE 5704 0 7 2 AE r R103 A4 r R103 O19B A9 20832 32 A6 AA 0 7704 1760 O45 14904 1760 O45 7704 1760 O45 28504 1760 O22 28504 1760 O14D 14904 0 O22 7704 1760 5 2 AE r R1BC "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]" A4 r R1BC O149 9944 1056 O45 9944 1056 O45 12504 1056 O100 12504 1056 OF1 9944 0 5 2 AE r R1BD "/0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)*1.[3]" A4 r R1BD O15B 6664 96 O45 6664 96 O45 9144 96 OFA 9144 0 OFA 6664 0 5 2 AE r R1BE "/0(MiChip)/4(RefreshCtr)*1.[3][3]" A4 r R1BE O139 6504 224 O45 6504 224 O45 7144 224 O107 7144 0 O107 6504 0 5 2 AE r R106 A4 r R106 O18F 17304 1632 O45 17304 1632 O45 20584 1632 OEB 20584 1632 OF7 17304 0 5 2 AE r R1BF "/0(MiChip)/5(DataMux)*1.[11][0]" A4 r R1BF O11F 16904 2528 O45 16904 2528 O45 18264 2528 OEE 18264 2528 O116 16904 0 5 2 AE r R107 A4 r R107 O11C 25304 416 O45 25304 416 O45 26424 416 O13E 26424 416 O10C 25304 0 5 2 AE r R1C0 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[7]" A4 r R1C0 OF2 24264 224 O45 24264 224 O45 24744 224 O109 24744 224 O107 24264 0 5 2 AE r R1C1 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[15]" A4 r R1C1 OF5 5544 2144 O45 5544 2144 O45 7064 2144 O13E 7064 0 O10C 5544 2144 5 2 AE r R1C2 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]" A4 r R1C2 O120 10024 1184 O45 10024 1184 O45 12664 1184 OFE 12664 1184 O127 10024 0 5 2 AE r R1C3 "/0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)*1.[5]" A4 r R1C3 O180 6344 416 O45 6344 416 O45 6744 416 O10C 6744 0 O13E 6344 416 5 2 AE r R1C4 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21).[2]" A4 r R1C4 O17D 19304 672 O45 19304 672 O45 24424 672 O12F 24424 672 O11D 19304 0 5 2 AE r R1C5 "/0(MiChip)/2(MemCtlA)*1.ores'" A4 r R1C5 OF2 20344 1184 O45 20344 1184 O45 20824 1184 O127 20824 0 O127 20344 0 5 2 AE r R1C6 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][0]" A4 r R1C6 O18E 26184 32 O45 26184 32 O45 27624 32 OEE 27624 0 O116 26184 32 5 2 AE r R1C7 "/0(MiChip)/3(AddrMux)*1.In1[1]" A4 r R1C7 O117 20584 480 O45 20584 480 O45 22664 480 O133 22664 480 O13D 20584 0 5 2 AE r R108 A4 r R108 O10B 16984 672 O45 16984 672 O45 18664 672 O12F 18664 672 O11D 16984 0 5 2 AE r R10A A4 r R10A O155 7304 672 O45 7304 672 O45 14504 672 O11D 14504 0 O12F 7304 672 3 2 AE r R1C8 "PDin16" A4 r R1C8 O19C A9 3656 24 A6 AA 0 0 36 O45 3624 32 O136 3624 0 7 2 AE r R1C9 "/0(MiChip)/3(AddrMux)*1.In1[2]" A4 r R1C9 O19D A9 6192 32 A6 AA 0 18024 224 O45 21784 224 O45 18024 224 O45 24184 224 O107 24184 0 O107 21784 0 O107 18024 0 5 2 AE r R10B A4 r R10B O18C 24024 32 O45 24024 32 O45 24824 32 O116 24824 32 OEE 24024 0 13 2 AE r R10D A4 r R10D O19E A9 25552 32 A6 AA 0 4184 2464 O45 10504 2464 O45 27624 2464 O45 4184 2464 O45 28824 2464 O45 26584 2464 O45 29704 2464 OFA 29704 2464 OFA 10504 2464 OFA 26584 2464 OFA 27624 2464 O10D 28824 0 OFA 4184 2464 5 2 AE r R10E A4 r R10E O118 15784 2208 O45 15784 2208 O45 16104 2208 OF4 16104 2208 O11B 15784 0 5 2 AE r R1CA "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nAd[0]" A4 r R1CA O197 10584 864 O45 10584 864 O45 12184 864 OEC 12184 864 O159 10584 0 5 2 AE r R1CB "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21).[2]" A4 r R1CB O117 18824 2528 O45 18824 2528 O45 20904 2528 OEE 20904 2528 O116 18824 0 5 2 AE r R1CC "RPadEnb" A4 r R1CC O103 16984 2208 O45 16984 2208 O45 17544 2208 O11B 17544 0 OF4 16984 2208 11 2 AE r R112 A4 r R112 O18D 4664 2400 O45 6184 2400 O45 22824 2400 O45 4664 2400 O45 13304 2400 O45 29544 2400 O10E 29544 2400 O10E 6184 2400 O10E 13304 2400 O10E 22824 2400 O112 4664 0 5 2 AE r R1CD "/0(MiChip)/4(RefreshCtr)*1.[3][15]" A4 r R1CD OF2 25064 32 O45 25064 32 O45 25544 32 OEE 25544 0 OEE 25064 0 7 2 AE r R1CE "Dout0" A4 r R1CE O19F A9 18112 32 A6 AA 0 7864 544 O45 17384 544 O45 7864 544 O45 25944 544 O102 25944 0 O13A 17384 544 O102 7864 0 7 2 AE r R1CF "/0(MiChip)/2(MemCtlA)/19(fsmc1)/0(Decoder)*1.nEnable" A4 r R1CF O15B 9704 800 O45 10264 800 O45 9704 800 O45 12184 800 O22 12184 0 O14D 10264 800 O22 9704 0 5 2 AE r R1D0 "/0(MiChip)/4(RefreshCtr)*1.[3].Cin" A4 r R1D0 O118 7624 2528 O45 7624 2528 O45 7944 2528 O116 7944 0 OEE 7624 2528 13 2 AE r R1D1 "/0(MiChip)*1.LdStatus[1]" A4 r R1D1 O190 7704 1120 O45 9464 1120 O45 12264 1120 O45 7704 1120 O45 14824 1120 O45 9944 1120 O45 23784 1120 O105 23784 0 O105 9464 0 O128 9944 1120 O128 12264 1120 O128 14824 1120 O105 7704 0 0 0 4320 0 1 AE r R1D2 "MIInnerChan3" O1A0 A2 0 0 32800 864 113 O1A1 A2 0 0 2240 832 2 O1A2 A2 0 0 2240 80 1 O1A3 A9 2240 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 2240 80 R2 1059061760 0 0 0 0 0 0 0 O1A4 A2 0 0 2240 80 1 O1A3 0 0 0 2 A4 r RC AE r RC 0 0 2240 80 R2 1059061760 0 0 0 0 752 0 0 0 0 2240 832 R1D3 "MIInnerLeft3" 1031153506 0 1 0 0 0 0 0 O18 2224 0 0 2 AE r R1D4 "PDWPout-3" A1A a A1A O18 2304 0 0 2 AE r R1D5 "PA10-3" A1A a A1A O24 2400 0 0 2 AE r R1D6 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 3200 0 0 2 AE r R1D7 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 3984 0 0 2 AE r R1D8 "Dout11-3" A1A a A1A O18 4064 0 0 2 AE r R1D9 "/0(MiChip)/4(RefreshCtr)*1.[8][9]-3" A1A a A1A O24 4160 0 0 2 AE r R1DA "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple15//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple14//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple13//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple12//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple11//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple10//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple9//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple8//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple7//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 4960 0 0 2 AE r R1DB "/0(MiChip)/5(DataMux)/12(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 5440 0 0 2 AE r R1DC "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 5904 0 0 2 AE r R1DD "Din11-3" A1A a A1A OCE 6000 0 0 2 AE r R1DE "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver3" A1A a A1A O18 6304 0 0 2 AE r R1DF "/0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)*1.[5]-3" A1A a A1A OCE 6400 0 0 2 AE r R1E0 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver9" A1A a A1A OB6 6720 0 0 2 AE r R1E1 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1*1*1" A1A a A1A OA4 7200 0 0 2 AE r R1E2 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1*1*1" A1A a A1A O18 7584 0 0 2 AE r R1E3 "/0(MiChip)/4(RefreshCtr)*1.[3].Cin-3" A1A a A1A O24 7680 0 0 2 AE r R1E4 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1*1*1" A1A a A1A OCA 8480 0 0 2 AE r R1E5 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 8704 0 0 2 AE r R1E6 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[6][1]-3" A1A a A1A ODD 8800 0 0 2 AE r R1E7 "/0(MiChip)/5(DataMux)/12(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 9280 0 0 2 AE r R1E8 "/0(MiChip)/0(RasDecode)/8(DecoderS)/13(Inv)" A1A a A1A O18 9424 0 0 2 AE r R1E9 "/0(MiChip)/5(DataMux)*1.[15][2]-3" A1A a A1A O86 9520 0 0 2 AE r R1EA "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv2" A1A a A1A O86 9680 0 0 2 AE r R1EB "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv7" A1A a A1A OCE 9840 0 0 2 AE r R1EC "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver7" A1A a A1A OCA 10160 0 0 2 AE r R1ED "/0(MiChip)/2(MemCtlA)/19(fsmc1)/0(Decoder)/1(NormalizedNor2)/0(Nor2)" A1A a A1A O18 10384 0 0 2 AE r R1EE "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nnAd[0]-3" A1A a A1A O24 10480 0 0 2 AE r R1EF "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 11264 0 0 2 AE r R1F0 "Din6-3" A1A a A1A O24 11360 0 0 2 AE r R1F1 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 12144 0 0 2 AE r R1F2 "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nAd[0]-3" A1A a A1A O86 12240 0 0 2 AE r R1F3 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/1(Inv)" A1A a A1A OA4 12400 0 0 2 AE r R1F4 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 12800 0 0 2 AE r R1F5 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 12944 0 0 2 AE r R1F6 "/0(MiChip)/5(DataMux)*1.[28][0]-3" A1A a A1A O18 13024 0 0 2 AE r R1F7 "/0(MiChip)/2(MemCtlA)*1.C1-3" A1A a A1A OCE 13120 0 0 2 AE r R1F8 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver2" A1A a A1A ODD 13440 0 0 2 AE r R1F9 "/0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 13904 0 0 2 AE r R1FA "/0(MiChip)*1.RASX-3" A1A a A1A O18 13984 0 0 2 AE r R1FB "/0(MiChip)/6(AddrCtl)/14(Decoder)*1.nEnable-3" A1A a A1A O171 14080 0 0 2 AE r R1FC "/0(MiChip)/2(MemCtlA)/17(fsm2i)/1(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A OC4 14400 0 0 2 AE r R1FD "/0(MiChip)/0(RasDecode)/3(A21o2i)*1" A1A a A1A OCE 14720 0 0 2 AE r R1FE "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver8" A1A a A1A O86 15040 0 0 2 AE r R1FF "/0(MiChip)/0(RasDecode)/8(DecoderS)/12(Inv)" A1A a A1A O86 15200 0 0 2 AE r R200 "/0(MiChip)/3(AddrMux)/5(Inv)*1" A1A a A1A O86 15360 0 0 2 AE r R201 "/0(MiChip)/2(MemCtlA)/37(Inv)*1" A1A a A1A O18 15504 0 0 2 AE r R202 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][4]-3" A1A a A1A O18 15584 0 0 2 AE r R203 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[5]-3" A1A a A1A O18 15664 0 0 2 AE r R204 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][4]-3" A1A a A1A O86 15760 0 0 2 AE r R205 "/0(MiChip)/2(MemCtlA)/34(Inv)*1" A1A a A1A O1A5 AD -16 0 128 856 O1A6 A2 -16 0 128 856 11 O1C 32 768 0 1 A12 i 58459 O21 16 752 0 4 A10 r R23 A4 r RC A12 i 58459 A16 lor 1 RC O21 16 0 0 4 A10 r R23 A4 r RB A12 i 58457 A16 lor 1 RB O1A7 A2 0 0 32 48 2 O91 0 0 0 0 O45 0 8 0 0 0 0 32 48 R206 "xVia@2" 0 0 0 3 A2A CameFrom r R207 "StdCellBase" A2B OriginalName r R208 "xVia" A17 i 74735 40 704 0 0 O20 40 792 0 1 A10 r R23 O1F 40 8 0 1 A10 r R23 O1E 16 8 0 1 A10 r R23 O1D 16 792 0 1 A10 r R23 O1B 32 40 0 1 A12 i 58457 O22 40 0 0 1 A10 r R23 O1A 128 328 2 1 A10 r R23 16 0 96 832 R209 "C2VD00A.mask" 1048576000 0 1 2 A28 r R20A "Vdd Vdd Gnd" A17 i 74734 1 A18 a A19 15904 0 0 2 AE r R20B "vdd" A1A a A1A O86 16000 0 0 2 AE r R20C "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv9" A1A a A1A O98 16160 0 0 2 AE r R20D "/0(MiChip)/0(RasDecode)/8(DecoderS)/2(NormalizedNor3)/0(Nor3)" A1A a A1A OAF 16480 0 0 2 AE r R20E "/0(MiChip)/2(MemCtlA)/18(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 16704 0 0 2 AE r R20F "/0(MiChip)/0(RasDecode)/8(DecoderS)*1.nAd[1]-3" A1A a A1A O16D 16800 0 0 2 AE r R210 "/0(MiChip)/2(MemCtlA)/13(B)//0(MiChip)/1(ClockGen)/2(B)//0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer0" A1A a A1A O98 17040 0 0 2 AE r R211 "/0(MiChip)/0(RasDecode)/8(DecoderS)/3(NormalizedNor3)/0(Nor3)" A1A a A1A O18 17344 0 0 2 AE r R212 "Dout0-3" A1A a A1A ODD 17440 0 0 2 AE r R213 "/0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O171 17920 0 0 2 AE r R214 "/0(MiChip)/2(MemCtlA)/21(fsm2i)/1(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A OA4 18240 0 0 2 AE r R215 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 18624 0 0 2 AE r R216 "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)*1.nAd[0]-3" A1A a A1A O18 18704 0 0 2 AE r R217 "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)*1.[5]-3" A1A a A1A O86 18800 0 0 2 AE r R218 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 18944 0 0 2 AE r R219 "/0(MiChip)/2(MemCtlA)*1.C3-3" A1A a A1A O98 19040 0 0 2 AE r R21A "/0(MiChip)/0(RasDecode)/8(DecoderS)/7(NormalizedNor3)/0(Nor3)" A1A a A1A O18 19344 0 0 2 AE r R21B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[9][1]-3" A1A a A1A O24 19440 0 0 2 AE r R21C "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O98 20240 0 0 2 AE r R21D "/0(MiChip)/0(RasDecode)/8(DecoderS)/6(NormalizedNor3)/0(Nor3)" A1A a A1A O18 20544 0 0 2 AE r R21E "/0(MiChip)/5(DataMux)/12(ParGen)*1.[14]-3" A1A a A1A O18 20624 0 0 2 AE r R21F "Dout5-3" A1A a A1A O86 20720 0 0 2 AE r R220 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv4" A1A a A1A O18 20864 0 0 2 AE r R221 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21).[2]-3" A1A a A1A O18 20944 0 0 2 AE r R222 "Gnd-3" A1A a A1A O18 21024 0 0 2 AE r R223 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two-3" A1A a A1A O18 21104 0 0 2 AE r R224 "/0(MiChip)/2(MemCtlA)*1.RefCy-3" A1A a A1A O86 21200 0 0 2 AE r R225 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv14" A1A a A1A O24 21360 0 0 2 AE r R226 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 22160 0 0 2 AE r R227 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv2" A1A a A1A OCE 22320 0 0 2 AE r R228 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver7" A1A a A1A O18 22624 0 0 2 AE r R229 "/0(MiChip)/3(AddrMux)*1.In1[1]-3" A1A a A1A O86 22720 0 0 2 AE r R22A "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/1(Inv)" A1A a A1A O168 22880 0 0 2 AE r R22B "/0(MiChip)/2(MemCtlA)/1(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 23184 0 0 2 AE r R22C "/0(MiChip)/2(MemCtlA)*1.iHoldA-3" A1A a A1A OB6 23280 0 0 2 AE r R22D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/12(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCA 23760 0 0 2 AE r R22E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/12(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 23984 0 0 2 AE r R22F "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nEnable-3" A1A a A1A OA4 24080 0 0 2 AE r R230 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1" A1A a A1A O18 24464 0 0 2 AE r R231 "PDout0-3" A1A a A1A O86 24560 0 0 2 AE r R232 "/0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1*1*1*1*1*1*1" A1A a A1A O18 24704 0 0 2 AE r R233 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[7]-3" A1A a A1A O18 24784 0 0 2 AE r R234 "/0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)*1.[4]-3" A1A a A1A O24 24880 0 0 2 AE r R235 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 25664 0 0 2 AE r R236 "/0(MiChip)/4(RefreshCtr)*1.Output[6]-3" A1A a A1A O86 25760 0 0 2 AE r R237 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv7" A1A a A1A O86 25920 0 0 2 AE r R238 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv12" A1A a A1A OAF 26080 0 0 2 AE r R239 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/6/1(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 26304 0 0 2 AE r R23A "Din5-3" A1A a A1A O18 26384 0 0 2 AE r R23B "/0(MiChip)/3(AddrMux)*1.In1[0]-3" A1A a A1A O18 26464 0 0 2 AE r R23C "A6-3" A1A a A1A O24 26560 0 0 2 AE r R23D "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple12//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple11//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple10//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple9//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple8//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple7//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 27344 0 0 2 AE r R23E "A8-3" A1A a A1A O18 27424 0 0 2 AE r R23F "/0(MiChip)/3(AddrMux)*1.In0[0]-3" A1A a A1A O18 27504 0 0 2 AE r R240 "A7-3" A1A a A1A O24 27600 0 0 2 AE r R241 "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple14//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple13//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple12//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple11//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple10//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple9//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple8//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple7//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 28384 0 0 2 AE r R242 "/0(MiChip)/3(AddrMux)*1.In1[9]-3" A1A a A1A O24 28480 0 0 2 AE r R243 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 29264 0 0 2 AE r R244 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2).[6]-3" A1A a A1A OCE 29360 0 0 2 AE r R245 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver11" A1A a A1A O24 29680 0 0 2 AE r R246 "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple7//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 30464 0 0 2 AE r R247 "Din15-3" A1A a A1A O1A8 A2 0 0 2240 832 2 O1A9 A2 0 0 2240 80 1 O1A3 0 0 0 2 A4 r RB AE r RB 0 0 2240 80 R2 1059061760 0 0 0 0 0 0 0 O1AA A2 0 0 2240 80 1 O1A3 0 0 0 2 A4 r RC AE r RC 0 0 2240 80 R2 1059061760 0 0 0 0 752 0 0 0 0 2240 832 R248 "MIInnerRight3" 1031153506 0 1 0 30560 0 0 0 0 0 32800 832 R249 "MIInnerIntRow3" 1030556027 0 0 0 0 6912 0 1 AE r R24A "Row3" O1AB A29 0 0 32800 2144 153 0 0 32800 2144 5 2 AE r RA1 A4 r RA1 O1AC A9 13232 32 A6 AA 0 7384 992 O45 7384 992 O45 20584 992 O105 20584 992 OF6 7384 0 3 2 AE r R24B "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21).[2]" A4 r R24B OFB 12744 32 OEE 12824 0 OEE 12744 0 5 2 AE r RA4 A4 r RA4 O139 15064 2080 O45 15064 2080 O45 15704 2080 O133 15704 0 OEE 15064 2080 5 2 AE r RA5 A4 r RA5 O184 13784 96 O45 13784 96 O45 13944 96 OFA 13944 0 O13A 13784 96 5 2 AE r R24C "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/12(counterUp1B2).[1]" A4 r R24C O147 20664 352 O45 20664 352 O45 23704 352 OF4 23704 0 O14D 20664 352 5 2 AE r R189 A4 r R189 O1AD A9 6752 32 A6 AA 0 15624 1504 O45 15624 1504 O45 22344 1504 O119 22344 1504 O100 15624 0 5 2 AE r R188 A4 r R188 O104 12984 1760 O45 12984 1760 O45 18984 1760 OF4 18984 1760 O14D 12984 0 5 2 AE r R18A A4 r R18A O103 14984 2016 O45 14984 2016 O45 15544 2016 O13A 15544 0 OFA 14984 2016 5 2 AE r R24D "/0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)*1.[7]" A4 r R24D O118 24344 1504 O45 24344 1504 O45 24664 1504 O100 24664 0 O119 24344 1504 5 2 AE r R18C A4 r R18C O139 4904 32 O45 4904 32 O45 5544 32 O133 5544 32 OEE 4904 0 5 2 AE r R24E "/0(MiChip)/2(MemCtlA)*1.S1" A4 r R24E O1AE A9 12352 32 A6 AA 0 14104 1120 O45 14104 1120 O45 26424 1120 OF6 26424 1120 O105 14104 0 9 2 AE r R24F "/0(MiChip)/5(DataMux)*1.[28][4]" A4 r R24F O1AF A9 17632 32 A6 AA 0 3144 288 O45 13944 288 O45 3144 288 O45 19464 288 O45 20744 288 O10A 20744 0 O121 13944 288 O121 19464 288 O10A 3144 0 5 2 AE r RB0 A4 r RB0 O1B0 A9 12992 32 A6 AA 0 2344 1888 O45 2344 1888 O45 15304 1888 O107 15304 1888 O12F 2344 0 3 2 AE r R250 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[7]" A4 r R250 OFB 9784 32 OEE 9864 0 OEE 9784 0 5 2 AE r R251 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[2]" A4 r R251 O125 22264 480 O45 22264 480 O45 24984 480 OF7 24984 480 O13D 22264 0 7 2 AE r R252 "/0(MiChip)/5(DataMux)*1.[28][6]" A4 r R252 O1B1 A9 9632 32 A6 AA 0 3944 96 O45 9784 96 O45 3944 96 O45 13544 96 OFA 13544 0 O13A 9784 96 OFA 3944 0 5 2 AE r R18F A4 r R18F O106 26104 480 O45 26104 480 O45 29624 480 O13D 29624 0 OF7 26104 480 5 2 AE r R190 A4 r R190 O144 23224 160 O45 23224 160 O45 27144 160 O11E 27144 160 O10E 23224 0 7 2 AE r R253 "/0(MiChip)/3(AddrMux)*1.In1[7]" A4 r R253 O15D 22424 800 O45 24264 800 O45 22424 800 O45 25624 800 O22 25624 0 O22 24264 0 O114 22424 800 5 2 AE r R254 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2).[1]" A4 r R254 O118 7144 736 O45 7144 736 O45 7464 736 O130 7464 0 O130 7144 0 5 2 AE r R255 "/0(MiChip)/5(DataMux)*1.[28][7]" A4 r R255 O147 10424 672 O45 10424 672 O45 13464 672 O11D 13464 0 O128 10424 672 5 2 AE r RB6 A4 r RB6 O10B 24504 608 O45 24504 608 O45 26184 608 O100 26184 608 O119 24504 0 3 2 AE r R192 A4 r R192 O135 29304 36 O136 29304 0 O1B2 A9 32 2108 A6 AB 0 29304 36 5 2 AE r R256 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2).[2]" A4 r R256 O180 7544 736 O45 7544 736 O45 7944 736 O130 7944 0 O130 7544 0 5 2 AE r RBA A4 r RBA O15D 13544 352 O45 13544 352 O45 16744 352 OF4 16744 0 O14D 13544 352 5 2 AE r R257 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[11]" A4 r R257 O180 29384 96 O45 29384 96 O45 29784 96 O13A 29784 96 OFA 29384 0 5 2 AE r R258 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[8]" A4 r R258 OF2 14744 1504 O45 14744 1504 O45 15224 1504 O119 15224 1504 O100 14744 0 5 2 AE r RBD A4 r RBD O15C 20664 224 O45 20664 224 O45 20904 224 O12F 20904 224 O107 20664 0 5 2 AE r RBE A4 r RBE O161 22264 608 O45 22264 608 O45 24024 608 O119 24024 0 O100 22264 608 5 2 AE r R259 "/0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)*1.[3]" A4 r R259 O15F 13864 608 O45 13864 608 O45 17464 608 O119 17464 0 O119 13864 0 5 2 AE r RC0 A4 r RC0 O101 5944 544 O45 5944 544 O45 8104 544 OF0 8104 544 O102 5944 0 5 2 AE r R25A "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[7]" A4 r R25A O106 22344 672 O45 22344 672 O45 25864 672 O11D 25864 0 O11D 22344 0 5 2 AE r R25B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[0]" A4 r R25B O13B 23864 352 O45 23864 352 O45 26264 352 OF4 26264 0 OF4 23864 0 3 2 AE r RC1 A4 r RC1 O1B3 A9 15256 24 A6 AA 0 0 164 O45 15224 160 O1B4 A9 32 188 A6 AB 0 15224 0 3 2 AE r R25C "/0(MiChip)/2(MemCtlA)*1.PadEnb" A4 r R25C O135 16504 36 O136 16504 0 O1B2 16504 36 5 2 AE r R196 A4 r R196 O122 4424 416 O45 4424 416 O45 10184 416 OEC 10184 416 O10C 4424 0 5 2 AE r RC2 A4 r RC2 O1B5 A9 8112 32 A6 AA 0 6664 1568 O45 6664 1568 O45 14744 1568 O102 14744 1568 OF0 6664 0 5 2 AE r R25D "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[14]" A4 r R25D O1B6 A9 6432 32 A6 AA 0 21304 32 O45 21304 32 O45 27704 32 O133 27704 32 OEE 21304 0 5 2 AE r RC4 A4 r RC4 O184 28264 160 O45 28264 160 O45 28424 160 O10E 28424 0 O11E 28264 160 5 2 AE r R25E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2).[6]" A4 r R25E O157 6824 672 O45 6824 672 O45 8664 672 O11D 8664 0 O11D 6824 0 5 2 AE r R198 A4 r R198 O1B6 13304 32 O45 13304 32 O45 19704 32 OEE 19704 0 O133 13304 32 5 2 AE r R25F "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/12(counterUp1B2).[6]" A4 r R25F O103 23384 288 O45 23384 288 O45 23944 288 O10A 23944 0 O10A 23384 0 5 2 AE r R260 "A4" A4 r R260 O11F 24104 288 O45 24104 288 O45 25464 288 O121 25464 288 O10A 24104 0 5 2 AE r R19A A4 r R19A O14C 6504 32 O45 6504 32 O45 10744 32 OEE 10744 0 O133 6504 32 7 2 AE r R261 "Din3" A4 r R261 O199 14104 1184 O45 25144 1184 O45 14104 1184 O45 26824 1184 O127 26824 0 O127 25144 0 OEB 14104 1184 5 2 AE r RC9 A4 r RC9 O125 24184 416 O45 24184 416 O45 26904 416 OEC 26904 416 O10C 24184 0 5 2 AE r RCA A4 r RCA O1B7 A9 7312 32 A6 AA 0 12584 480 O45 12584 480 O45 19864 480 OF7 19864 480 O13D 12584 0 5 2 AE r R19B A4 r R19B O140 26504 608 O45 26504 608 O45 27384 608 O100 27384 608 O119 26504 0 5 2 AE r RCB A4 r RCB O143 26344 1248 O45 26344 1248 O45 27544 1248 O159 27544 1248 OFD 26344 0 3 2 AE r R262 "PDout35" A4 r R262 OFB 12904 1824 O10A 12984 1824 O121 12904 0 5 2 AE r RCC A4 r RCC O1B8 A9 6912 32 A6 AA 0 14984 1952 O45 14984 1952 O45 21864 1952 O10E 21864 1952 O11E 14984 0 5 2 AE r RCE A4 r RCE O15C 27304 1056 O45 27304 1056 O45 27544 1056 OF1 27544 0 OF1 27304 1056 5 2 AE r RCD A4 r RCD O15B 24344 1440 O45 24344 1440 O45 26824 1440 O11D 26824 1440 O128 24344 0 5 2 AE r R263 "PDout16" A4 r R263 O126 13064 800 O45 13064 800 O45 18904 800 O22 18904 0 O114 13064 800 5 2 AE r RCF A4 r RCF O111 11304 608 O45 11304 608 O45 12584 608 O100 12584 608 O119 11304 0 5 2 AE r R19D A4 r R19D O103 10424 608 O45 10424 608 O45 10984 608 O100 10984 608 O119 10424 0 5 2 AE r RD0 A4 r RD0 O184 27224 160 O45 27224 160 O45 27384 160 O10E 27384 0 O11E 27224 160 5 2 AE r R264 "/0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)*1.[5]" A4 r R264 O141 17544 608 O45 17544 608 O45 19784 608 O100 19784 608 O119 17544 0 5 2 AE r R19F A4 r R19F O12E 18424 96 O45 18424 96 O45 19144 96 O13A 19144 96 OFA 18424 0 5 2 AE r R1A1 A4 r R1A1 O18C 29144 160 O45 29144 160 O45 29944 160 O10E 29944 0 O11E 29144 160 5 2 AE r R1A0 A4 r R1A0 O12C 21624 224 O45 21624 224 O45 30104 224 O12F 30104 224 O107 21624 0 3 2 AE r R265 "/0(MiChip)/2(MemCtlA)/21(fsm2i)*1.[4]" A4 r R265 O135 18184 36 O136 18184 0 O1B2 18184 36 5 2 AE r RD5 A4 r RD5 O1B9 A9 18672 32 A6 AA 0 6264 1248 O45 6264 1248 O45 24904 1248 OFD 24904 0 O159 6264 1248 7 2 AE r R266 "Dout8" A4 r R266 O1BA A9 14832 32 A6 AA 0 10104 1312 O45 22584 1312 O45 10104 1312 O45 24904 1312 O22 24904 1312 O114 22584 0 O114 10104 0 5 2 AE r RD8 A4 r RD8 O145 14584 1376 O45 14584 1376 O45 18664 1376 O130 18664 1376 OFE 14584 0 5 2 AE r RDA A4 r RDA O157 8744 352 O45 8744 352 O45 10584 352 O14D 10584 352 OF4 8744 0 5 2 AE r RDB A4 r RDB O17B 28424 352 O45 28424 352 O45 29464 352 OF4 29464 0 O14D 28424 352 5 2 AE r R267 "/0(MiChip)/0(RasDecode)*1.RasN[4]" A4 r R267 O143 17304 1568 O45 17304 1568 O45 18504 1568 O102 18504 1568 OF0 17304 0 5 2 AE r R268 "/0(MiChip)/0(RasDecode)*1.RasN[5]" A4 r R268 OFF 14424 416 O45 14424 416 O45 16424 416 O10C 16424 0 O10C 14424 0 5 2 AE r R1A3 A4 r R1A3 O15B 28024 32 O45 28024 32 O45 30504 32 OEE 30504 0 O133 28024 32 5 2 AE r RE0 A4 r RE0 O198 8504 1632 O45 8504 1632 O45 14824 1632 O13D 14824 1632 OF7 8504 0 5 2 AE r R269 "/0(MiChip)/5(DataMux)/12(ParGen)/13(XOR4)*1.[3]" A4 r R269 O11C 4984 352 O45 4984 352 O45 6104 352 O14D 6104 352 OF4 4984 0 5 2 AE r R1A5 A4 r R1A5 O103 4024 32 O45 4024 32 O45 4584 32 O133 4584 32 OEE 4024 0 5 2 AE r RE3 A4 r RE3 O1B7 2264 224 O45 2264 224 O45 9544 224 O12F 9544 224 O107 2264 0 5 2 AE r R1A6 A4 r R1A6 O11F 6264 1184 O45 6264 1184 O45 7624 1184 OEB 7624 1184 O127 6264 0 5 2 AE r R26A "Dout13" A4 r R26A O1BB A9 4912 32 A6 AA 0 13384 224 O45 13384 224 O45 18264 224 O12F 18264 224 O107 13384 0 5 2 AE r R26B "/0(MiChip)/5(DataMux)/12(ParGen)/13(XOR4)*1.[5]" A4 r R26B O146 5064 480 O45 5064 480 O45 9224 480 O13D 9224 0 O13D 5064 0 5 2 AE r R1AA A4 r R1AA O184 20984 1568 O45 20984 1568 O45 21144 1568 OF0 21144 0 O102 20984 1568 5 2 AE r R1A9 A4 r R1A9 O10B 14904 1632 O45 14904 1632 O45 16584 1632 O13D 16584 1632 OF7 14904 0 5 2 AE r R1AB A4 r R1AB O11F 13064 736 O45 13064 736 O45 14424 736 OFE 14424 736 O130 13064 0 5 2 AE r RE5 A4 r RE5 O197 17384 1632 O45 17384 1632 O45 18984 1632 OF7 18984 0 O13D 17384 1632 5 2 AE r R26C "/0(MiChip)/2(MemCtlA)*1.C4B" A4 r R26C O132 18024 416 O45 18024 416 O45 23944 416 OEC 23944 416 O10C 18024 0 5 2 AE r R26D "/0(MiChip)/2(MemCtlA)*1.[71]" A4 r R26D O1BC A9 3872 32 A6 AA 0 10344 416 O45 10344 416 O45 14184 416 O10C 14184 0 O10C 10344 0 3 2 AE r R26E "/0(MiChip)/4(RefreshCtr)*1.[1][0]" A4 r R26E O135 23304 36 O136 23304 0 O1B2 23304 36 5 2 AE r R26F "/0(MiChip)/2(MemCtlA)*1.[52]" A4 r R26F O11C 22904 864 O45 22904 864 O45 24024 864 OFD 24024 864 O159 22904 0 10 2 AE r R270 "/0(MiChip)/2(MemCtlA)*1.WR" A4 r R270 OF2 15384 160 O45 15784 160 O45 15384 160 O45 15864 160 O11E 15864 160 O11E 15384 160 O10E 15384 0 O10E 15784 0 O11E 15384 160 O10E 15384 0 3 2 AE r R271 "/0(MiChip)/4(RefreshCtr)*1.[1][1]" A4 r R271 O135 29224 36 O136 29224 0 O1B2 29224 36 5 2 AE r R1AE A4 r R1AE O17B 9464 480 O45 9464 480 O45 10504 480 OF7 10504 480 O13D 9464 0 7 2 AE r R272 "/0(MiChip)/4(RefreshCtr)*1.Output[1]" A4 r R272 O15F 25544 96 O45 26104 96 O45 25544 96 O45 29144 96 OFA 29144 0 OFA 26104 0 O13A 25544 96 5 2 AE r R1B0 A4 r R1B0 O15C 12424 736 O45 12424 736 O45 12664 736 OFE 12664 736 O130 12424 0 5 2 AE r R1B1 A4 r R1B1 O101 18904 928 O45 18904 928 O45 21064 928 OEB 21064 0 O127 18904 928 5 2 AE r R273 "/0(MiChip)/5(DataMux)*1.[15][4]" A4 r R273 OFF 8904 736 O45 8904 736 O45 10904 736 OFE 10904 736 O130 8904 0 5 2 AE r R1B2 A4 r R1B2 O18C 8824 672 O45 8824 672 O45 9624 672 O128 9624 672 O11D 8824 0 5 2 AE r R274 "/0(MiChip)/4(RefreshCtr)*1.[1][7]" A4 r R274 O10B 6744 352 O45 6744 352 O45 8424 352 OF4 8424 0 OF4 6744 0 5 2 AE r R275 "XIRQ0" A4 r R275 O118 28344 288 O45 28344 288 O45 28664 288 O121 28664 288 O10A 28344 0 5 2 AE r R276 "/0(MiChip)/4(RefreshCtr)*1.[8][11]" A4 r R276 O1BD A9 4832 32 A6 AA 0 7224 800 O45 7224 800 O45 12024 800 O22 12024 0 O22 7224 0 5 2 AE r R277 "/0(MiChip)/2(MemCtlA)*1.[26]" A4 r R277 O18C 22184 288 O45 22184 288 O45 22984 288 O10A 22984 0 O121 22184 288 7 2 AE r R278 "/0(MiChip)*1.HoldIgnore" A4 r R278 O125 24584 992 O45 25944 992 O45 24584 992 O45 27304 992 OF6 27304 0 OF6 25944 0 O105 24584 992 5 2 AE r R279 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[2]" A4 r R279 O106 9624 224 O45 9624 224 O45 13144 224 O107 13144 0 O107 9624 0 5 2 AE r REE A4 r REE O139 24584 928 O45 24584 928 O45 25224 928 O127 25224 928 OEB 24584 0 5 2 AE r R1B4 A4 r R1B4 O15C 2984 96 O45 2984 96 O45 3224 96 OFA 3224 0 O13A 2984 96 5 2 AE r R27A "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)*1.[3]" A4 r R27A O118 5864 32 O45 5864 32 O45 6184 32 O133 6184 32 OEE 5864 0 5 2 AE r R27B "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[3]" A4 r R27B O144 6024 608 O45 6024 608 O45 9944 608 O100 9944 608 O119 6024 0 5 2 AE r RF0 A4 r RF0 O115 18024 736 O45 18024 736 O45 22504 736 O130 22504 0 OFE 18024 736 5 2 AE r RF1 A4 r RF1 OF5 17224 352 O45 17224 352 O45 18744 352 OF4 18744 0 O14D 17224 352 5 2 AE r RF2 A4 r RF2 O106 7864 1184 O45 7864 1184 O45 11384 1184 O127 11384 0 OEB 7864 1184 5 2 AE r RF4 A4 r RF4 O14B 25704 288 O45 25704 288 O45 26664 288 O121 26664 288 O10A 25704 0 5 2 AE r RF7 A4 r RF7 O103 4104 352 O45 4104 352 O45 4664 352 O14D 4664 352 OF4 4104 0 5 2 AE r RB A4 r RB O198 14664 1440 O45 14664 1440 O45 20984 1440 O128 20984 0 O11D 14664 1440 5 2 AE r R27C "/0(MiChip)/3(AddrMux)*1.[14]" A4 r R27C O180 14904 1824 O45 14904 1824 O45 15304 1824 O121 15304 0 O10A 14904 1824 5 2 AE r RF8 A4 r RF8 O115 17944 160 O45 17944 160 O45 22424 160 O10E 22424 0 O11E 17944 160 5 2 AE r RFC A4 r RFC O1BE A9 18272 32 A6 AA 0 8344 544 O45 8344 544 O45 26584 544 OF0 26584 544 O102 8344 0 5 2 AE r R27D "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[12]" A4 r R27D O161 24264 864 O45 24264 864 O45 26024 864 O159 26024 0 OFD 24264 864 5 2 AE r RFE A4 r RFE O10B 14504 736 O45 14504 736 O45 16184 736 OFE 16184 736 O130 14504 0 5 2 AE r RFF A4 r RFF O184 27464 160 O45 27464 160 O45 27624 160 O11E 27624 160 O10E 27464 0 3 2 AE r R27E "/0(MiChip)/5(DataMux)/12(ParGen)*1.[10]" A4 r R27E OFB 5384 32 OEE 5464 0 OEE 5384 0 5 2 AE r R101 A4 r R101 O103 18824 352 O45 18824 352 O45 19384 352 OF4 19384 0 O14D 18824 352 3 2 AE r R27F "/0(MiChip)/4(RefreshCtr)*1.[3][11]" A4 r R27F OFB 12024 864 O159 12104 0 OFD 12024 864 5 2 AE r R102 A4 r R102 O1BF A9 2832 32 A6 AA 0 14024 96 O45 14024 96 O45 16824 96 O13A 16824 96 OFA 14024 0 5 2 AE r R280 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]" A4 r R280 O1C0 A9 11072 32 A6 AA 0 7304 928 O45 7304 928 O45 18344 928 OEB 18344 0 O127 7304 928 5 2 AE r R103 A4 r R103 O132 22584 1376 O45 22584 1376 O45 28504 1376 OFE 28504 0 O130 22584 1376 5 2 AE r R1BC A4 r R1BC O12E 12504 32 O45 12504 32 O45 13224 32 O133 13224 32 OEE 12504 0 3 2 AE r R281 "/0(MiChip)/4(RefreshCtr)*1.[3][2]" A4 r R281 OFB 22104 32 OEE 22184 0 OEE 22104 0 5 2 AE r R282 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]" A4 r R282 O1C0 7464 1056 O45 7464 1056 O45 18504 1056 OF1 18504 0 OF1 7464 1056 5 2 AE r R283 "/0(MiChip)/7(StatusReg)*1.[14][0]" A4 r R283 O103 10664 352 O45 10664 352 O45 11224 352 OF4 11224 0 O14D 10664 352 3 2 AE r R284 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[4]" A4 r R284 O135 20824 36 O136 20824 0 O1B2 20824 36 5 2 AE r R1BF A4 r R1BF O11F 16904 96 O45 16904 96 O45 18264 96 OFA 18264 0 O13A 16904 96 5 2 AE r R106 A4 r R106 O15C 20344 96 O45 20344 96 O45 20584 96 OFA 20584 0 O13A 20344 96 5 2 AE r R107 A4 r R107 O103 26424 352 O45 26424 352 O45 26984 352 O14D 26984 352 OF4 26424 0 3 2 AE r R1C0 A4 r R1C0 OFB 24664 1568 OF0 24744 0 O102 24664 1568 5 2 AE r R1C2 A4 r R1C2 O12E 12664 608 O45 12664 608 O45 13384 608 O100 13384 608 O119 12664 0 5 2 AE r R1C3 A4 r R1C3 O129 6344 1760 O45 6344 1760 O45 9704 1760 OF4 9704 1760 O14D 6344 0 5 2 AE r R285 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[16]" A4 r R285 O18E 16424 736 O45 16424 736 O45 17864 736 O130 17864 0 OFE 16424 736 3 2 AE r R1C6 A4 r R1C6 OFB 26184 416 OEC 26264 416 O10C 26184 0 5 2 AE r R1C7 A4 r R1C7 O12E 22664 736 O45 22664 736 O45 23384 736 OFE 23384 736 O130 22664 0 5 2 AE r R108 A4 r R108 O1BD 13864 672 O45 13864 672 O45 18664 672 O11D 18664 0 O128 13864 672 7 2 AE r R286 "/0(MiChip)/7(StatusReg)*1.[14][4]" A4 r R286 O1C1 A9 20752 32 A6 AA 0 9704 1696 O45 17304 1696 O45 9704 1696 O45 30424 1696 OEC 30424 0 O10C 17304 1696 OEC 9704 0 3 2 AE r R287 "/0(MiChip)/4(RefreshCtr)*1.[3][7]" A4 r R287 O135 25784 36 O136 25784 0 O1B2 25784 36 5 2 AE r R288 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21).[2]" A4 r R288 OF2 18824 224 O45 18824 224 O45 19304 224 O12F 19304 224 O107 18824 0 3 2 AE r R289 "PDin20" A4 r R289 O1C2 A9 2696 24 A6 AA 0 0 100 O45 2664 96 O124 2664 0 5 2 AE r R28A "/0(MiChip)/4(RefreshCtr)*1.[3][14]" A4 r R28A O17B 20184 32 O45 20184 32 O45 21224 32 OEE 21224 0 OEE 20184 0 5 2 AE r R10A A4 r R10A O1AC 7304 864 O45 7304 864 O45 20504 864 OFD 20504 864 O159 7304 0 5 2 AE r R10B A4 r R10B O118 24504 736 O45 24504 736 O45 24824 736 O130 24824 0 OFE 24504 736 5 2 AE r R10D A4 r R10D O184 29704 288 O45 29704 288 O45 29864 288 O121 29864 288 O10A 29704 0 3 2 AE r R28B "PDin22" A4 r R28B O1C3 A9 3496 24 A6 AA 0 0 36 O45 3464 32 O136 3464 0 5 2 AE r R1CB A4 r R1CB O146 20904 96 O45 20904 96 O45 25064 96 O13A 25064 96 OFA 20904 0 5 2 AE r R1CA A4 r R1CA O103 12184 352 O45 12184 352 O45 12744 352 O14D 12744 352 OF4 12184 0 5 2 AE r R1CC A4 r R1CC O12E 16984 160 O45 16984 160 O45 17704 160 O11E 17704 160 O10E 16984 0 5 2 AE r R112 A4 r R112 O17B 28504 1440 O45 28504 1440 O45 29544 1440 O128 29544 0 O11D 28504 1440 5 2 AE r R1CE A4 r R1CE O180 17384 416 O45 17384 416 O45 17784 416 OEC 17784 416 O10C 17384 0 5 2 AE r R1D0 A4 r R1D0 O17B 7624 1120 O45 7624 1120 O45 8664 1120 OF6 8664 1120 O105 7624 0 5 2 AE r R1D1 A4 r R1D1 O157 14824 1568 O45 14824 1568 O45 16664 1568 O102 16664 1568 OF0 14824 0 3 2 AE r R28C "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2).[2]" A4 r R28C O188 28744 32 O133 29064 32 OEE 28744 0 0 0 7744 0 1 AE r R28D "MIInnerChan4" O1C4 A2 0 0 32800 864 132 O1C5 A2 0 0 2160 832 2 O1C6 A2 0 0 2160 80 1 O1C7 A9 2160 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 2160 80 R2 1059061760 0 0 0 0 0 0 0 O1C8 A2 0 0 2160 80 1 O1C7 0 0 0 2 A4 r RC AE r RC 0 0 2160 80 R2 1059061760 0 0 0 0 752 0 0 0 0 2160 832 R28E "MIInnerLeft4" 1031153506 0 1 0 0 0 0 0 O24 2160 0 0 2 AE r R28F "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 2960 0 0 2 AE r R290 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 3760 0 0 2 AE r R291 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 4544 0 0 2 AE r R292 "Dout11-4" A1A a A1A O18 4624 0 0 2 AE r R293 "/0(MiChip)/4(RefreshCtr)*1.[8][9]-4" A1A a A1A O24 4720 0 0 2 AE r R294 "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1*1*1*1*1*1" A1A a A1A O86 5520 0 0 2 AE r R295 "/0(MiChip)/5(DataMux)/7(DecoderS)/7(Inv)" A1A a A1A ODD 5680 0 0 2 AE r R296 "/0(MiChip)/5(DataMux)/12(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 6144 0 0 2 AE r R297 "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)*1.[3]-4" A1A a A1A O24 6240 0 0 2 AE r R298 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1" A1A a A1A O86 7040 0 0 2 AE r R299 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OA4 7200 0 0 2 AE r R29A "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 7584 0 0 2 AE r R29B "Dout12-4" A1A a A1A O86 7680 0 0 2 AE r R29C "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/1(Inv)*1*1*1*1*1*1" A1A a A1A O24 7840 0 0 2 AE r R29D "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 8624 0 0 2 AE r R29E "/0(MiChip)/4(RefreshCtr)*1.[3].Cin-4" A1A a A1A O24 8720 0 0 2 AE r R29F "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 9504 0 0 2 AE r R2A0 "PDWPout-4" A1A a A1A O18 9584 0 0 2 AE r R2A1 "/0(MiChip)/5(DataMux)*1.[15][5]-4" A1A a A1A O18 9664 0 0 2 AE r R2A2 "/0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)*1.[5]-4" A1A a A1A O18 9744 0 0 2 AE r R2A3 "/0(MiChip)/5(DataMux)*1.[28][6]-4" A1A a A1A O86 9840 0 0 2 AE r R2A4 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv3" A1A a A1A OA4 10000 0 0 2 AE r R2A5 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 10384 0 0 2 AE r R2A6 "/0(MiChip)/5(DataMux)*1.[28][7]-4" A1A a A1A O18 10464 0 0 2 AE r R2A7 "/0(MiChip)/5(DataMux)*1.[15][2]-4" A1A a A1A O18 10544 0 0 2 AE r R2A8 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[6][1]-4" A1A a A1A O18 10624 0 0 2 AE r R2A9 "/0(MiChip)/7(StatusReg)*1.[14][0]-4" A1A a A1A O86 10720 0 0 2 AE r R2AA "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/0(Inv)*1*1*1*1" A1A a A1A O18 10864 0 0 2 AE r R2AB "/0(MiChip)/5(DataMux)*1.[15][4]-4" A1A a A1A OCA 10960 0 0 2 AE r R2AC "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)/1(NormalizedNor2)/0(Nor2)" A1A a A1A O24 11200 0 0 2 AE r R2AD "/0(MiChip)/2(MemCtlA)/43(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 12000 0 0 2 AE r R2AE "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv11" A1A a A1A OAF 12160 0 0 2 AE r R2AF "/0(MiChip)/2(MemCtlA)/43(fsm1)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O86 12400 0 0 2 AE r R2B0 "/0(MiChip)/2(MemCtlA)/43(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 12544 0 0 2 AE r R2B1 "Din6-4" A1A a A1A O18 12624 0 0 2 AE r R2B2 "/0(MiChip)/5(DataMux)*1.[15][3]-4" A1A a A1A O18 12704 0 0 2 AE r R2B3 "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nAd[0]-4" A1A a A1A O86 12800 0 0 2 AE r R2B4 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 12944 0 0 2 AE r R2B5 "PDout35-4" A1A a A1A O18 13024 0 0 2 AE r R2B6 "PDout16-4" A1A a A1A OA4 13120 0 0 2 AE r R2B7 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 13504 0 0 2 AE r R2B8 "/0(MiChip)/0(RasDecode)/8(DecoderS)*1.nAd[1]-4" A1A a A1A O86 13600 0 0 2 AE r R2B9 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 13744 0 0 2 AE r R2BA "/0(MiChip)*1.RASX-4" A1A a A1A O18 13824 0 0 2 AE r R2BB "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)*1.nAd[0]-4" A1A a A1A OA4 13920 0 0 2 AE r R2BC "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O168 14320 0 0 2 AE r R2BD "/0(MiChip)/2(MemCtlA)/10(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 14624 0 0 2 AE r R2BE "Gnd-4" A1A a A1A O18 14704 0 0 2 AE r R2BF "Dout6-4" A1A a A1A O18 14784 0 0 2 AE r R2C0 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncount-4" A1A a A1A O18 14864 0 0 2 AE r R2C1 "/0(MiChip)/3(AddrMux)*1.[14]-4" A1A a A1A O18 14944 0 0 2 AE r R2C2 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][4]-4" A1A a A1A O18 15024 0 0 2 AE r R2C3 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][4]-4" A1A a A1A O86 15120 0 0 2 AE r R2C4 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv8" A1A a A1A O18 15264 0 0 2 AE r R2C5 "PA10-4" A1A a A1A OCA 15360 0 0 2 AE r R2C6 "/0(MiChip)/2(MemCtlA)/8(ffrs1)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O98 15600 0 0 2 AE r R2C7 "/0(MiChip)/2(MemCtlA)/8(ffrs1)/1(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A OCA 15920 0 0 2 AE r R2C8 "/0(MiChip)/5(DataMux)/7(DecoderS)/3(NormalizedNor2)/0(Nor2)" A1A a A1A OCA 16160 0 0 2 AE r R2C9 "/0(MiChip)/2(MemCtlA)/6(ffrs1)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 16384 0 0 2 AE r R2CA "/0(MiChip)/5(DataMux)/12(ParGen)*1.[16]-4" A1A a A1A O18 16464 0 0 2 AE r R2CB "/0(MiChip)/2(MemCtlA)*1.PadEnb-4" A1A a A1A O18 16544 0 0 2 AE r R2CC "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv).nEnable-4" A1A a A1A O18 16624 0 0 2 AE r R2CD "/0(MiChip)*1.LdStatus[1]-4" A1A a A1A O86 16720 0 0 2 AE r R2CE "/0(MiChip)/6(AddrCtl)/14(Decoder)/8(Inv)" A1A a A1A O18 16864 0 0 2 AE r R2CF "/0(MiChip)/5(DataMux)*1.[11][0]-4" A1A a A1A OCA 16960 0 0 2 AE r R2D0 "/0(MiChip)/5(DataMux)/7(DecoderS)/1(NormalizedNor2)/0(Nor2)" A1A a A1A O18 17184 0 0 2 AE r R2D1 "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)*1.[5]-4" A1A a A1A O18 17264 0 0 2 AE r R2D2 "/0(MiChip)/7(StatusReg)*1.[14][4]-4" A1A a A1A O98 17360 0 0 2 AE r R2D3 "/0(MiChip)/2(MemCtlA)/6(ffrs1)/1(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O18 17664 0 0 2 AE r R2D4 "RPadEnb-4" A1A a A1A O18 17744 0 0 2 AE r R2D5 "Dout0-4" A1A a A1A OCE 17840 0 0 2 AE r R2D6 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver13" A1A a A1A O18 18144 0 0 2 AE r R2D7 "/0(MiChip)/2(MemCtlA)/21(fsm2i)*1.[4]-4" A1A a A1A O18 18224 0 0 2 AE r R2D8 "Dout13-4" A1A a A1A O86 18320 0 0 2 AE r R2D9 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv13" A1A a A1A OC4 18480 0 0 2 AE r R2DA "/0(MiChip)/0(RasDecode)/4(A21o2i)*1" A1A a A1A O18 18784 0 0 2 AE r R2DB "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[9][1]-4" A1A a A1A O18 18864 0 0 2 AE r R2DC "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two-4" A1A a A1A OA4 18960 0 0 2 AE r R2DD "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 19360 0 0 2 AE r R2DE "/0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 19824 0 0 2 AE r R2DF "Din4-4" A1A a A1A ODD 19920 0 0 2 AE r R2E0 "/0(MiChip)/5(DataMux)/12(ParGen)//0(MiChip)/5(DataMux)/0(ParGen)/2(Xor2)*1*1" A1A a A1A OA4 20400 0 0 2 AE r R2E1 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/12(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 20784 0 0 2 AE r R2E2 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[4]-4" A1A a A1A O18 20864 0 0 2 AE r R2E3 "Dout5-4" A1A a A1A O18 20944 0 0 2 AE r R2E4 "/0(MiChip)/2(MemCtlA)*1.RefCy-4" A1A a A1A O24 21040 0 0 2 AE r R2E5 "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple8//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple7//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 21824 0 0 2 AE r R2E6 "Dout7-4" A1A a A1A O171 21920 0 0 2 AE r R2E7 "/0(MiChip)/2(MemCtlA)/2(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O18 22224 0 0 2 AE r R2E8 "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nEnable-4" A1A a A1A O18 22304 0 0 2 AE r R2E9 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[5]-4" A1A a A1A O86 22400 0 0 2 AE r R2EA "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv12" A1A a A1A O24 22560 0 0 2 AE r R2EB "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/12(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 23344 0 0 2 AE r R2EC "/0(MiChip)/3(AddrMux)*1.In1[1]-4" A1A a A1A OCE 23440 0 0 2 AE r R2ED "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver5" A1A a A1A O98 23760 0 0 2 AE r R2EE "/0(MiChip)/2(MemCtlA)/4(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O86 24080 0 0 2 AE r R2EF "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv2" A1A a A1A O18 24224 0 0 2 AE r R2F0 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[12]-4" A1A a A1A OAF 24320 0 0 2 AE r R2F1 "/0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 24544 0 0 2 AE r R2F2 "/0(MiChip)*1.HoldIgnore-4" A1A a A1A OCE 24640 0 0 2 AE r R2F3 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver7" A1A a A1A O18 24944 0 0 2 AE r R2F4 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[2]-4" A1A a A1A O18 25024 0 0 2 AE r R2F5 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21).[2]-4" A1A a A1A O98 25120 0 0 2 AE r R2F6 "/0(MiChip)/2(MemCtlA)/11(ffrs1)/1(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O18 25424 0 0 2 AE r R2F7 "A4-4" A1A a A1A OAF 25520 0 0 2 AE r R2F8 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/6/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 25744 0 0 2 AE r R2F9 "/0(MiChip)/4(RefreshCtr)*1.[3][7]-4" A1A a A1A OCE 25840 0 0 2 AE r R2FA "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver3" A1A a A1A O18 26144 0 0 2 AE r R2FB "PDout0-4" A1A a A1A O18 26224 0 0 2 AE r R2FC "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][0]-4" A1A a A1A OCA 26320 0 0 2 AE r R2FD "/0(MiChip)/2(MemCtlA)/11(ffrs1)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A OAF 26560 0 0 2 AE r R2FE "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/3/6/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 26784 0 0 2 AE r R2FF "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)*1.decoded[1]-4" A1A a A1A O18 26864 0 0 2 AE r R300 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)*1.decoded[0]-4" A1A a A1A O18 26944 0 0 2 AE r R301 "/0(MiChip)/3(AddrMux)*1.In1[0]-4" A1A a A1A O86 27040 0 0 2 AE r R302 "/0(MiChip)/2(MemCtlA)/54(mux21)/0(NormalizedMux21)/0(Inv)*1" A1A a A1A O98 27200 0 0 2 AE r R303 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/2(Or6)/1(NormalizedNor3)/0(Nor3)" A1A a A1A O18 27504 0 0 2 AE r R304 "Din5-4" A1A a A1A O18 27584 0 0 2 AE r R305 "/0(MiChip)/3(AddrMux)*1.In0[0]-4" A1A a A1A OCE 27680 0 0 2 AE r R306 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver14" A1A a A1A O18 27984 0 0 2 AE r R307 "Din15-4" A1A a A1A O86 28080 0 0 2 AE r R308 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv13" A1A a A1A O18 28224 0 0 2 AE r R309 "/0(MiChip)/3(AddrMux)*1.In1[9]-4" A1A a A1A OCE 28320 0 0 2 AE r R30A "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver13" A1A a A1A O18 28624 0 0 2 AE r R30B "XIRQ0-4" A1A a A1A OA4 28720 0 0 2 AE r R30C "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 29104 0 0 2 AE r R30D "Din8-4" A1A a A1A OB6 29200 0 0 2 AE r R30E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 29680 0 0 2 AE r R30F "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv11" A1A a A1A O24 29840 0 0 2 AE r R310 "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O1C9 A2 0 0 2160 832 2 O1CA A2 0 0 2160 80 1 O1C7 0 0 0 2 A4 r RB AE r RB 0 0 2160 80 R2 1059061760 0 0 0 0 0 0 0 O1CB A2 0 0 2160 80 1 O1C7 0 0 0 2 A4 r RC AE r RC 0 0 2160 80 R2 1059061760 0 0 0 0 752 0 0 0 0 2160 832 R311 "MIInnerRight4" 1031153506 0 1 0 30640 0 0 0 0 0 32800 832 R312 "MIInnerIntRow4" 1030556027 0 0 0 0 9888 0 1 AE r R313 "Row4" O1CC A29 0 0 32800 2848 175 0 0 32800 2848 5 2 AE r R314 "Dout1" A4 r R314 OED 17944 1888 O45 17944 1888 O45 27944 1888 O12F 27944 0 OEB 17944 1888 7 2 AE r RA1 A4 r RA1 O183 20584 352 O45 24424 352 O45 20584 352 O45 28904 352 OF4 28904 0 O10D 24424 352 OF4 20584 0 5 2 AE r RA4 A4 r RA4 O184 14904 2080 O45 14904 2080 O45 15064 2080 O133 15064 0 O130 14904 2080 5 2 AE r RA5 A4 r RA5 O103 13224 1952 O45 13224 1952 O45 13784 1952 O11E 13784 0 O159 13224 1952 5 2 AE r R188 A4 r R188 O19D 18984 1504 O45 18984 1504 O45 25144 1504 O114 25144 1504 O100 18984 0 5 2 AE r R189 A4 r R189 O192 22344 2336 O45 22344 2336 O45 29144 2336 O13D 29144 2336 O109 22344 0 5 2 AE r R315 "PDout20" A4 r R315 O142 6424 1056 O45 6424 1056 O45 12904 1056 OF1 12904 0 O14D 6424 1056 9 2 AE r R316 "Dout2" A4 r R316 O1CD A9 11312 32 A6 AA 0 18104 416 O45 23704 416 O45 18104 416 O45 28584 416 O45 29384 416 O112 29384 416 O10C 23704 0 O10C 28584 0 O10C 18104 0 5 2 AE r R18A A4 r R18A O184 14824 2272 O45 14824 2272 O45 14984 2272 OF3 14984 0 O102 14824 2272 5 2 AE r R317 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21).[2]" A4 r R317 O184 13464 544 O45 13464 544 O45 13624 544 O102 13624 0 O102 13464 0 5 2 AE r R318 "/0(MiChip)/5(DataMux)*1.[28][2]" A4 r R318 O111 22824 864 O45 22824 864 O45 24104 864 O159 24104 0 O11E 22824 864 5 2 AE r R319 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/12(counterUp1B2).[2]" A4 r R319 O117 20744 800 O45 20744 800 O45 22824 800 O22 22824 0 O22 20744 0 5 2 AE r R31A "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21).[2]" A4 r R31A OF2 7064 96 O45 7064 96 O45 7544 96 OFA 7544 0 OFA 7064 0 5 2 AE r R24E A4 r R24E O18F 23144 1120 O45 23144 1120 O45 26424 1120 O105 26424 0 OEC 23144 1120 5 2 AE r R31B "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[11]" A4 r R31B O1CE A9 8432 32 A6 AA 0 12104 672 O45 12104 672 O45 20504 672 O13E 20504 672 O11D 12104 0 7 2 AE r R31C "/0(MiChip)/3(AddrMux)*1.In1[6]" A4 r R31C O134 28264 2400 O45 29704 2400 O45 28264 2400 O45 31384 2400 O10C 31384 2400 O112 29704 0 O10C 28264 2400 5 2 AE r RB0 A4 r RB0 O1AE 15304 736 O45 15304 736 O45 27624 736 O133 27624 736 O130 15304 0 5 2 AE r R31D "/0(MiChip)/6(AddrCtl)*1.[13]" A4 r R31D O103 16184 544 O45 16184 544 O45 16744 544 O102 16744 0 OF3 16184 544 5 2 AE r R31E "/0(MiChip)/5(DataMux)*1.[28][5]" A4 r R31E O15F 19384 2784 O45 19384 2784 O45 22984 2784 OEE 22984 2784 O1CF A9 32 2816 A6 AB 0 19384 0 5 2 AE r R251 A4 r R251 O18C 24984 2144 O45 24984 2144 O45 25784 2144 O11D 25784 2144 O13E 24984 0 5 2 AE r R252 A4 r R252 O18F 9784 864 O45 9784 864 O45 13064 864 O11E 13064 864 O159 9784 0 5 2 AE r R18F A4 r R18F O1D0 A9 5392 32 A6 AA 0 20744 2272 O45 20744 2272 O45 26104 2272 OF3 26104 0 O102 20744 2272 5 2 AE r R255 A4 r R255 O1D1 A9 6592 32 A6 AA 0 3864 480 O45 3864 480 O45 10424 480 O13D 10424 0 O109 3864 480 5 2 AE r RB6 A4 r RB6 OF2 26184 1056 O45 26184 1056 O45 26664 1056 O14D 26664 1056 OF1 26184 0 5 2 AE r RBA A4 r RBA O131 10104 2080 O45 10104 2080 O45 13544 2080 O133 13544 0 O130 10104 2080 5 2 AE r RBD A4 r RBD O162 20904 1696 O45 20904 1696 O45 26424 1696 O105 26424 1696 OEC 20904 0 3 2 AE r R31F "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[12]" A4 r R31F O135 22504 2788 O1D2 A9 32 2812 A6 AB 0 22504 0 O136 22504 2788 5 2 AE r R320 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[13]" A4 r R320 O103 17864 544 O45 17864 544 O45 18424 544 O102 18424 0 O102 17864 0 5 2 AE r R321 "/0(MiChip)/3(AddrMux)*1.In1[8]" A4 r R321 O15C 27864 2016 O45 27864 2016 O45 28104 2016 O13A 28104 0 O22 27864 2016 5 2 AE r RBE A4 r RBE O12A 20344 928 O45 20344 928 O45 22264 928 OEB 22264 0 O12F 20344 928 5 2 AE r R322 "PDout5" A4 r R322 O15C 6904 288 O45 6904 288 O45 7144 288 O10A 7144 0 O116 6904 288 5 2 AE r R323 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[13]" A4 r R323 O184 28184 608 O45 28184 608 O45 28344 608 O119 28344 0 O119 28184 0 5 2 AE r RC0 A4 r RC0 O134 8104 1952 O45 8104 1952 O45 11224 1952 O159 11224 1952 O11E 8104 0 5 2 AE r R25C A4 r R25C OF5 16504 2080 O45 16504 2080 O45 18024 2080 O130 18024 2080 O133 16504 0 5 2 AE r R196 A4 r R196 O10B 10184 1504 O45 10184 1504 O45 11864 1504 O114 11864 1504 O100 10184 0 7 2 AE r RC2 A4 r RC2 O1D3 A9 9312 32 A6 AA 0 14744 2144 O45 21064 2144 O45 14744 2144 O45 24024 2144 O11D 24024 2144 O11D 21064 2144 O13E 14744 0 5 2 AE r RC4 A4 r RC4 O18C 27464 2144 O45 27464 2144 O45 28264 2144 O13E 28264 0 O11D 27464 2144 5 2 AE r R198 A4 r R198 O14B 12344 544 O45 12344 544 O45 13304 544 O102 13304 0 OF3 12344 544 5 2 AE r R324 "Din2" A4 r R324 O1D4 A9 12912 32 A6 AA 0 7384 2720 O45 7384 2720 O45 20264 2720 OFA 20264 2720 O1D5 A9 32 2752 A6 AB 0 7384 0 5 2 AE r R260 A4 r R260 O134 25464 480 O45 25464 480 O45 28584 480 O109 28584 480 O13D 25464 0 5 2 AE r R261 A4 r R261 O197 14104 544 O45 14104 544 O45 15704 544 OF3 15704 544 O102 14104 0 7 2 AE r R19A A4 r R19A O162 6104 2784 O45 6504 2784 O45 6104 2784 O45 11624 2784 OEE 11624 2784 O1CF 6504 0 OEE 6104 2784 9 2 AE r RC9 A4 r RC9 O1D6 A9 4992 32 A6 AA 0 23224 2400 O45 26904 2400 O45 23224 2400 O45 27784 2400 O45 28184 2400 O10C 28184 2400 O112 26904 0 O10C 27784 2400 O10C 23224 2400 7 2 AE r RCA A4 r RCA O1C0 19864 160 O45 21544 160 O45 19864 160 O45 30904 160 O1D7 A9 32 2688 A6 AB 0 30904 160 O1D7 21544 160 O10E 19864 0 3 2 AE r R19B A4 r R19B O1D8 A9 5416 24 A6 AA 0 27384 36 O45 27384 32 O136 27384 0 5 2 AE r R262 A4 r R262 O157 11144 1760 O45 11144 1760 O45 12984 1760 O14D 12984 0 OF1 11144 1760 5 2 AE r RCB A4 r RCB O14B 27544 2272 O45 27544 2272 O45 28504 2272 O102 28504 2272 OF3 27544 0 9 2 AE r RCC A4 r RCC O150 18744 2464 O45 21864 2464 O45 18744 2464 O45 28904 2464 O45 29704 2464 OF4 29704 2464 O10D 21864 0 OF4 28904 2464 OF4 18744 2464 9 2 AE r RCD A4 r RCD O1D9 A9 5072 32 A6 AA 0 23304 2208 O45 26824 2208 O45 23304 2208 O45 27944 2208 O45 28344 2208 O119 28344 2208 O11B 26824 0 O119 27944 2208 O119 23304 2208 3 2 AE r RCE A4 r RCE O1DA A9 5496 24 A6 AA 0 27304 2660 O45 27304 2656 O1DB A9 32 2684 A6 AB 0 27304 0 5 2 AE r R263 A4 r R263 O1DC A9 7552 32 A6 AA 0 5544 736 O45 5544 736 O45 13064 736 O130 13064 0 O133 5544 736 5 2 AE r R325 "/0(MiChip)/2(MemCtlA)*1.WrHCy" A4 r R325 O101 12184 2144 O45 12184 2144 O45 14344 2144 O13E 14344 0 O11D 12184 2144 5 2 AE r RCF A4 r RCF O198 12584 2784 O45 12584 2784 O45 18904 2784 OEE 18904 2784 O1CF 12584 0 3 2 AE r RD0 A4 r RD0 O1DD A9 5576 24 A6 AA 0 27224 2724 O45 27224 2720 O1DE A9 32 2748 A6 AB 0 27224 0 7 2 AE r R19F A4 r R19F O1DF A9 13656 24 A6 AA 0 19144 100 O45 21304 96 O45 19144 96 O45 21144 96 O1DE 21144 100 O124 21304 0 O124 19144 0 5 2 AE r R1A1 A4 r R1A1 O18E 29144 224 O45 29144 224 O45 30584 224 O10F 30584 224 O107 29144 0 5 2 AE r R1A0 A4 r R1A0 O18D 5224 2528 O45 5224 2528 O45 30104 2528 O116 30104 0 O10A 5224 2528 11 2 AE r R326 "/0(MiChip)/5(DataMux)/6(DataLatchMux)*1.[4]" A4 r R326 O1E0 A9 8192 32 A6 AA 0 17784 1760 O45 18584 1760 O45 22184 1760 O45 17784 1760 O45 20904 1760 O45 25944 1760 O14D 25944 0 OF1 18584 1760 OF1 20904 1760 OF1 22184 1760 OF1 17784 1760 5 2 AE r R265 A4 r R265 O14C 18184 224 O45 18184 224 O45 22424 224 O10F 22424 224 O107 18184 0 5 2 AE r RD5 A4 r RD5 O1E1 A9 24432 32 A6 AA 0 6264 2592 O45 6264 2592 O45 30664 2592 O107 30664 2592 O10F 6264 0 6 2 AE r R266 A4 r R266 O1E2 A9 7896 24 A6 AA 0 24904 2788 O45 24904 2784 O136 24904 2788 O1D2 24904 0 O136 24904 2788 O1D2 24904 0 7 2 AE r R327 "/0(MiChip)/5(DataMux)/7(DecoderS)*1.nAd[0]" A4 r R327 O1E3 A9 11392 32 A6 AA 0 5624 2336 O45 12984 2336 O45 5624 2336 O45 16984 2336 O109 16984 0 O13D 12984 2336 O109 5624 0 5 2 AE r RDA A4 r RDA O12E 9864 608 O45 9864 608 O45 10584 608 O119 10584 0 O11B 9864 608 7 2 AE r RDB A4 r RDB O126 22584 928 O45 24744 928 O45 22584 928 O45 28424 928 OEB 28424 0 OEB 24744 0 O12F 22584 928 5 2 AE r R328 "/0(MiChip)/5(DataMux)*1.[23][6]" A4 r R328 O1B6 2904 2656 O45 2904 2656 O45 9304 2656 O10E 9304 2656 O1D7 2904 0 5 2 AE r R1A3 A4 r R1A3 O179 19144 608 O45 19144 608 O45 28024 608 O119 28024 0 O11B 19144 608 5 2 AE r R329 "/0(MiChip)/2(MemCtlA)*1.[20]" A4 r R329 O15C 15544 160 O45 15544 160 O45 15784 160 O10E 15784 0 O10E 15544 0 5 2 AE r R32A "PDout38" A4 r R32A O180 13704 2080 O45 13704 2080 O45 14104 2080 O130 14104 2080 O133 13704 0 5 2 AE r R32B "/0(MiChip)/2(MemCtlA)/54(mux21)/0(NormalizedMux21)*1.[2]" A4 r R32B O118 27064 2272 O45 27064 2272 O45 27384 2272 O102 27384 2272 OF3 27064 0 7 2 AE r R32C "/0(MiChip)/5(DataMux)/9(DataLatchMux)*1.[4]" A4 r R32C O11C 23544 2784 O45 23864 2784 O45 23544 2784 O45 24664 2784 OEE 24664 2784 OEE 23864 2784 O1CF 23544 0 5 2 AE r RE0 A4 r RE0 O103 14264 416 O45 14264 416 O45 14824 416 O10C 14824 0 O112 14264 416 5 2 AE r R32D "/0(MiChip)/2(MemCtlA)*1.[1]" A4 r R32D O11C 11144 544 O45 11144 544 O45 12264 544 O102 12264 0 O102 11144 0 5 2 AE r R1A5 A4 r R1A5 O180 4584 2784 O45 4584 2784 O45 4984 2784 OEE 4984 2784 O1CF 4584 0 5 2 AE r R1A6 A4 r R1A6 OFF 7624 2144 O45 7624 2144 O45 9624 2144 O11D 9624 2144 O13E 7624 0 5 2 AE r RE3 A4 r RE3 OF8 9544 2272 O45 9544 2272 O45 14744 2272 O102 14744 2272 OF3 9544 0 5 2 AE r R26A A4 r R26A O14F 18264 1248 O45 18264 1248 O45 26024 1248 OF0 26024 1248 OFD 18264 0 9 2 AE r R32E "/0(MiChip)/2(MemCtlA)*1.C4A" A4 r R32E O1E4 A9 13312 32 A6 AA 0 11864 1184 O45 18824 1184 O45 11864 1184 O45 23864 1184 O45 25144 1184 O127 25144 0 OF7 18824 1184 O127 23864 0 O127 11864 0 5 2 AE r R32F "/0(MiChip)/2(MemCtlA)*1.C0" A4 r R32F O157 16264 608 O45 16264 608 O45 18104 608 O11B 18104 608 O119 16264 0 7 2 AE r R330 "/0(MiChip)/2(MemCtlA)*1.aHold" A4 r R330 O14B 25384 1184 O45 26184 1184 O45 25384 1184 O45 26344 1184 O127 26344 0 OF7 26184 1184 O127 25384 0 5 2 AE r R1AA A4 r R1AA O14C 20984 672 O45 20984 672 O45 25224 672 O13E 25224 672 O11D 20984 0 5 2 AE r R331 "/0(MiChip)/5(DataMux)*1.Select.I-B" A4 r R331 O148 17144 2336 O45 17144 2336 O45 21784 2336 O13D 21784 2336 O109 17144 0 7 2 AE r R1A9 A4 r R1A9 O1E5 A9 14752 32 A6 AA 0 9544 2656 O45 16584 2656 O45 9544 2656 O45 24264 2656 O10E 24264 2656 O1D7 16584 0 O10E 9544 2656 5 2 AE r R1AB A4 r R1AB O101 12264 608 O45 12264 608 O45 14424 608 O119 14424 0 O11B 12264 608 7 2 AE r R332 "/0(MiChip)/2(MemCtlA)*1.C2" A4 r R332 OEA 5384 2400 O45 8824 2400 O45 5384 2400 O45 21944 2400 O112 21944 0 O10C 8824 2400 O112 5384 0 9 2 AE r RE5 A4 r RE5 O1E0 15624 1440 O45 17384 1440 O45 15624 1440 O45 20024 1440 O45 23784 1440 O128 23784 0 O128 17384 0 OFE 20024 1440 O128 15624 0 5 2 AE r R26C A4 r R26C O15C 23704 992 O45 23704 992 O45 23944 992 OF6 23944 0 O121 23704 992 5 2 AE r R333 "/0(MiChip)/2(MemCtlA)*1.[5]" A4 r R333 O1E6 A9 15312 32 A6 AA 0 9144 32 O45 9144 32 O45 24424 32 OEE 24424 0 O1CF 9144 32 5 2 AE r R334 "/0(MiChip)/2(MemCtlA)*1.[61]" A4 r R334 O17A 22024 2016 O45 22024 2016 O45 25704 2016 O22 25704 2016 O13A 22024 0 5 2 AE r R335 "/0(MiChip)/4(RefreshCtr)*1.Output[0]" A4 r R335 O13B 23224 800 O45 23224 800 O45 25624 800 O22 25624 0 O22 23224 0 5 2 AE r R336 "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nEnable" A4 r R336 O17B 11064 2144 O45 11064 2144 O45 12104 2144 O11D 12104 2144 O13E 11064 0 5 2 AE r R337 "/0(MiChip)/5(DataMux)/7(DecoderS)*1.nnAd[0]" A4 r R337 O139 15304 2272 O45 15304 2272 O45 15944 2272 OF3 15944 0 O102 15304 2272 5 2 AE r R338 "/0(MiChip)/2(MemCtlA)*1.[7]" A4 r R338 O143 16344 160 O45 16344 160 O45 17544 160 O10E 17544 0 O10E 16344 0 3 2 AE r R339 "PDin1" A4 r R339 O1E7 A9 4056 24 A6 AA 0 0 100 O45 4024 96 O124 4024 0 7 2 AE r R33A "/0(MiChip)/5(DataMux)/7(DecoderS)*1.nnAd[1]" A4 r R33A O17B 16024 224 O45 16104 224 O45 16024 224 O45 17064 224 O107 17064 0 O10F 16104 224 O107 16024 0 5 2 AE r R33B "/0(MiChip)/2(MemCtlA)*1.[14]" A4 r R33B O143 25304 672 O45 25304 672 O45 26504 672 O11D 26504 0 O11D 25304 0 5 2 AE r R1AE A4 r R1AE O111 9224 160 O45 9224 160 O45 10504 160 O10E 10504 0 O1D7 9224 160 5 2 AE r R1B0 A4 r R1B0 O11F 11304 160 O45 11304 160 O45 12664 160 O10E 12664 0 O1D7 11304 160 3 2 AE r R1B1 A4 r R1B1 OFB 18904 2720 OFA 18984 2720 O1D5 18904 0 5 2 AE r R33C "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)*1.[4]" A4 r R33C O18F 1704 2592 O45 1704 2592 O45 4984 2592 O10F 4984 0 O107 1704 2592 9 2 AE r R33D "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]" A4 r R33D O183 10744 1312 O45 14024 1312 O45 10744 1312 O45 18264 1312 O45 19064 1312 O114 19064 0 O114 14024 0 O100 18264 1312 O114 10744 0 3 2 AE r R273 A4 r R273 O15E 10904 2784 OEE 11064 2784 O1CF 10904 0 9 2 AE r R33E "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]" A4 r R33E O1CE 10824 928 O45 14184 928 O45 10824 928 O45 18184 928 O45 19224 928 OEB 19224 0 OEB 14184 0 O12F 18184 928 OEB 10824 0 5 2 AE r R1B2 A4 r R1B2 O1BF 9624 1248 O45 9624 1248 O45 12424 1248 OF0 12424 1248 OFD 9624 0 5 2 AE r R33F "/0(MiChip)/2(MemCtlA)*1.[54]" A4 r R33F O140 14584 160 O45 14584 160 O45 15464 160 O10E 15464 0 O10E 14584 0 7 2 AE r R340 "/0(MiChip)/5(DataMux)*1.[15][6]" A4 r R340 O1E4 5784 1696 O45 13144 1696 O45 5784 1696 O45 19064 1696 O105 19064 1696 OEC 13144 0 OEC 5784 0 7 2 AE r R341 "/0(MiChip)/5(DataMux)*1.[15][7]" A4 r R341 O104 4024 224 O45 5704 224 O45 4024 224 O45 10024 224 O107 10024 0 O107 5704 0 O10F 4024 224 5 2 AE r R275 A4 r R275 O118 28664 480 O45 28664 480 O45 28984 480 O109 28984 480 O13D 28664 0 5 2 AE r R278 A4 r R278 OF5 24584 2656 O45 24584 2656 O45 26104 2656 O10E 26104 2656 O1D7 24584 0 5 2 AE r R342 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21).[2]" A4 r R342 O18E 12824 160 O45 12824 160 O45 14264 160 O10E 14264 0 O10E 12824 0 5 2 AE r R343 "/0(MiChip)/4(RefreshCtr)*1.[8][4]" A4 r R343 OEF 8504 352 O45 8504 352 O45 20424 352 OF4 20424 0 OF4 8504 0 11 2 AE r REE A4 r REE O1E8 A9 12832 32 A6 AA 0 12424 480 O45 15704 480 O45 20424 480 O45 12424 480 O45 17464 480 O45 25224 480 O13D 25224 0 O13D 15704 0 O13D 17464 0 O109 20424 480 O13D 12424 0 5 2 AE r R344 "/0(MiChip)/4(RefreshCtr)*1.[8][5]" A4 r R344 O118 28744 224 O45 28744 224 O45 29064 224 O10F 29064 224 O107 28744 0 23 2 AE r R1B4 A4 r R1B4 O1E9 A9 12432 32 A6 AA 0 904 1824 O45 2184 1824 O45 2984 1824 O45 3784 1824 O45 7304 1824 O45 10344 1824 O45 904 1824 O45 8744 1824 O45 4184 1824 O45 3144 1824 O45 2264 1824 O45 13304 1824 OF6 13304 1824 O121 2184 0 OF6 2264 1824 O121 2984 0 OF6 3144 1824 O121 3784 0 OF6 4184 1824 OF6 7304 1824 O121 8744 0 OF6 10344 1824 OF6 904 1824 5 2 AE r R27A A4 r R27A O117 4104 96 O45 4104 96 O45 6184 96 OFA 6184 0 O1D5 4104 96 3 2 AE r R345 "PDin6" A4 r R345 O1EA A9 3256 24 A6 AA 0 0 2788 O45 3224 2784 O1D2 3224 0 11 2 AE r RF0 A4 r RF0 O1EB A9 10832 32 A6 AA 0 18024 1952 O45 20664 1952 O45 27864 1952 O45 18024 1952 O45 25944 1952 O45 28824 1952 O159 28824 1952 O159 20664 1952 O159 25944 1952 O11E 27864 0 O11E 18024 0 5 2 AE r RF1 A4 r RF1 O118 17224 224 O45 17224 224 O45 17544 224 O10F 17544 224 O107 17224 0 5 2 AE r RF2 A4 r RF2 O1EC A9 21952 32 A6 AA 0 7864 288 O45 7864 288 O45 29784 288 O116 29784 288 O10A 7864 0 5 2 AE r R346 "/0(MiChip)/2(MemCtlA)/43(fsm1)/0(ffR)*1.[4]" A4 r R346 O140 11464 480 O45 11464 480 O45 12344 480 O13D 12344 0 O13D 11464 0 5 2 AE r R347 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21).[2]" A4 r R347 O184 10184 1760 O45 10184 1760 O45 10344 1760 O14D 10344 0 OF1 10184 1760 3 2 AE r R348 "PDin7" A4 r R348 O1ED A9 9016 24 A6 AA 0 0 36 O45 8984 32 O136 8984 0 5 2 AE r RF7 A4 r RF7 O197 3064 2528 O45 3064 2528 O45 4664 2528 O116 4664 0 O10A 3064 2528 5 2 AE r R27C A4 r R27C O12E 14184 1952 O45 14184 1952 O45 14904 1952 O11E 14904 0 O159 14184 1952 7 2 AE r RB A4 r RB O189 6824 2208 O45 8424 2208 O45 6824 2208 O45 14664 2208 O11B 14664 0 O119 8424 2208 O119 6824 2208 11 2 AE r RF8 A4 r RF8 O1EB 17944 1824 O45 20584 1824 O45 27784 1824 O45 17944 1824 O45 25864 1824 O45 28744 1824 OF6 28744 1824 OF6 20584 1824 OF6 25864 1824 O121 27784 0 O121 17944 0 7 2 AE r R349 "/0(MiChip)*1.RASn[1]" A4 r R349 O147 6984 544 O45 9864 544 O45 6984 544 O45 10024 544 OF3 10024 544 O102 9864 0 O102 6984 0 5 2 AE r R34A "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[2]" A4 r R34A O11C 24184 864 O45 24184 864 O45 25304 864 O11E 25304 864 O159 24184 0 7 2 AE r RFE A4 r RFE O13B 16184 96 O45 17624 96 O45 16184 96 O45 18584 96 OFA 18584 0 OFA 17624 0 OFA 16184 0 5 2 AE r RFF A4 r RFF O17B 26584 672 O45 26584 672 O45 27624 672 O11D 27624 0 O13E 26584 672 5 2 AE r R27D A4 r R27D O184 24104 2144 O45 24104 2144 O45 24264 2144 O13E 24264 0 O11D 24104 2144 5 2 AE r R34B "/0(MiChip)/2(MemCtlA)/43(fsm1)/0(ffR)*1.[7]" A4 r R34B O118 12184 1952 O45 12184 1952 O45 12504 1952 O11E 12504 0 O11E 12184 0 7 2 AE r R34C "/0(MiChip)*1.[27][1]" A4 r R34C O1EE A9 18912 32 A6 AA 0 4744 1376 O45 11224 1376 O45 4744 1376 O45 23624 1376 O128 23624 1376 OFE 11224 0 OFE 4744 0 11 2 AE r R34D "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv).nEnable" A4 r R34D O1E0 17864 1056 O45 18664 1056 O45 22264 1056 O45 17864 1056 O45 20984 1056 O45 26024 1056 OF1 26024 0 O14D 18664 1056 O14D 20984 1056 O14D 22264 1056 O14D 17864 1056 5 2 AE r R101 A4 r R101 O11F 18824 544 O45 18824 544 O45 20184 544 OF3 20184 544 O102 18824 0 5 2 AE r R280 A4 r R280 O1EF A9 13952 32 A6 AA 0 7304 992 O45 7304 992 O45 21224 992 O121 21224 992 OF6 7304 0 5 2 AE r R34E "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/2(Or6).One" A4 r R34E OF2 26984 2016 O45 26984 2016 O45 27464 2016 O13A 27464 0 O22 26984 2016 5 2 AE r R103 A4 r R103 O126 16744 864 O45 16744 864 O45 22584 864 O159 22584 0 O11E 16744 864 9 2 AE r R1BC A4 r R1BC O189 7784 1888 O45 10104 1888 O45 7784 1888 O45 13224 1888 O45 15624 1888 OEB 15624 1888 O12F 10104 0 O12F 13224 0 O12F 7784 0 7 2 AE r R34F "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv).nEnable" A4 r R34F O11C 23624 1312 O45 23944 1312 O45 23624 1312 O45 24744 1312 O100 24744 1312 O100 23944 1312 O114 23624 0 5 2 AE r R282 A4 r R282 O1F0 A9 13872 32 A6 AA 0 7464 2016 O45 7464 2016 O45 21304 2016 O22 21304 2016 O13A 7464 0 5 2 AE r R283 A4 r R283 O14B 9704 2144 O45 9704 2144 O45 10664 2144 O13E 10664 0 O11D 9704 2144 5 2 AE r R1BF A4 r R1BF O18E 16904 2464 O45 16904 2464 O45 18344 2464 OF4 18344 2464 O10D 16904 0 5 2 AE r R284 A4 r R284 O1F1 A9 3792 32 A6 AA 0 20824 2720 O45 20824 2720 O45 24584 2720 OFA 24584 2720 O1D5 20824 0 5 2 AE r R107 A4 r R107 O11F 25624 864 O45 25624 864 O45 26984 864 O159 26984 0 O11E 25624 864 5 2 AE r R350 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)*1.nInput[3]" A4 r R350 O18C 25064 1632 O45 25064 1632 O45 25864 1632 OF7 25864 0 O127 25064 1632 5 2 AE r R351 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][0]" A4 r R351 O17B 25704 800 O45 25704 800 O45 26744 800 O13A 26744 800 O22 25704 0 5 2 AE r R352 "/0(MiChip)/4(RefreshCtr)*1.[3][4]" A4 r R352 O148 3944 160 O45 3944 160 O45 8584 160 O10E 8584 0 O1D7 3944 160 5 2 AE r R353 "/0(MiChip)/5(DataMux)*1.[11][1]" A4 r R353 O1F2 A9 10912 32 A6 AA 0 4504 2464 O45 4504 2464 O45 15384 2464 OF4 15384 2464 O10D 4504 0 7 2 AE r R1C2 A4 r R1C2 O162 10264 224 O45 13384 224 O45 10264 224 O45 15784 224 O10F 15784 224 O107 13384 0 O107 10264 0 5 2 AE r R1C3 A4 r R1C3 O15D 9704 1568 O45 9704 1568 O45 12904 1568 OFD 12904 1568 OF0 9704 0 5 2 AE r R285 A4 r R285 OF2 15944 2464 O45 15944 2464 O45 16424 2464 O10D 16424 0 OF4 15944 2464 5 2 AE r R354 "/0(MiChip)/4(RefreshCtr)*1.[3][13]" A4 r R354 O18E 18344 160 O45 18344 160 O45 19784 160 O1D7 19784 160 O10E 18344 0 5 2 AE r R355 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[5]" A4 r R355 O180 23064 2784 O45 23064 2784 O45 23464 2784 O1CF 23464 0 OEE 23064 2784 5 2 AE r R1C7 A4 r R1C7 OF2 22904 992 O45 22904 992 O45 23384 992 OF6 23384 0 O121 22904 992 5 2 AE r R1C6 A4 r R1C6 O18C 25464 2720 O45 25464 2720 O45 26264 2720 O1D5 26264 0 OFA 25464 2720 5 2 AE r R108 A4 r R108 O1BB 8984 416 O45 8984 416 O45 13864 416 O10C 13864 0 O112 8984 416 5 2 AE r R286 A4 r R286 O157 15464 416 O45 15464 416 O45 17304 416 O10C 17304 0 O112 15464 416 7 2 AE r R356 "/0(MiChip)/5(DataMux)*1.Select[0]" A4 r R356 O1CE 7704 96 O45 11384 96 O45 7704 96 O45 16104 96 OFA 16104 0 O1D5 11384 96 OFA 7704 0 5 2 AE r R287 A4 r R287 O12E 25784 2016 O45 25784 2016 O45 26504 2016 O22 26504 2016 O13A 25784 0 3 2 AE r R357 "PDin14" A4 r R357 O1F3 A9 2456 24 A6 AA 0 0 2724 O45 2424 2720 O1DE 2424 0 7 2 AE r R358 "/0(MiChip)/7(StatusReg)*1.[14][5]" A4 r R358 O1AD 15064 2208 O45 15144 2208 O45 15064 2208 O45 21784 2208 O11B 21784 0 O11B 15144 0 O119 15064 2208 7 2 AE r R10A A4 r R10A O183 20504 544 O45 24504 544 O45 20504 544 O45 28824 544 O102 28824 0 OF3 24504 544 O102 20504 0 5 2 AE r R359 "/0(MiChip)/5(DataMux)*1.[11][5]" A4 r R359 O14C 2984 2720 O45 2984 2720 O45 7224 2720 O1D5 7224 0 OFA 2984 2720 7 2 AE r R10D A4 r R10D O14E 21064 2080 O45 23384 2080 O45 21064 2080 O45 29864 2080 O133 29864 0 O130 23384 2080 O133 21064 0 7 2 AE r R35A "/0(MiChip)/5(DataMux)*1.[11][6]" A4 r R35A O1F4 A9 16352 32 A6 AA 0 3704 800 O45 17624 800 O45 3704 800 O45 20024 800 O22 20024 0 O13A 17624 800 O22 3704 0 5 2 AE r R1CB A4 r R1CB O129 25064 992 O45 25064 992 O45 28424 992 O121 28424 992 OF6 25064 0 5 2 AE r R35B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/11(counterUp1B2).[1]" A4 r R35B O139 28984 352 O45 28984 352 O45 29624 352 OF4 29624 0 OF4 28984 0 5 2 AE r R1CA A4 r R1CA O180 12744 1952 O45 12744 1952 O45 13144 1952 O159 13144 1952 O11E 12744 0 7 2 AE r R112 A4 r R112 O126 22664 224 O45 24824 224 O45 22664 224 O45 28504 224 O107 28504 0 O107 24824 0 O10F 22664 224 7 2 AE r R35C "/0(MiChip)/5(DataMux)*1.[11][7]" A4 r R35C O1F5 A9 10512 32 A6 AA 0 9464 1120 O45 19224 1120 O45 9464 1120 O45 19944 1120 O105 19944 0 OEC 19224 1120 O105 9464 0 5 2 AE r R1CC A4 r R1CC O13B 17704 2272 O45 17704 2272 O45 20104 2272 O102 20104 2272 OF3 17704 0 5 2 AE r R1CE A4 r R1CE O152 17784 1568 O45 17784 1568 O45 25384 1568 OFD 25384 1568 OF0 17784 0 5 2 AE r R1D0 A4 r R1D0 O103 8104 2272 O45 8104 2272 O45 8664 2272 OF3 8664 0 O102 8104 2272 7 2 AE r R1D1 A4 r R1D1 O1E5 9464 1632 O45 16664 1632 O45 9464 1632 O45 24184 1632 O127 24184 1632 OF7 16664 0 O127 9464 1632 5 2 AE r R35D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][3]" A4 r R35D O143 25544 32 O45 25544 32 O45 26744 32 OEE 26744 0 O1CF 25544 32 0 0 10720 0 1 AE r R35E "MIInnerChan5" O1F6 A2 0 0 32800 856 148 O1F7 A2 0 0 880 832 2 O1F8 A2 0 0 880 80 1 O1F9 A9 880 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 880 80 R2 1059061760 0 0 0 0 0 0 0 O1FA A2 0 0 880 80 1 O1F9 0 0 0 2 A4 r RC AE r RC 0 0 880 80 R2 1059061760 0 0 0 0 752 0 0 0 0 880 832 R35F "MIInnerLeft5" 1031153506 0 1 0 0 0 0 0 O24 880 0 0 2 AE r R360 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 1664 0 0 2 AE r R361 "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)*1.[4]-5" A1A a A1A ODD 1760 0 0 2 AE r R362 "/0(MiChip)/5(DataMux)/0(ParGen)/2(Xor2)*1" A1A a A1A O24 2240 0 0 2 AE r R363 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 3024 0 0 2 AE r R364 "/0(MiChip)/4(RefreshCtr)*1.[8][9]-5" A1A a A1A O24 3120 0 0 2 AE r R365 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 3904 0 0 2 AE r R366 "/0(MiChip)/4(RefreshCtr)*1.[3][4]-5" A1A a A1A O18 3984 0 0 2 AE r R367 "/0(MiChip)/5(DataMux)*1.[15][7]-5" A1A a A1A O18 4064 0 0 2 AE r R368 "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)*1.[3]-5" A1A a A1A O24 4160 0 0 2 AE r R369 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 4944 0 0 2 AE r R36A "Dout11-5" A1A a A1A OA4 5040 0 0 2 AE r R36B "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 5440 0 0 2 AE r R36C "/0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1" A1A a A1A OA4 5920 0 0 2 AE r R36D "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 6320 0 0 2 AE r R36E "/0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1" A1A a A1A ODD 6800 0 0 2 AE r R36F "/0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1" A1A a A1A O24 7280 0 0 2 AE r R370 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 8064 0 0 2 AE r R371 "/0(MiChip)/4(RefreshCtr)*1.[3].Cin-5" A1A a A1A O86 8160 0 0 2 AE r R372 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv4" A1A a A1A ODD 8320 0 0 2 AE r R373 "/0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1" A1A a A1A O86 8800 0 0 2 AE r R374 "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)/4(Inv)" A1A a A1A OCA 8960 0 0 2 AE r R375 "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 9184 0 0 2 AE r R376 "/0(MiChip)/5(DataMux)*1.[15][2]-5" A1A a A1A O18 9264 0 0 2 AE r R377 "/0(MiChip)/5(DataMux)*1.[23][6]-5" A1A a A1A OCE 9360 0 0 2 AE r R378 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver3" A1A a A1A O86 9680 0 0 2 AE r R379 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv3" A1A a A1A O86 9840 0 0 2 AE r R37A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0(counterCLP2NL)/1(Inv)*1" A1A a A1A O86 10000 0 0 2 AE r R37B "/0(MiChip)/0(RasDecode)/8(DecoderS)/11(Inv)" A1A a A1A O86 10160 0 0 2 AE r R37C "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 10320 0 0 2 AE r R37D "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 11104 0 0 2 AE r R37E "PDout35-5" A1A a A1A O18 11184 0 0 2 AE r R37F "Din11-5" A1A a A1A O18 11264 0 0 2 AE r R380 "/0(MiChip)/5(DataMux)*1.[15][3]-5" A1A a A1A O18 11344 0 0 2 AE r R381 "/0(MiChip)/5(DataMux)*1.Select[0]-5" A1A a A1A OA4 11440 0 0 2 AE r R382 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 11824 0 0 2 AE r R383 "Din0-5" A1A a A1A O86 11920 0 0 2 AE r R384 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/1(Inv)" A1A a A1A O18 12064 0 0 2 AE r R385 "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nEnable-5" A1A a A1A O18 12144 0 0 2 AE r R386 "/0(MiChip)/2(MemCtlA)*1.WrHCy-5" A1A a A1A O18 12224 0 0 2 AE r R387 "/0(MiChip)/2(MemCtlA)*1.C1-5" A1A a A1A O18 12304 0 0 2 AE r R388 "Din1-5" A1A a A1A O18 12384 0 0 2 AE r R389 "/0(MiChip)/5(DataMux)*1.[15][5]-5" A1A a A1A ODD 12480 0 0 2 AE r R38A "/0(MiChip)/5(DataMux)/12(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 12944 0 0 2 AE r R38B "/0(MiChip)/5(DataMux)/7(DecoderS)*1.nAd[0]-5" A1A a A1A O18 13024 0 0 2 AE r R38C "/0(MiChip)/5(DataMux)*1.[28][6]-5" A1A a A1A O18 13104 0 0 2 AE r R38D "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nAd[0]-5" A1A a A1A O18 13184 0 0 2 AE r R38E "/0(MiChip)*1.RASX-5" A1A a A1A O24 13280 0 0 2 AE r R38F "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 14064 0 0 2 AE r R390 "PDout38-5" A1A a A1A O18 14144 0 0 2 AE r R391 "/0(MiChip)/3(AddrMux)*1.[14]-5" A1A a A1A O18 14224 0 0 2 AE r R392 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncount-5" A1A a A1A ODD 14320 0 0 2 AE r R393 "/0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1" A1A a A1A O18 14784 0 0 2 AE r R394 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][4]-5" A1A a A1A O18 14864 0 0 2 AE r R395 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][4]-5" A1A a A1A O168 14960 0 0 2 AE r R396 "/0(MiChip)/7(StatusReg)/6(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 15264 0 0 2 AE r R397 "/0(MiChip)/5(DataMux)/7(DecoderS)*1.nnAd[0]-5" A1A a A1A O18 15344 0 0 2 AE r R398 "/0(MiChip)/5(DataMux)*1.[11][1]-5" A1A a A1A O18 15424 0 0 2 AE r R399 "/0(MiChip)/7(StatusReg)*1.[14][4]-5" A1A a A1A OA4 15520 0 0 2 AE r R39A "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 15904 0 0 2 AE r R39B "/0(MiChip)/5(DataMux)/12(ParGen)*1.[16]-5" A1A a A1A O86 16000 0 0 2 AE r R39C "/0(MiChip)/5(DataMux)/7(DecoderS)/4(Inv)" A1A a A1A O18 16144 0 0 2 AE r R39D "/0(MiChip)/6(AddrCtl)*1.[13]-5" A1A a A1A ODD 16240 0 0 2 AE r R39E "/0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 16720 0 0 2 AE r R39F "/0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1*1*1" A1A a A1A O18 17504 0 0 2 AE r R3A0 "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)*1.[5]-5" A1A a A1A O18 17584 0 0 2 AE r R3A1 "/0(MiChip)/5(DataMux)*1.[11][6]-5" A1A a A1A OCE 17680 0 0 2 AE r R3A2 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver6" A1A a A1A O18 17984 0 0 2 AE r R3A3 "/0(MiChip)/2(MemCtlA)*1.PadEnb-5" A1A a A1A O18 18064 0 0 2 AE r R3A4 "/0(MiChip)/2(MemCtlA)*1.C0-5" A1A a A1A O18 18144 0 0 2 AE r R3A5 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]-5" A1A a A1A O18 18224 0 0 2 AE r R3A6 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]-5" A1A a A1A O86 18320 0 0 2 AE r R3A7 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv0" A1A a A1A OCE 18480 0 0 2 AE r R3A8 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver0" A1A a A1A O18 18784 0 0 2 AE r R3A9 "/0(MiChip)/2(MemCtlA)*1.C4A-5" A1A a A1A O18 18864 0 0 2 AE r R3AA "Din6-5" A1A a A1A O18 18944 0 0 2 AE r R3AB "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two-5" A1A a A1A O18 19024 0 0 2 AE r R3AC "/0(MiChip)/5(DataMux)*1.[15][6]-5" A1A a A1A O18 19104 0 0 2 AE r R3AD "Din15-5" A1A a A1A O18 19184 0 0 2 AE r R3AE "/0(MiChip)/5(DataMux)*1.[11][7]-5" A1A a A1A ODD 19280 0 0 2 AE r R3AF "/0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1" A1A a A1A O18 19744 0 0 2 AE r R3B0 "/0(MiChip)/4(RefreshCtr)*1.[3][13]-5" A1A a A1A O86 19840 0 0 2 AE r R3B1 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv4" A1A a A1A O18 19984 0 0 2 AE r R3B2 "/0(MiChip)/2(MemCtlA)*1.C3-5" A1A a A1A O18 20064 0 0 2 AE r R3B3 "RPadEnb-5" A1A a A1A O18 20144 0 0 2 AE r R3B4 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[9][1]-5" A1A a A1A O18 20224 0 0 2 AE r R3B5 "Din2-5" A1A a A1A O18 20304 0 0 2 AE r R3B6 "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nEnable-5" A1A a A1A O18 20384 0 0 2 AE r R3B7 "LPRESET-5" A1A a A1A OCE 20480 0 0 2 AE r R3B8 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver11" A1A a A1A OCE 20800 0 0 2 AE r R3B9 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver1" A1A a A1A O18 21104 0 0 2 AE r R3BA "Din7-5" A1A a A1A O86 21200 0 0 2 AE r R3BB "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/0(Inv)*1*1" A1A a A1A OA4 21360 0 0 2 AE r R3BC "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O171 21760 0 0 2 AE r R3BD "/0(MiChip)/5(DataMux)/5(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A OCE 22080 0 0 2 AE r R3BE "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver4" A1A a A1A O18 22384 0 0 2 AE r R3BF "/0(MiChip)/2(MemCtlA)/21(fsm2i)*1.[4]-5" A1A a A1A OCE 22480 0 0 2 AE r R3C0 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver12" A1A a A1A O18 22784 0 0 2 AE r R3C1 "/0(MiChip)/5(DataMux)*1.[28][2]-5" A1A a A1A O18 22864 0 0 2 AE r R3C2 "/0(MiChip)/3(AddrMux)*1.In1[1]-5" A1A a A1A O86 22960 0 0 2 AE r R3C3 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv5" A1A a A1A O18 23104 0 0 2 AE r R3C4 "/0(MiChip)/2(MemCtlA)*1.S1-5" A1A a A1A O86 23200 0 0 2 AE r R3C5 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/0(Inv)*1" A1A a A1A O18 23344 0 0 2 AE r R3C6 "/0(MiChip)*1.LdStatus[0]-5" A1A a A1A O16D 23440 0 0 2 AE r R3C7 "/0(MiChip)/1(ClockGen)/0(B)/Buffer1" A1A a A1A O18 23664 0 0 2 AE r R3C8 "/0(MiChip)/2(MemCtlA)*1.C4B-5" A1A a A1A OCE 23760 0 0 2 AE r R3C9 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver1" A1A a A1A OCE 24080 0 0 2 AE r R3CA "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver12" A1A a A1A O18 24384 0 0 2 AE r R3CB "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.nLoad-5" A1A a A1A O18 24464 0 0 2 AE r R3CC "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.load-5" A1A a A1A OCE 24560 0 0 2 AE r R3CD "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver4" A1A a A1A O18 24864 0 0 2 AE r R3CE "Dout8-5" A1A a A1A O86 24960 0 0 2 AE r R3CF "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv3" A1A a A1A O18 25104 0 0 2 AE r R3D0 "/0(MiChip)/5(DataMux)*1.[28][0]-5" A1A a A1A O18 25184 0 0 2 AE r R3D1 "/0(MiChip)/2(MemCtlA)*1.RefCy-5" A1A a A1A O18 25264 0 0 2 AE r R3D2 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[2]-5" A1A a A1A O18 25344 0 0 2 AE r R3D3 "Dout0-5" A1A a A1A O18 25424 0 0 2 AE r R3D4 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][0]-5" A1A a A1A O18 25504 0 0 2 AE r R3D5 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][3]-5" A1A a A1A O18 25584 0 0 2 AE r R3D6 "/0(MiChip)/3(AddrMux)*1.In1[0]-5" A1A a A1A O18 25664 0 0 2 AE r R3D7 "/0(MiChip)/2(MemCtlA)*1.[61]-5" A1A a A1A OCE 25760 0 0 2 AE r R3D8 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver2" A1A a A1A O171 26080 0 0 2 AE r R3D9 "/0(MiChip)/2(MemCtlA)/0(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O18 26384 0 0 2 AE r R3DA "Dout5-5" A1A a A1A O18 26464 0 0 2 AE r R3DB "/0(MiChip)/4(RefreshCtr)*1.[3][7]-5" A1A a A1A O18 26544 0 0 2 AE r R3DC "/0(MiChip)/3(AddrMux)*1.In0[0]-5" A1A a A1A O18 26624 0 0 2 AE r R3DD "PDout0-5" A1A a A1A O18 26704 0 0 2 AE r R3DE "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][0]-5" A1A a A1A O86 26800 0 0 2 AE r R3DF "/0(MiChip)/2(MemCtlA)/54(mux21)/0(NormalizedMux21)/2(Inv)*1" A1A a A1A O18 26944 0 0 2 AE r R3E0 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/2(Or6).One-5" A1A a A1A OA4 27040 0 0 2 AE r R3E1 "/0(MiChip)/2(MemCtlA)/54(mux21)/0(NormalizedMux21)/1(A22o2i)*1" A1A a A1A O18 27424 0 0 2 AE r R3E2 "/0(MiChip)/3(AddrMux)*1.In1[9]-5" A1A a A1A O86 27520 0 0 2 AE r R3E3 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1" A1A a A1A OA4 27680 0 0 2 AE r R3E4 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1" A1A a A1A OA4 28080 0 0 2 AE r R3E5 "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1" A1A a A1A O18 28464 0 0 2 AE r R3E6 "Din5-5" A1A a A1A O18 28544 0 0 2 AE r R3E7 "A4-5" A1A a A1A OCE 28640 0 0 2 AE r R3E8 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver8" A1A a A1A O18 28944 0 0 2 AE r R3E9 "XIRQ0-5" A1A a A1A O18 29024 0 0 2 AE r R3EA "/0(MiChip)/4(RefreshCtr)*1.[8][5]-5" A1A a A1A OCE 29120 0 0 2 AE r R3EB "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver5" A1A a A1A OCE 29440 0 0 2 AE r R3EC "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver0" A1A a A1A O24 29760 0 0 2 AE r R3ED "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 30544 0 0 2 AE r R3EE "Din8-5" A1A a A1A O24 30640 0 0 2 AE r R3EF "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O16D 31440 0 0 2 AE r R3F0 "/0(MiChip)/6(AddrCtl)/7(B)//0(MiChip)/2(MemCtlA)/16(B)//0(MiChip)/2(MemCtlA)/13(B)//0(MiChip)/1(ClockGen)/2(B)//0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer1" A1A a A1A O16D 31680 0 0 2 AE r R3F1 "/0(MiChip)/6(AddrCtl)/7(B)//0(MiChip)/2(MemCtlA)/16(B)//0(MiChip)/2(MemCtlA)/13(B)//0(MiChip)/1(ClockGen)/2(B)//0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer0" A1A a A1A O1FB A2 0 0 880 832 2 O1FC A2 0 0 880 80 1 O1F9 0 0 0 2 A4 r RB AE r RB 0 0 880 80 R2 1059061760 0 0 0 0 0 0 0 O1FD A2 0 0 880 80 1 O1F9 0 0 0 2 A4 r RC AE r RC 0 0 880 80 R2 1059061760 0 0 0 0 752 0 0 0 0 880 832 R3F2 "MIInnerRight5" 1031153506 0 1 0 31920 0 0 0 0 0 32800 832 R3F3 "MIInnerIntRow5" 1030701209 0 0 0 0 13568 0 1 AE r R3F4 "Row5" O1FE A29 0 0 32800 3424 198 0 0 32800 3424 5 2 AE r R314 A4 r R314 O19A 12504 992 O45 12504 992 O45 17944 992 OF6 17944 0 O112 12504 992 5 2 AE r RA1 A4 r RA1 O11A 20104 1504 O45 20104 1504 O45 24424 1504 O100 24424 0 O12F 20104 1504 5 2 AE r R3F5 "PDin36" A4 r R3F5 O15A 7704 2464 O45 7704 2464 O45 10584 2464 O10D 10584 0 OEB 7704 2464 3 2 AE r R3F6 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[4]" A4 r R3F6 OFB 8264 992 O112 8344 992 OF6 8264 0 5 2 AE r RA4 A4 r RA4 O131 11464 1952 O45 11464 1952 O45 14904 1952 O11E 14904 0 O128 11464 1952 5 2 AE r RA5 A4 r RA5 O1F1 9464 2592 O45 9464 2592 O45 13224 2592 O10F 13224 0 O22 9464 2592 5 2 AE r R188 A4 r R188 O10B 25144 224 O45 25144 224 O45 26824 224 O1FF A9 32 3200 A6 AB 0 26824 224 O107 25144 0 3 2 AE r R315 A4 r R315 O200 A9 6456 24 A6 AA 0 0 804 O45 6424 800 O201 A9 32 828 A6 AB 0 6424 0 5 2 AE r R316 A4 r R316 OEF 17464 1696 O45 17464 1696 O45 29384 1696 OEC 29384 0 OEC 17464 1696 5 2 AE r R3F7 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[3]" A4 r R3F7 O180 9384 480 O45 9384 480 O45 9784 480 O13D 9784 0 O13D 9384 0 5 2 AE r R18A A4 r R18A O131 11384 2144 O45 11384 2144 O45 14824 2144 O13E 14824 0 OFD 11384 2144 5 2 AE r R318 A4 r R318 O145 18744 1312 O45 18744 1312 O45 22824 1312 O114 22824 0 O133 18744 1312 5 2 AE r R3F8 "PDout21" A4 r R3F8 O202 A9 6376 24 A6 AA 0 0 612 O45 4584 608 O45 6344 608 O203 A9 32 636 A6 AB 0 6344 0 O1D2 4584 612 5 2 AE r R24E A4 r R24E O17C 15464 1952 O45 15464 1952 O45 23144 1952 O11E 23144 0 O128 15464 1952 13 2 AE r R3F9 "Dout3" A4 r R3F9 O204 A9 21632 32 A6 AA 0 8584 928 O45 22344 928 O45 24344 928 O45 8584 928 O45 24824 928 O45 22744 928 O45 30184 928 O10D 30184 928 OEB 22344 0 OEB 22744 0 OEB 24344 0 OEB 24824 0 O10D 8584 928 5 2 AE r R3FA "/0(MiChip)/2(MemCtlA)*1.S3" A4 r R3FA O126 17384 160 O45 17384 160 O45 23224 160 O205 A9 32 3264 A6 AB 0 23224 160 O10E 17384 0 5 2 AE r R31D A4 r R31D O14A 12184 608 O45 12184 608 O45 16184 608 O119 16184 0 O1CF 12184 608 5 2 AE r R31E A4 r R31E O1E9 10584 2528 O45 10584 2528 O45 22984 2528 O116 22984 0 O159 10584 2528 5 2 AE r R3FB "/0(MiChip)/5(DataMux)*1.[31]" A4 r R3FB O14A 18024 2976 O45 18024 2976 O45 22024 2976 O206 A9 32 3008 A6 AB 0 22024 0 O10C 18024 2976 7 2 AE r R252 A4 r R252 O17D 8024 2080 O45 13064 2080 O45 8024 2080 O45 13144 2080 O114 13144 2080 O133 13064 0 O114 8024 2080 5 2 AE r R18F A4 r R18F O1B3 17544 1444 O45 17544 1440 O45 20744 1440 O207 A9 32 1468 A6 AB 0 20744 0 O208 A9 32 1980 A6 AB 0 17544 1444 5 2 AE r R255 A4 r R255 O209 A9 8272 32 A6 AA 0 3864 992 O45 3864 992 O45 12104 992 O112 12104 992 OF6 3864 0 5 2 AE r RB6 A4 r RB6 O1E5 11944 2464 O45 11944 2464 O45 26664 2464 O10D 26664 0 OEB 11944 2464 3 2 AE r R3FC "PDout3" A4 r R3FC O20A A9 13736 24 A6 AA 0 0 740 O45 13704 736 O1DB 13704 740 3 2 AE r RBD A4 r RBD OFB 26424 160 O205 26504 160 O10E 26424 0 5 2 AE r R321 A4 r R321 O145 27864 672 O45 27864 672 O45 31944 672 O1D5 31944 672 O11D 27864 0 5 2 AE r RBE A4 r RBE O1BC 16504 1824 O45 16504 1824 O45 20344 1824 O121 20344 0 OF0 16504 1824 3 2 AE r R322 A4 r R322 O20B A9 6936 24 A6 AA 0 0 356 O45 6904 352 O20C A9 32 380 A6 AB 0 6904 0 5 2 AE r R3FD "PDout6" A4 r R3FD OF2 1384 288 O45 1384 288 O45 1864 288 O10A 1864 0 O20D A9 32 3136 A6 AB 0 1384 288 5 2 AE r RC0 A4 r RC0 O20E A9 21576 24 A6 AA 0 11224 1572 O45 11224 1568 O45 11704 1568 O20F A9 32 1852 A6 AB 0 11704 1572 O210 A9 32 1596 A6 AB 0 11224 0 5 2 AE r R3FE "/0(MiChip)/7(StatusReg)*1.[16][2]" A4 r R3FE O17A 11304 3168 O45 11304 3168 O45 14984 3168 O1FF 14984 0 O107 11304 3168 5 2 AE r R3FF "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21).[2]" A4 r R3FF O1B5 13624 96 O45 13624 96 O45 21704 96 OFA 21704 0 O211 A9 32 3328 A6 AB 0 13624 96 5 2 AE r R400 "PDout7" A4 r R400 O183 1784 1120 O45 1784 1120 O45 10104 1120 OF3 10104 1120 O105 1784 0 5 2 AE r R25C A4 r R25C O1D9 12984 2784 O45 12984 2784 O45 18024 2784 O1CF 18024 0 O119 12984 2784 5 2 AE r R196 A4 r R196 O147 11864 2272 O45 11864 2272 O45 14904 2272 O105 14904 2272 OF3 11864 0 5 2 AE r RC2 A4 r RC2 O212 A9 17416 24 A6 AA 0 15384 2852 O45 15384 2848 O45 21064 2848 O213 A9 32 2876 A6 AB 0 21064 0 O214 A9 32 572 A6 AB 0 15384 2852 5 2 AE r RC4 A4 r RC4 O1BF 24664 2720 O45 24664 2720 O45 27464 2720 O1D5 27464 0 O11D 24664 2720 5 2 AE r R198 A4 r R198 O14B 12344 96 O45 12344 96 O45 13304 96 O211 13304 96 OFA 12344 0 5 2 AE r R401 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[8]" A4 r R401 O111 27384 864 O45 27384 864 O45 28664 864 O159 28664 0 O116 27384 864 5 2 AE r R402 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21).[2]" A4 r R402 O17C 4104 1376 O45 4104 1376 O45 11784 1376 OFE 11784 0 O13A 4104 1376 5 2 AE r R403 "A3" A4 r R403 O18C 27704 992 O45 27704 992 O45 28504 992 O112 28504 992 OF6 27704 0 5 2 AE r R324 A4 r R324 O198 13944 480 O45 13944 480 O45 20264 480 O13D 20264 0 O215 A9 32 2944 A6 AB 0 13944 480 5 2 AE r R260 A4 r R260 O216 A9 4376 24 A6 AA 0 28424 228 O45 28424 224 O45 28584 224 O217 A9 32 252 A6 AB 0 28584 0 O218 A9 32 3196 A6 AB 0 28424 228 3 2 AE r R19A A4 r R19A O219 A9 26696 24 A6 AA 0 6104 548 O45 6104 544 O214 6104 0 7 2 AE r R261 A4 r R261 O21A A9 14352 32 A6 AA 0 15704 1056 O45 18344 1056 O45 15704 1056 O45 30024 1056 OF1 30024 0 O109 18344 1056 OF1 15704 0 5 2 AE r R404 "A5" A4 r R404 O21B A9 4696 24 A6 AA 0 28104 36 O45 28104 32 O45 28344 32 O21C A9 32 3388 A6 AB 0 28344 36 O136 28104 0 5 2 AE r RCA A4 r RCA O115 17064 2592 O45 17064 2592 O45 21544 2592 O10F 21544 0 O22 17064 2592 7 2 AE r RCC A4 r RCC O21D A9 14056 24 A6 AA 0 18744 804 O45 28904 800 O45 18744 800 O45 27224 800 O137 27224 804 O201 28904 0 O201 18744 0 5 2 AE r RCB A4 r RCB O13C 14264 352 O45 14264 352 O45 28504 352 OF4 28504 0 O21E A9 32 3072 A6 AB 0 14264 352 5 2 AE r R262 A4 r R262 O18F 7864 1568 O45 7864 1568 O45 11144 1568 OF0 11144 0 O121 7864 1568 3 2 AE r R263 A4 r R263 O1DD 0 100 O45 5544 96 O124 5544 0 5 2 AE r R325 A4 r R325 O157 10344 96 O45 10344 96 O45 12184 96 OFA 12184 0 O211 10344 96 5 2 AE r RCF A4 r RCF O101 18904 3168 O45 18904 3168 O45 21064 3168 O107 21064 3168 O1FF 18904 0 7 2 AE r R405 "/0(MiChip)/5(DataMux)*1.[23][2]" A4 r R405 O17A 4344 288 O45 5064 288 O45 4344 288 O45 8024 288 O10A 8024 0 O10A 5064 0 O20D 4344 288 5 2 AE r R19F A4 r R19F O104 15144 2144 O45 15144 2144 O45 21144 2144 O13E 21144 0 OFD 15144 2144 5 2 AE r R1A1 A4 r R1A1 O17D 25464 160 O45 25464 160 O45 30584 160 O10E 30584 0 O205 25464 160 5 2 AE r R1A0 A4 r R1A0 O21F A9 29576 24 A6 AA 0 3224 420 O45 3224 416 O45 5224 416 O220 A9 32 444 A6 AB 0 5224 0 O221 A9 32 3004 A6 AB 0 3224 420 9 2 AE r R406 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]" A4 r R406 O222 A9 8752 32 A6 AA 0 2904 160 O45 5144 160 O45 2904 160 O45 11544 160 O45 11624 160 O205 11624 160 O10E 5144 0 O10E 11544 0 O205 2904 160 5 2 AE r RD5 A4 r RD5 O103 30664 160 O45 30664 160 O45 31224 160 O205 31224 160 O10E 30664 0 5 2 AE r R407 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21).[2]" A4 r R407 O1BF 5384 1184 O45 5384 1184 O45 8184 1184 O11B 8184 1184 O127 5384 0 3 2 AE r R265 A4 r R265 O135 22424 36 O136 22424 0 O21C 22424 36 7 2 AE r R408 "/0(MiChip)/5(DataMux)*1.[23][3]" A4 r R408 O1D0 8664 1824 O45 11464 1824 O45 8664 1824 O45 14024 1824 O121 14024 0 O121 11464 0 OF0 8664 1824 5 2 AE r R326 A4 r R326 OF2 17304 2208 O45 17304 2208 O45 17784 2208 O11B 17784 0 O127 17304 2208 5 2 AE r R266 A4 r R266 O14C 20664 480 O45 20664 480 O45 24904 480 O13D 24904 0 O215 20664 480 9 2 AE r R409 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]" A4 r R409 O222 3064 1504 O45 5304 1504 O45 3064 1504 O45 11704 1504 O45 11784 1504 O12F 11784 1504 O100 5304 0 O100 11704 0 O12F 3064 1504 5 2 AE r R40A "PDout17" A4 r R40A OF2 5464 1440 O45 5464 1440 O45 5944 1440 O11E 5944 1440 O128 5464 0 5 2 AE r R327 A4 r R327 O17A 12984 2656 O45 12984 2656 O45 16664 2656 O130 16664 2656 O1D7 12984 0 7 2 AE r R40B "/0(MiChip)/5(DataMux)*1.[39][3]" A4 r R40B O115 1464 544 O45 1624 544 O45 1464 544 O45 5944 544 O102 5944 0 O102 1624 0 O223 A9 32 2880 A6 AB 0 1464 544 11 2 AE r R40C "/0(MiChip)/5(DataMux)/11(DataLatchMux)*1.[4]" A4 r R40C O224 A9 21152 32 A6 AA 0 8424 2336 O45 11944 2336 O45 29224 2336 O45 8424 2336 O45 27544 2336 O45 29544 2336 O109 29544 0 O109 11944 0 OF1 27544 2336 O109 29224 0 OF1 8424 2336 5 2 AE r RDA A4 r RDA O120 7224 2720 O45 7224 2720 O45 9864 2720 O1D5 9864 0 O11D 7224 2720 5 2 AE r RDB A4 r RDB O17A 18904 3232 O45 18904 3232 O45 22584 3232 O205 22584 0 O10E 18904 3232 5 2 AE r R328 A4 r R328 O140 9304 96 O45 9304 96 O45 10184 96 O211 10184 96 OFA 9304 0 3 2 AE r R40D "HOLDA" A4 r R40D O225 A9 5736 24 A6 AA 0 27064 612 O45 27064 608 O203 27064 0 5 2 AE r R40E "/0(MiChip)/2(MemCtlA)/54(mux21)/0(NormalizedMux21)*1.[1]" A4 r R40E O15C 26904 96 O45 26904 96 O45 27144 96 OFA 27144 0 OFA 26904 0 5 2 AE r R40F "/0(MiChip)/5(DataMux)/7(DecoderS)*1.nAd[1]" A4 r R40F O12E 16024 1696 O45 16024 1696 O45 16744 1696 OEC 16744 1696 OEC 16024 0 7 2 AE r R410 "/0(MiChip)/6(AddrCtl)*1.[19]" A4 r R410 O191 27304 96 O45 31464 96 O45 27304 96 O45 31704 96 OFA 31704 0 OFA 31464 0 O211 27304 96 5 2 AE r R411 "/0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)*1.[3]" A4 r R411 O1D0 14344 32 O45 14344 32 O45 19704 32 OEE 19704 0 OEE 14344 0 5 2 AE r R1A3 A4 r R1A3 O138 2984 1248 O45 2984 1248 O45 19144 1248 OFD 19144 0 O13E 2984 1248 5 2 AE r R32A A4 r R32A OFC 9384 672 O45 9384 672 O45 14104 672 O11D 14104 0 O1D5 9384 672 5 2 AE r R32C A4 r R32C O10B 24664 2656 O45 24664 2656 O45 26344 2656 O130 26344 2656 O1D7 24664 0 5 2 AE r RE0 A4 r RE0 O1F1 10504 32 O45 10504 32 O45 14264 32 OEE 14264 0 O226 A9 32 3392 A6 AB 0 10504 32 5 2 AE r R412 "/0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)*1.[5]" A4 r R412 O12D 8744 1696 O45 8744 1696 O45 14424 1696 OEC 14424 0 OEC 8744 0 5 2 AE r R413 "/0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)*1.[5]" A4 r R413 O197 4264 1568 O45 4264 1568 O45 5864 1568 OF0 5864 0 O121 4264 1568 3 2 AE r R1A5 A4 r R1A5 OFB 4904 288 O10A 4984 0 O20D 4904 288 5 2 AE r R414 "PDout39" A4 r R414 O15B 7784 32 O45 7784 32 O45 10264 32 OEE 10264 0 O226 7784 32 5 2 AE r R1A6 A4 r R1A6 O129 6264 2272 O45 6264 2272 O45 9624 2272 OF3 9624 0 O105 6264 2272 5 2 AE r R26A A4 r R26A O227 A9 10536 24 A6 AA 0 22264 292 O45 22264 288 O45 26024 288 O228 A9 32 316 A6 AB 0 26024 0 O229 A9 32 3132 A6 AB 0 22264 292 5 2 AE r R32E A4 r R32E O12E 18824 2080 O45 18824 2080 O45 19544 2080 O114 19544 2080 O133 18824 0 5 2 AE r R415 "/0(MiChip)/5(DataMux)*1.Select.I-A" A4 r R415 O1D9 16824 288 O45 16824 288 O45 21864 288 O10A 21864 0 O20D 16824 288 5 2 AE r R32F A4 r R32F O111 18104 3040 O45 18104 3040 O45 19384 3040 OF4 19384 3040 O21E 18104 0 5 2 AE r R1AA A4 r R1AA O12A 23304 160 O45 23304 160 O45 25224 160 O10E 25224 0 O205 23304 160 5 2 AE r R1A9 A4 r R1A9 O120 6904 2656 O45 6904 2656 O45 9544 2656 O1D7 9544 0 O130 6904 2656 5 2 AE r R1AB A4 r R1AB O1D0 12264 1504 O45 12264 1504 O45 17624 1504 O12F 17624 1504 O100 12264 0 5 2 AE r RE5 A4 r RE5 O14B 19064 3360 O45 19064 3360 O45 20024 3360 O226 20024 0 OEE 19064 3360 5 2 AE r R26C A4 r R26C O14C 19464 864 O45 19464 864 O45 23704 864 O159 23704 0 O116 19464 864 5 2 AE r R416 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[7][0]" A4 r R416 O15A 7064 352 O45 7064 352 O45 9944 352 OF4 9944 0 O21E 7064 352 5 2 AE r R417 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21).[2]" A4 r R417 O17A 2584 1056 O45 2584 1056 O45 6264 1056 OF1 6264 0 O109 2584 1056 5 2 AE r R334 A4 r R334 O141 23464 1248 O45 23464 1248 O45 25704 1248 OFD 25704 0 O13E 23464 1248 5 2 AE r R336 A4 r R336 O12E 12104 480 O45 12104 480 O45 12824 480 O215 12824 480 O13D 12104 0 5 2 AE r R418 "/0(MiChip)/5(DataMux)*1.[15][0]" A4 r R418 O190 12584 1120 O45 12584 1120 O45 28664 1120 OF3 28664 1120 O105 12584 0 5 2 AE r R419 "/0(MiChip)/7(StatusReg)*1.[2]" A4 r R419 O1B7 7944 1440 O45 7944 1440 O45 15224 1440 O128 15224 0 O11E 7944 1440 5 2 AE r R337 A4 r R337 O141 13064 2208 O45 13064 2208 O45 15304 2208 O11B 15304 0 O127 13064 2208 5 2 AE r R41A "/0(MiChip)/5(DataMux)*1.[15][1]" A4 r R41A O1D0 7144 800 O45 7144 800 O45 12504 800 O22 12504 0 O10F 7144 800 5 2 AE r R1AE A4 r R1AE O131 5784 96 O45 5784 96 O45 9224 96 OFA 9224 0 O211 5784 96 7 2 AE r R41B "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)*1.nEnable" A4 r R41B O1F1 5304 1632 O45 8904 1632 O45 5304 1632 O45 9064 1632 OF7 9064 0 OF7 8904 0 O14D 5304 1632 5 2 AE r R1B0 A4 r R1B0 O192 11304 3104 O45 11304 3104 O45 18104 3104 O10A 18104 3104 O20D 11304 0 5 2 AE r R1B1 A4 r R1B1 O115 14504 736 O45 14504 736 O45 18984 736 O130 18984 0 O1D7 14504 736 5 2 AE r R33C A4 r R33C OF2 1224 416 O45 1224 416 O45 1704 416 O10C 1704 0 O206 1224 416 5 2 AE r R41C "/0(MiChip)/5(DataMux)/0(ParGen)*1.[3]" A4 r R41C OFC 14584 864 O45 14584 864 O45 19304 864 O159 19304 0 O116 14584 864 7 2 AE r R273 A4 r R273 O113 8184 1056 O45 11064 1056 O45 8184 1056 O45 15544 1056 OF1 15544 0 OF1 11064 0 OF1 8184 0 5 2 AE r R33D A4 r R33D O157 16424 1312 O45 16424 1312 O45 18264 1312 O114 18264 0 O133 16424 1312 5 2 AE r R1B2 A4 r R1B2 O11F 12424 160 O45 12424 160 O45 13784 160 O205 13784 160 O10E 12424 0 5 2 AE r R33E A4 r R33E O22A A9 2992 32 A6 AA 0 18184 2656 O45 18184 2656 O45 21144 2656 O130 21144 2656 O1D7 18184 0 5 2 AE r R41D "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]" A4 r R41D O21A 6024 1888 O45 6024 1888 O45 20344 1888 O100 20344 1888 O12F 6024 0 3 2 AE r R41E "PDin3" A4 r R41E O22B A9 4456 24 A6 AA 0 0 228 O45 4424 224 O217 4424 0 5 2 AE r R340 A4 r R340 O22A 19064 3104 O45 19064 3104 O45 22024 3104 O10A 22024 3104 O20D 19064 0 5 2 AE r R341 A4 r R341 O111 2744 1184 O45 2744 1184 O45 4024 1184 O127 4024 0 O11B 2744 1184 5 2 AE r R275 A4 r R275 O191 24584 736 O45 24584 736 O45 28984 736 O130 28984 0 O1D7 24584 736 7 2 AE r R278 A4 r R278 O143 26104 32 O45 26824 32 O45 26104 32 O45 27304 32 OEE 27304 0 OEE 26824 0 OEE 26104 0 5 2 AE r R41F "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]" A4 r R41F O21A 6184 2016 O45 6184 2016 O45 20504 2016 OFE 20504 2016 O13A 6184 0 5 2 AE r R420 "/0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)*1.[3]" A4 r R420 O11F 15304 2592 O45 15304 2592 O45 16664 2592 O10F 16664 0 O22 15304 2592 5 2 AE r R421 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[14]" A4 r R421 O19D 2184 928 O45 2184 928 O45 8344 928 OEB 8344 0 OEB 2184 0 5 2 AE r R422 "/0(MiChip)/2(MemCtlA)*1.[65]" A4 r R422 O17B 26184 672 O45 26184 672 O45 27224 672 O11D 27224 0 O1D5 26184 672 5 2 AE r R423 "/0(MiChip)/4(RefreshCtr)*1.[8][12]" A4 r R423 O19A 24984 480 O45 24984 480 O45 30424 480 O13D 30424 0 O215 24984 480 3 2 AE r R424 "PDin5" A4 r R424 O22C A9 2536 24 A6 AA 0 0 164 O45 2504 160 O1B4 2504 0 5 2 AE r REE A4 r REE O11A 20424 1824 O45 20424 1824 O45 24744 1824 OF0 24744 1824 O121 20424 0 5 2 AE r R344 A4 r R344 OFF 29064 352 O45 29064 352 O45 31064 352 O21E 31064 352 OF4 29064 0 5 2 AE r R1B4 A4 r R1B4 O184 3144 992 O45 3144 992 O45 3304 992 O112 3304 992 OF6 3144 0 5 2 AE r R27A A4 r R27A O18E 2664 288 O45 2664 288 O45 4104 288 O10A 4104 0 O20D 2664 288 5 2 AE r R425 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21).[2]" A4 r R425 O17B 15864 1440 O45 15864 1440 O45 16904 1440 O11E 16904 1440 O128 15864 0 5 2 AE r RF0 A4 r RF0 O140 27944 1504 O45 27944 1504 O45 28824 1504 O100 28824 0 O12F 27944 1504 5 2 AE r RF2 A4 r RF2 O139 29784 736 O45 29784 736 O45 30424 736 O1D7 30424 736 O130 29784 0 5 2 AE r RF1 A4 r RF1 O1D6 12584 1376 O45 12584 1376 O45 17544 1376 OFE 17544 0 O13A 12584 1376 5 2 AE r R426 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[1]" A4 r R426 O11F 23784 608 O45 23784 608 O45 25144 608 O1CF 25144 608 O119 23784 0 3 2 AE r R427 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)*1.nInput[0]" A4 r R427 OFB 18424 32 OEE 18504 0 OEE 18424 0 5 2 AE r RF7 A4 r RF7 O11F 1704 992 O45 1704 992 O45 3064 992 OF6 3064 0 O112 1704 992 5 2 AE r R428 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[17]" A4 r R428 OFC 14664 2912 O45 14664 2912 O45 19384 2912 O215 19384 0 O13D 14664 2912 5 2 AE r R27C A4 r R27C O1F1 10424 352 O45 10424 352 O45 14184 352 OF4 14184 0 O21E 10424 352 5 2 AE r RB A4 r RB O15F 8424 2208 O45 8424 2208 O45 12024 2208 O127 12024 2208 O11B 8424 0 5 2 AE r RF8 A4 r RF8 O140 27864 1248 O45 27864 1248 O45 28744 1248 OFD 28744 0 O13E 27864 1248 5 2 AE r R34A A4 r R34A O14B 25304 608 O45 25304 608 O45 26264 608 O1CF 26264 608 O119 25304 0 5 2 AE r RFF A4 r RFF O15A 23704 992 O45 23704 992 O45 26584 992 OF6 26584 0 O112 23704 992 3 2 AE r R429 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)*1.nInput[1]" A4 r R429 O135 20824 36 O136 20824 0 O21C 20824 36 5 2 AE r R34C A4 r R34C O18C 22824 1632 O45 22824 1632 O45 23624 1632 OF7 23624 0 O14D 22824 1632 5 2 AE r R34D A4 r R34D OF2 17384 2080 O45 17384 2080 O45 17864 2080 O133 17864 0 O114 17384 2080 5 2 AE r R101 A4 r R101 O144 16264 608 O45 16264 608 O45 20184 608 O119 20184 0 O1CF 16264 608 5 2 AE r R42A "/0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21).[2]" A4 r R42A OF2 27544 32 O45 27544 32 O45 28024 32 OEE 28024 0 OEE 27544 0 5 2 AE r R34E A4 r R34E O11C 26984 224 O45 26984 224 O45 28104 224 O1FF 28104 224 O107 26984 0 11 2 AE r R42B "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv).nEnable" A4 r R42B O224 8504 1184 O45 12024 1184 O45 29304 1184 O45 8504 1184 O45 27624 1184 O45 29624 1184 O127 29624 0 O127 12024 0 O11B 27624 1184 O127 29304 0 O11B 8504 1184 11 2 AE r R280 A4 r R280 O22D A9 15072 32 A6 AA 0 6424 2400 O45 14824 2400 O45 21224 2400 O45 6424 2400 O45 18264 2400 O45 21464 2400 O112 21464 0 OF6 14824 2400 OF6 18264 2400 O112 21224 0 OF6 6424 2400 5 2 AE r R103 A4 r R103 O15D 13544 1632 O45 13544 1632 O45 16744 1632 OF7 16744 0 O14D 13544 1632 5 2 AE r R1BC A4 r R1BC O161 13864 160 O45 13864 160 O45 15624 160 O10E 15624 0 O205 13864 160 5 2 AE r R34F A4 r R34F O10B 24744 864 O45 24744 864 O45 26424 864 O116 26424 864 O159 24744 0 11 2 AE r R282 A4 r R282 O22D 6584 3296 O45 14984 3296 O45 21304 3296 O45 6584 3296 O45 18424 3296 O45 21624 3296 O211 21624 0 OFA 14984 3296 OFA 18424 3296 O211 21304 0 OFA 6584 3296 5 2 AE r R283 A4 r R283 O106 6184 2144 O45 6184 2144 O45 9704 2144 O13E 9704 0 OFD 6184 2144 5 2 AE r R42C "/0(MiChip)/4(RefreshCtr)*1.[3][12]" A4 r R42C O15C 30264 864 O45 30264 864 O45 30504 864 O159 30504 0 O116 30264 864 5 2 AE r R1BF A4 r R1BF O12D 12664 800 O45 12664 800 O45 18344 800 O22 18344 0 O10F 12664 800 5 2 AE r R107 A4 r R107 O125 22904 1312 O45 22904 1312 O45 25624 1312 O114 25624 0 O133 22904 1312 3 2 AE r R351 A4 r R351 OFB 26664 2528 O116 26744 0 O159 26664 2528 5 2 AE r R352 A4 r R352 OF2 3944 480 O45 3944 480 O45 4424 480 O215 4424 480 O13D 3944 0 5 2 AE r R353 A4 r R353 O1D0 15384 2720 O45 15384 2720 O45 20744 2720 O11D 20744 2720 O1D5 15384 0 5 2 AE r R1C2 A4 r R1C2 O161 14024 2080 O45 14024 2080 O45 15784 2080 O133 15784 0 O114 14024 2080 5 2 AE r R285 A4 r R285 O143 15944 160 O45 15944 160 O45 17144 160 O205 17144 160 O10E 15944 0 3 2 AE r R42D "PDin10" A4 r R42D O22E A9 7576 24 A6 AA 0 0 36 O45 7544 32 O136 7544 0 5 2 AE r R42E "/0(MiChip)/5(DataMux)*1.[11][2]" A4 r R42E O1AE 4024 1312 O45 4024 1312 O45 16344 1312 O114 16344 0 O133 4024 1312 5 2 AE r R354 A4 r R354 O22F A9 4592 32 A6 AA 0 15224 2272 O45 15224 2272 O45 19784 2272 OF3 19784 0 O105 15224 2272 3 2 AE r R42F "PDin11" A4 r R42F O230 A9 13576 24 A6 AA 0 0 868 O45 13544 864 O231 A9 32 892 A6 AB 0 13544 0 5 2 AE r R430 "/0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)*1.[4]" A4 r R430 O162 16984 1632 O45 16984 1632 O45 22504 1632 O14D 22504 1632 OF7 16984 0 5 2 AE r R1C6 A4 r R1C6 O129 22104 96 O45 22104 96 O45 25464 96 OFA 25464 0 O211 22104 96 5 2 AE r R1C7 A4 r R1C7 O15F 19304 1248 O45 19304 1248 O45 22904 1248 OFD 22904 0 O13E 19304 1248 5 2 AE r R431 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)*1.nInput[4]" A4 r R431 O101 19944 32 O45 19944 32 O45 22104 32 OEE 22104 0 OEE 19944 0 5 2 AE r R432 "/0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)*1.[3]" A4 r R432 O117 5144 480 O45 5144 480 O45 7224 480 O13D 7224 0 O215 5144 480 9 2 AE r R433 "/0(MiChip)/5(DataMux)*1.[11][3]" A4 r R433 O232 A9 20112 32 A6 AA 0 4904 224 O45 16264 224 O45 4904 224 O45 21384 224 O45 24984 224 O107 24984 0 O107 16264 0 O107 21384 0 O107 4904 0 5 2 AE r R108 A4 r R108 OF5 7464 480 O45 7464 480 O45 8984 480 O13D 8984 0 O215 7464 480 7 2 AE r R286 A4 r R286 O233 A9 12272 32 A6 AA 0 5464 1760 O45 15464 1760 O45 5464 1760 O45 17704 1760 OF7 17704 1760 O14D 15464 0 OF7 5464 1760 5 2 AE r R287 A4 r R287 O103 25944 96 O45 25944 96 O45 26504 96 OFA 26504 0 O211 25944 96 5 2 AE r R356 A4 r R356 O1F1 7624 1952 O45 7624 1952 O45 11384 1952 O11E 11384 0 O128 7624 1952 5 2 AE r R434 "/0(MiChip)/5(DataMux)*1.[11][4]" A4 r R434 O10B 18184 2784 O45 18184 2784 O45 19864 2784 O1CF 19864 0 O119 18184 2784 5 2 AE r R435 "HOLD" A4 r R435 O129 22984 2592 O45 22984 2592 O45 26344 2592 O10F 26344 0 O22 22984 2592 5 2 AE r R10A A4 r R10A O11A 20184 672 O45 20184 672 O45 24504 672 O11D 24504 0 O1D5 20184 672 5 2 AE r R359 A4 r R359 O187 2984 672 O45 2984 672 O45 9224 672 O1D5 9224 672 O11D 2984 0 5 2 AE r R436 "/0(MiChip)/1(ClockGen)*1.[11]" A4 r R436 O1BB 18584 992 O45 18584 992 O45 23464 992 OF6 23464 0 O112 18584 992 5 2 AE r R10D A4 r R10D O22F 18824 2208 O45 18824 2208 O45 23384 2208 O11B 23384 0 O127 18824 2208 5 2 AE r R437 "/0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)*1.[5]" A4 r R437 O14A 6744 608 O45 6744 608 O45 10744 608 O1CF 10744 608 O119 6744 0 3 2 AE r R438 "PDin23" A4 r R438 O234 A9 3416 24 A6 AA 0 0 484 O45 3384 480 O235 A9 32 508 A6 AB 0 3384 0 5 2 AE r R35A A4 r R35A O19A 17624 1376 O45 17624 1376 O45 23064 1376 O13A 23064 1376 OFE 17624 0 5 2 AE r R1CA A4 r R1CA O180 12744 1632 O45 12744 1632 O45 13144 1632 OF7 13144 0 O14D 12744 1632 5 2 AE r R439 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[0]" A4 r R439 O12E 28744 1312 O45 28744 1312 O45 29464 1312 O114 29464 0 O133 28744 1312 5 2 AE r R35C A4 r R35C O11A 19224 736 O45 19224 736 O45 23544 736 O1D7 23544 736 O130 19224 0 5 2 AE r R1CC A4 r R1CC O132 14184 672 O45 14184 672 O45 20104 672 O11D 20104 0 O1D5 14184 672 5 2 AE r R112 A4 r R112 O14A 18664 1760 O45 18664 1760 O45 22664 1760 O14D 22664 0 OF7 18664 1760 5 2 AE r R1D0 A4 r R1D0 O12C 8104 288 O45 8104 288 O45 16584 288 O20D 16584 288 O10A 8104 0 5 2 AE r R1CE A4 r R1CE O17A 25384 1376 O45 25384 1376 O45 29064 1376 O13A 29064 1376 OFE 25384 0 10 2 AE r R43A "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)*1.nInput[6]" A4 r R43A O236 A9 3568 32 A6 AA 0 19608 2080 O45 19608 2080 O45 23144 2080 O114 23144 2080 O237 A9 32 608 A6 AB 0 19608 1504 O238 A9 1936 32 A6 AA 0 17704 1504 O45 17704 1504 O45 19608 1504 O237 19608 1504 O100 17704 0 3 2 AE r R43B "PDin27" A4 r R43B O239 A9 1176 24 A6 AA 0 0 292 O45 1144 288 O228 1144 0 5 2 AE r R1D1 A4 r R1D1 O120 6824 2528 O45 6824 2528 O45 9464 2528 O116 9464 0 O159 6824 2528 5 2 AE r R35D A4 r R35D O129 22184 32 O45 22184 32 O45 25544 32 OEE 25544 0 O226 22184 32 5 2 AE r R43C "DataDir" A4 r R43C O239 31624 164 O45 31624 160 O45 31864 160 O1B4 31864 0 O1B4 31624 0 0 0 14400 0 1 AE r R43D "MIInnerChan6" O23A A2 0 0 32800 864 160 O23B A2 0 0 720 832 2 O23C A2 0 0 720 80 1 O23D A9 720 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 720 80 R2 1059061760 0 0 0 0 0 0 0 O23E A2 0 0 720 80 1 O23D 0 0 0 2 A4 r RC AE r RC 0 0 720 80 R2 1059061760 0 0 0 0 752 0 0 0 0 720 832 R43E "MIInnerLeft6" 1031153506 0 1 0 0 0 0 0 ODD 720 0 0 2 AE r R43F "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1" A1A a A1A O18 1184 0 0 2 AE r R440 "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)*1.[4]-6" A1A a A1A O86 1280 0 0 2 AE r R441 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 1424 0 0 2 AE r R442 "/0(MiChip)/5(DataMux)*1.[39][3]-6" A1A a A1A O86 1520 0 0 2 AE r R443 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 1664 0 0 2 AE r R444 "/0(MiChip)/4(RefreshCtr)*1.[8][9]-6" A1A a A1A O24 1760 0 0 2 AE r R445 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 2544 0 0 2 AE r R446 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21).[2]-6" A1A a A1A O18 2624 0 0 2 AE r R447 "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)*1.[3]-6" A1A a A1A O18 2704 0 0 2 AE r R448 "/0(MiChip)/5(DataMux)*1.[15][7]-6" A1A a A1A OA4 2800 0 0 2 AE r R449 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 3184 0 0 2 AE r R44A "Din13-6" A1A a A1A O24 3280 0 0 2 AE r R44B "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 4080 0 0 2 AE r R44C "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 4224 0 0 2 AE r R44D "/0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)*1.[5]-6" A1A a A1A O18 4304 0 0 2 AE r R44E "/0(MiChip)/5(DataMux)*1.[23][2]-6" A1A a A1A O86 4400 0 0 2 AE r R44F "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv4" A1A a A1A O18 4544 0 0 2 AE r R450 "PDout21-6" A1A a A1A OCE 4640 0 0 2 AE r R451 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver4" A1A a A1A O86 4960 0 0 2 AE r R452 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 5104 0 0 2 AE r R453 "/0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)*1.[3]-6" A1A a A1A OCA 5200 0 0 2 AE r R454 "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)/1(NormalizedNor2)/0(Nor2)" A1A a A1A O98 5440 0 0 2 AE r R455 "/0(MiChip)/7(StatusReg)/0(ffrs1)/1(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O18 5744 0 0 2 AE r R456 "/0(MiChip)/5(DataMux)*1.[15][2]-6" A1A a A1A O86 5840 0 0 2 AE r R457 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 6000 0 0 2 AE r R458 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 6144 0 0 2 AE r R459 "/0(MiChip)/7(StatusReg)*1.[14][0]-6" A1A a A1A O18 6224 0 0 2 AE r R45A "Dout12-6" A1A a A1A OA4 6320 0 0 2 AE r R45B "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 6720 0 0 2 AE r R45C "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver1" A1A a A1A O18 7024 0 0 2 AE r R45D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[7][0]-6" A1A a A1A O18 7104 0 0 2 AE r R45E "/0(MiChip)/5(DataMux)*1.[15][1]-6" A1A a A1A O18 7184 0 0 2 AE r R45F "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[6][1]-6" A1A a A1A O86 7280 0 0 2 AE r R460 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv1" A1A a A1A O86 7440 0 0 2 AE r R461 "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)/2(Inv)" A1A a A1A O18 7584 0 0 2 AE r R462 "/0(MiChip)/5(DataMux)*1.Select[0]-6" A1A a A1A O18 7664 0 0 2 AE r R463 "PDin36-6" A1A a A1A O18 7744 0 0 2 AE r R464 "PDout39-6" A1A a A1A O18 7824 0 0 2 AE r R465 "PDout35-6" A1A a A1A O18 7904 0 0 2 AE r R466 "/0(MiChip)/7(StatusReg)*1.[2]-6" A1A a A1A O86 8000 0 0 2 AE r R467 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv6" A1A a A1A O86 8160 0 0 2 AE r R468 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 8320 0 0 2 AE r R469 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver4" A1A a A1A O18 8624 0 0 2 AE r R46A "/0(MiChip)/5(DataMux)*1.[23][3]-6" A1A a A1A ODD 8720 0 0 2 AE r R46B "/0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1" A1A a A1A O86 9200 0 0 2 AE r R46C "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv5" A1A a A1A O18 9344 0 0 2 AE r R46D "PDout38-6" A1A a A1A O18 9424 0 0 2 AE r R46E "/0(MiChip)*1.RASX-6" A1A a A1A ODD 9520 0 0 2 AE r R46F "/0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1" A1A a A1A O86 10000 0 0 2 AE r R470 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 10160 0 0 2 AE r R471 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv6" A1A a A1A O18 10304 0 0 2 AE r R472 "/0(MiChip)/2(MemCtlA)*1.WrHCy-6" A1A a A1A O18 10384 0 0 2 AE r R473 "/0(MiChip)/3(AddrMux)*1.[14]-6" A1A a A1A O18 10464 0 0 2 AE r R474 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncount-6" A1A a A1A O18 10544 0 0 2 AE r R475 "/0(MiChip)/5(DataMux)*1.[28][5]-6" A1A a A1A ODD 10640 0 0 2 AE r R476 "/0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1" A1A a A1A O86 11120 0 0 2 AE r R477 "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)/4(Inv)" A1A a A1A O18 11264 0 0 2 AE r R478 "/0(MiChip)/7(StatusReg)*1.[16][2]-6" A1A a A1A O18 11344 0 0 2 AE r R479 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][4]-6" A1A a A1A O18 11424 0 0 2 AE r R47A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][4]-6" A1A a A1A OA4 11520 0 0 2 AE r R47B "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 11904 0 0 2 AE r R47C "PDout0-6" A1A a A1A O18 11984 0 0 2 AE r R47D "Gnd-6" A1A a A1A O18 12064 0 0 2 AE r R47E "/0(MiChip)/5(DataMux)*1.[28][7]-6" A1A a A1A O18 12144 0 0 2 AE r R47F "/0(MiChip)/6(AddrCtl)*1.[13]-6" A1A a A1A OCE 12240 0 0 2 AE r R480 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver6" A1A a A1A O18 12544 0 0 2 AE r R481 "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)*1.[5]-6" A1A a A1A O18 12624 0 0 2 AE r R482 "/0(MiChip)/5(DataMux)*1.[11][0]-6" A1A a A1A OCA 12720 0 0 2 AE r R483 "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 12944 0 0 2 AE r R484 "/0(MiChip)/2(MemCtlA)*1.PadEnb-6" A1A a A1A O18 13024 0 0 2 AE r R485 "/0(MiChip)/5(DataMux)/7(DecoderS)*1.nnAd[0]-6" A1A a A1A OA4 13120 0 0 2 AE r R486 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 13504 0 0 2 AE r R487 "/0(MiChip)*1.[27][2]-6" A1A a A1A O86 13600 0 0 2 AE r R488 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OA4 13760 0 0 2 AE r R489 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 14144 0 0 2 AE r R48A "RPadEnb-6" A1A a A1A O18 14224 0 0 2 AE r R48B "Din5-6" A1A a A1A O86 14320 0 0 2 AE r R48C "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 14464 0 0 2 AE r R48D "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two-6" A1A a A1A O18 14544 0 0 2 AE r R48E "/0(MiChip)/5(DataMux)/0(ParGen)*1.[3]-6" A1A a A1A O18 14624 0 0 2 AE r R48F "/0(MiChip)/5(DataMux)/0(ParGen)*1.[17]-6" A1A a A1A OA4 14720 0 0 2 AE r R490 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 15104 0 0 2 AE r R491 "Din7-6" A1A a A1A O18 15184 0 0 2 AE r R492 "/0(MiChip)/4(RefreshCtr)*1.[3][13]-6" A1A a A1A O18 15264 0 0 2 AE r R493 "/0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)*1.[3]-6" A1A a A1A O18 15344 0 0 2 AE r R494 "Dout6-6" A1A a A1A O24 15440 0 0 2 AE r R495 "/0(MiChip)/2(MemCtlA)/39(FF)*1" A1A a A1A O18 16224 0 0 2 AE r R496 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[9][1]-6" A1A a A1A O86 16320 0 0 2 AE r R497 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/1(Inv)*1*1*1*1" A1A a A1A O18 16464 0 0 2 AE r R498 "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nEnable-6" A1A a A1A O18 16544 0 0 2 AE r R499 "/0(MiChip)/4(RefreshCtr)*1.[3].Cin-6" A1A a A1A OCA 16640 0 0 2 AE r R49A "/0(MiChip)/5(DataMux)/7(DecoderS)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O86 16880 0 0 2 AE r R49B "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 17024 0 0 2 AE r R49C "Din4-6" A1A a A1A O18 17104 0 0 2 AE r R49D "/0(MiChip)/5(DataMux)/12(ParGen)*1.[16]-6" A1A a A1A OCE 17200 0 0 2 AE r R49E "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver5" A1A a A1A O18 17504 0 0 2 AE r R49F "Dout4-6" A1A a A1A O18 17584 0 0 2 AE r R4A0 "/0(MiChip)/2(MemCtlA)*1.C1-6" A1A a A1A O98 17680 0 0 2 AE r R4A1 "/0(MiChip)/7(StatusReg)/1(ffrs1)/1(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O18 17984 0 0 2 AE r R4A2 "/0(MiChip)/5(DataMux)*1.[31]-6" A1A a A1A O18 18064 0 0 2 AE r R4A3 "/0(MiChip)/5(DataMux)*1.[15][3]-6" A1A a A1A OA4 18160 0 0 2 AE r R4A4 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 18544 0 0 2 AE r R4A5 "/0(MiChip)/1(ClockGen)*1.[11]-6" A1A a A1A O18 18624 0 0 2 AE r R4A6 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv).nEnable-6" A1A a A1A O18 18704 0 0 2 AE r R4A7 "/0(MiChip)/5(DataMux)*1.[28][2]-6" A1A a A1A O18 18784 0 0 2 AE r R4A8 "/0(MiChip)*1.LdStatus[0]-6" A1A a A1A O18 18864 0 0 2 AE r R4A9 "/0(MiChip)*1.LdAddrHi[1]-6" A1A a A1A O168 18960 0 0 2 AE r R4AA "/0(MiChip)/2(MemCtlA)/24(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 19264 0 0 2 AE r R4AB "/0(MiChip)/3(AddrMux)*1.In1[1]-6" A1A a A1A O18 19344 0 0 2 AE r R4AC "/0(MiChip)/2(MemCtlA)*1.C0-6" A1A a A1A O18 19424 0 0 2 AE r R4AD "/0(MiChip)/2(MemCtlA)*1.C4B-6" A1A a A1A O18 19504 0 0 2 AE r R4AE "/0(MiChip)/2(MemCtlA)*1.C4A-6" A1A a A1A ODD 19600 0 0 2 AE r R4AF "/0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1" A1A a A1A O18 20064 0 0 2 AE r R4B0 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.nLoad-6" A1A a A1A O18 20144 0 0 2 AE r R4B1 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.load-6" A1A a A1A OA4 20240 0 0 2 AE r R4B2 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 20624 0 0 2 AE r R4B3 "Dout8-6" A1A a A1A O86 20720 0 0 2 AE r R4B4 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv1" A1A a A1A OA4 20880 0 0 2 AE r R4B5 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 21280 0 0 2 AE r R4B6 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 22064 0 0 2 AE r R4B7 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][0]-6" A1A a A1A O18 22144 0 0 2 AE r R4B8 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][3]-6" A1A a A1A O18 22224 0 0 2 AE r R4B9 "Dout13-6" A1A a A1A OAF 22320 0 0 2 AE r R4BA "/0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A OCA 22560 0 0 2 AE r R4BB "/0(MiChip)/7(StatusReg)/1(ffrs1)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 22784 0 0 2 AE r R4BC "/0(MiChip)*1.[27][1]-6" A1A a A1A O18 22864 0 0 2 AE r R4BD "/0(MiChip)/3(AddrMux)*1.In1[0]-6" A1A a A1A O18 22944 0 0 2 AE r R4BE "HOLD-6" A1A a A1A O86 23040 0 0 2 AE r R4BF "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv6" A1A a A1A O168 23200 0 0 2 AE r R4C0 "/0(MiChip)/2(MemCtlA)/5(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O86 23520 0 0 2 AE r R4C1 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv7" A1A a A1A O18 23664 0 0 2 AE r R4C2 "/0(MiChip)/3(AddrMux)*1.In0[0]-6" A1A a A1A O24 23760 0 0 2 AE r R4C3 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 24544 0 0 2 AE r R4C4 "XIRQ0-6" A1A a A1A O18 24624 0 0 2 AE r R4C5 "/0(MiChip)/3(AddrMux)*1.In1[9]-6" A1A a A1A OCA 24720 0 0 2 AE r R4C6 "/0(MiChip)/2(MemCtlA)/9(fsm2p)/0(ffP)/1(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 24944 0 0 2 AE r R4C7 "/0(MiChip)/4(RefreshCtr)*1.[8][12]-6" A1A a A1A O86 25040 0 0 2 AE r R4C8 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv1" A1A a A1A O24 25200 0 0 2 AE r R4C9 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 26000 0 0 2 AE r R4CA "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv6" A1A a A1A O18 26144 0 0 2 AE r R4CB "/0(MiChip)/2(MemCtlA)*1.[65]-6" A1A a A1A OCE 26240 0 0 2 AE r R4CC "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver2" A1A a A1A OCA 26560 0 0 2 AE r R4CD "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/3/2(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O86 26800 0 0 2 AE r R4CE "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv0" A1A a A1A OCE 26960 0 0 2 AE r R4CF "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver0" A1A a A1A O18 27264 0 0 2 AE r R4D0 "/0(MiChip)/6(AddrCtl)*1.[19]-6" A1A a A1A O18 27344 0 0 2 AE r R4D1 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[8]-6" A1A a A1A OCE 27440 0 0 2 AE r R4D2 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver6" A1A a A1A OCE 27760 0 0 2 AE r R4D3 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver1" A1A a A1A OAF 28080 0 0 2 AE r R4D4 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/2(Or6)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O98 28320 0 0 2 AE r R4D5 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/2(Or6)/2(NormalizedNor3)/0(Nor3)" A1A a A1A O86 28640 0 0 2 AE r R4D6 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv0" A1A a A1A OCE 28800 0 0 2 AE r R4D7 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver7" A1A a A1A O24 29120 0 0 2 AE r R4D8 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 29920 0 0 2 AE r R4D9 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver12" A1A a A1A O86 30240 0 0 2 AE r R4DA "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv12" A1A a A1A O24 30400 0 0 2 AE r R4DB "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 31200 0 0 2 AE r R4DC "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O23F A2 0 0 800 832 2 O240 A2 0 0 800 80 1 O241 A9 800 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 800 80 R2 1059061760 0 0 0 0 0 0 0 O242 A2 0 0 800 80 1 O241 0 0 0 2 A4 r RC AE r RC 0 0 800 80 R2 1059061760 0 0 0 0 752 0 0 0 0 800 832 R4DD "MIInnerRight6" 1031153506 0 1 0 32000 0 0 0 0 0 32800 832 R4DE "MIInnerIntRow6" 1030556027 0 0 0 0 17824 0 1 AE r R4DF "Row6" O243 A29 0 0 32800 4064 226 0 0 32800 4064 5 2 AE r R4E0 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21).[2]" A4 r R4E0 O1D0 1304 672 O45 1304 672 O45 6664 672 O11D 6664 0 O11D 1304 0 7 2 AE r R314 A4 r R314 O244 A9 20296 24 A6 AA 0 12504 420 O45 29624 416 O45 12504 416 O45 27704 416 O220 27704 0 O245 A9 32 3644 A6 AB 0 29624 420 O220 12504 0 5 2 AE r RA1 A4 r RA1 O1B6 13704 928 O45 13704 928 O45 20104 928 OEB 20104 0 O20D 13704 928 5 2 AE r R3F5 A4 r R3F5 O161 7704 3296 O45 7704 3296 O45 9464 3296 O130 9464 3296 O211 7704 0 5 2 AE r R4E1 "/0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)*1.[7]" A4 r R4E1 O1D0 16984 3616 O45 16984 3616 O45 22344 3616 O246 A9 32 3648 A6 AB 0 22344 0 O10C 16984 3616 5 2 AE r R4E2 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)*1.nInput[7]" A4 r R4E2 OF8 23624 352 O45 23624 352 O45 28824 352 OF4 28824 0 OF4 23624 0 5 2 AE r R4E3 "PDout10" A4 r R4E3 O247 A9 8856 24 A6 AA 0 0 548 O45 8264 544 O45 8824 544 O214 8824 0 O214 8264 0 5 2 AE r RA4 A4 r RA4 OFF 11464 1568 O45 11464 1568 O45 13464 1568 O10D 13464 1568 OF0 11464 0 5 2 AE r RA5 A4 r RA5 O157 9464 1568 O45 9464 1568 O45 11304 1568 O10D 11304 1568 OF0 9464 0 5 2 AE r R4E4 "PDin38" A4 r R4E4 O11C 21544 736 O45 21544 736 O45 22664 736 O211 22664 736 O130 21544 0 5 2 AE r R188 A4 r R188 O143 25624 288 O45 25624 288 O45 26824 288 O10A 26824 0 O248 A9 32 3776 A6 AB 0 25624 288 3 2 AE r R4E5 "HINT" A4 r R4E5 O202 0 3300 O45 6344 3296 O249 A9 32 764 A6 AB 0 6344 3300 9 2 AE r R4E6 "/0(MiChip)/5(DataMux)*1.[28][1]" A4 r R4E6 O148 20904 928 O45 24504 928 O45 20904 928 O45 25064 928 O45 25544 928 O20D 25544 928 OEB 24504 0 OEB 25064 0 OEB 20904 0 5 2 AE r R4E7 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[6]" A4 r R4E7 O11F 26104 3424 O45 26104 3424 O45 27464 3424 O24A A9 32 3456 A6 AB 0 27464 0 O24A 26104 0 5 2 AE r R316 A4 r R316 O24B A9 15336 24 A6 AA 0 17464 3812 O45 17464 3808 O45 23704 3808 O217 23704 3812 O24C A9 32 3836 A6 AB 0 17464 0 5 2 AE r R18A A4 r R18A O157 11384 2400 O45 11384 2400 O45 13224 2400 OF7 13224 2400 O112 11384 0 5 2 AE r R4E8 "PDout11" A4 r R4E8 O24D A9 8776 24 A6 AA 0 0 420 O45 4184 416 O45 8744 416 O220 8744 0 O220 4184 0 7 2 AE r R4E9 "/0(MiChip)*1.[4]" A4 r R4E9 O233 5544 2592 O45 12904 2592 O45 5544 2592 O45 17784 2592 O10F 17784 0 O128 12904 2592 O10F 5544 0 5 2 AE r R318 A4 r R318 O10B 18744 2912 O45 18744 2912 O45 20424 2912 O105 20424 2912 O215 18744 0 5 2 AE r R3F8 A4 r R3F8 OFF 4584 3744 O45 4584 3744 O45 6584 3744 O10A 6584 3744 O248 4584 0 5 2 AE r R24E A4 r R24E O24E A9 12112 32 A6 AA 0 15464 2208 O45 15464 2208 O45 27544 2208 O121 27544 2208 O11B 15464 0 3 2 AE r R3F9 A4 r R3F9 O24F A9 24216 24 A6 AA 0 8584 3876 O45 8584 3872 O250 A9 32 3900 A6 AB 0 8584 0 5 2 AE r R3FA A4 r R3FA O157 21384 3680 O45 21384 3680 O45 23224 3680 O251 A9 32 3712 A6 AB 0 23224 0 OF4 21384 3680 5 2 AE r R4EA "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21).[2]" A4 r R4EA O252 A9 9472 32 A6 AA 0 11144 4000 O45 11144 4000 O45 20584 4000 O253 A9 32 4032 A6 AB 0 20584 0 OEE 11144 4000 5 2 AE r R4EB "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[1]" A4 r R4EB OFF 27784 608 O45 27784 608 O45 29784 608 O24A 29784 608 O119 27784 0 5 2 AE r R31D A4 r R31D O11F 12184 1632 O45 12184 1632 O45 13544 1632 O112 13544 1632 OF7 12184 0 5 2 AE r R31E A4 r R31E O1D1 4024 4000 O45 4024 4000 O45 10584 4000 O253 10584 0 OEE 4024 4000 5 2 AE r R3FB A4 r R3FB O117 18024 1312 O45 18024 1312 O45 20104 1312 O1D5 20104 1312 O114 18024 0 5 2 AE r R4EC "PDout22" A4 r R4EC O254 A9 9656 24 A6 AA 0 0 292 O45 6104 288 O45 9624 288 O228 9624 0 O228 6104 0 5 2 AE r R18F A4 r R18F OFC 17544 3360 O45 17544 3360 O45 22264 3360 O11D 22264 3360 O226 17544 0 5 2 AE r R4ED "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[12]" A4 r R4ED O180 29944 352 O45 29944 352 O45 30344 352 OF4 30344 0 OF4 29944 0 5 2 AE r R4EE "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21).[2]" A4 r R4EE O111 17224 2400 O45 17224 2400 O45 18504 2400 O112 18504 0 OF7 17224 2400 5 2 AE r RB6 A4 r RB6 O156 4904 352 O45 4904 352 O45 11944 352 OF4 11944 0 O251 4904 352 5 2 AE r R255 A4 r R255 O18F 12104 2976 O45 12104 2976 O45 15384 2976 OF1 15384 2976 O206 12104 0 3 2 AE r R4EF "PDout1" A4 r R4EF O255 A9 4856 24 A6 AA 0 0 3620 O45 4824 3616 O220 4824 3620 5 2 AE r R4F0 "Din10" A4 r R4F0 O256 A9 2136 24 A6 AA 0 30664 356 O45 30664 352 O45 32744 352 O257 A9 32 3708 A6 AB 0 32744 356 O20C 30664 0 5 2 AE r R4F1 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21).[2]" A4 r R4F1 O22A 8904 416 O45 8904 416 O45 11864 416 O10C 11864 0 O246 8904 416 5 2 AE r R4F2 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[4]" A4 r R4F2 O184 4504 224 O45 4504 224 O45 4664 224 O107 4664 0 O107 4504 0 5 2 AE r R4F3 "PDout23" A4 r R4F3 O258 A9 12616 24 A6 AA 0 0 3236 O45 9544 3232 O45 12584 3232 O201 12584 3236 O259 A9 32 3260 A6 AB 0 9544 0 5 2 AE r R4F4 "PDout2" A4 r R4F4 O25A A9 3176 24 A6 AA 0 0 356 O45 824 352 O45 3144 352 O257 3144 356 O20C 824 0 5 2 AE r R4F5 "/0(MiChip)/7(StatusReg)*1.[16][0]" A4 r R4F5 O184 5544 3552 O45 5544 3552 O45 5704 3552 O25B A9 32 3584 A6 AB 0 5704 0 O13D 5544 3552 5 2 AE r R3FC A4 r R3FC O1B0 744 480 O45 744 480 O45 13704 480 O13D 13704 0 O13D 744 0 5 2 AE r RBD A4 r RBD O25C A9 8696 24 A6 AA 0 24104 548 O45 24104 544 O45 26504 544 O214 26504 0 O25D A9 32 3516 A6 AB 0 24104 548 9 2 AE r R4F6 "/0(MiChip)/7(StatusReg)*1.[16][1]" A4 r R4F6 O25E A9 15872 32 A6 AA 0 6744 1120 O45 7304 1120 O45 6744 1120 O45 17944 1120 O45 22584 1120 O105 22584 0 O105 7304 0 O105 17944 0 O215 6744 1120 5 2 AE r RBE A4 r RBE O103 16504 3360 O45 16504 3360 O45 17064 3360 O11D 17064 3360 O226 16504 0 3 2 AE r R3FD A4 r R3FD O25F A9 1416 24 A6 AA 0 0 228 O45 1384 224 O217 1384 0 5 2 AE r R3FE A4 r R3FE OF5 11304 1504 O45 11304 1504 O45 12824 1504 O116 12824 1504 O100 11304 0 5 2 AE r RC0 A4 r RC0 O12A 11704 928 O45 11704 928 O45 13624 928 O20D 13624 928 OEB 11704 0 3 2 AE r R4F7 "PDout24" A4 r R4F7 O260 A9 9096 24 A6 AA 0 0 3812 O45 9064 3808 O217 9064 3812 3 2 AE r R400 A4 r R400 O261 A9 10136 24 A6 AA 0 0 100 O45 10104 96 O124 10104 0 5 2 AE r R25C A4 r R25C O117 12984 1440 O45 12984 1440 O45 15064 1440 O10F 15064 1440 O128 12984 0 5 2 AE r R4F8 "PDout8" A4 r R4F8 O262 A9 14456 24 A6 AA 0 0 3684 O45 1624 3680 O45 14424 3680 O20C 14424 3684 O257 1624 0 5 2 AE r R4F9 "/0(MiChip)/2(MemCtlA)/36(fsmc1)/0(Decoder)*1.nnAd[0]" A4 r R4F9 O263 A9 2352 32 A6 AA 0 5224 864 O45 5224 864 O45 7544 864 O159 7544 0 O159 5224 0 5 2 AE r RC2 A4 r RC2 O18F 15384 2912 O45 15384 2912 O45 18664 2912 O105 18664 2912 O215 15384 0 5 2 AE r R196 A4 r R196 O264 A9 17896 24 A6 AA 0 14904 3492 O45 14904 3488 O45 15544 3488 O214 15544 3492 O25D 14904 0 5 2 AE r RC4 A4 r RC4 O18C 24664 480 O45 24664 480 O45 25464 480 O25B 25464 480 O13D 24664 0 3 2 AE r R4FA "PDout9" A4 r R4FA O265 A9 14936 24 A6 AA 0 0 3940 O45 14904 3936 O124 14904 3940 5 2 AE r R198 A4 r R198 O266 A9 26296 24 A6 AA 0 6504 1060 O45 6504 1056 O45 13304 1056 O267 A9 32 1084 A6 AB 0 13304 0 O267 6504 0 5 2 AE r R401 A4 r R401 O129 27384 288 O45 27384 288 O45 30744 288 O248 30744 288 O10A 27384 0 5 2 AE r R4FB "PDout15" A4 r R4FB O1D8 0 3556 O45 5064 3552 O45 5384 3552 O235 5384 3556 O268 A9 32 3580 A6 AB 0 5064 0 3 2 AE r R403 A4 r R403 O269 A9 4296 24 A6 AA 0 28504 484 O45 28504 480 O235 28504 0 7 2 AE r R324 A4 r R324 O26A A9 18856 24 A6 AA 0 13944 36 O45 31464 32 O45 13944 32 O45 21624 32 O26B A9 32 4028 A6 AB 0 21624 36 O136 31464 0 O136 13944 0 3 2 AE r R4FC "PDout25" A4 r R4FC O26C A9 11256 24 A6 AA 0 0 1508 O45 11224 1504 O186 11224 1508 3 2 AE r R261 A4 r R261 O262 18344 2596 O45 18344 2592 O137 18344 0 3 2 AE r R4FD "CLOCKOUT" A4 r R4FD O22C 0 3876 O45 2504 3872 O1B4 2504 3876 5 2 AE r RCA A4 r RCA O26D A9 20536 24 A6 AA 0 12264 3300 O45 12264 3296 O45 17064 3296 O26E A9 32 3324 A6 AB 0 17064 0 O249 12264 3300 5 2 AE r R262 A4 r R262 O161 7864 672 O45 7864 672 O45 9624 672 O226 9624 672 O11D 7864 0 5 2 AE r RCB A4 r RCB O26F A9 24376 24 A6 AA 0 8424 3556 O45 8424 3552 O45 14264 3552 O268 14264 0 O235 8424 3556 5 2 AE r R325 A4 r R325 O1BD 10344 1312 O45 10344 1312 O45 15144 1312 O1D5 15144 1312 O114 10344 0 5 2 AE r RCF A4 r RCF O270 A9 11816 24 A6 AA 0 20984 4004 O45 20984 4000 O45 21064 4000 O26B 21064 0 O136 20984 4004 5 2 AE r R405 A4 r R405 O15C 4104 224 O45 4104 224 O45 4344 224 O107 4344 0 O271 A9 32 3840 A6 AB 0 4104 224 5 2 AE r R19F A4 r R19F O141 15144 1248 O45 15144 1248 O45 17384 1248 O1CF 17384 1248 OFD 15144 0 7 2 AE r R4FE "/0(MiChip)/5(DataMux)*1.[39][1]" A4 r R4FE O272 A9 17792 32 A6 AA 0 2504 1824 O45 13384 1824 O45 2504 1824 O45 20264 1824 O121 20264 0 O11B 13384 1824 O121 2504 0 5 2 AE r R1A1 A4 r R1A1 O273 A9 15632 32 A6 AA 0 9864 288 O45 9864 288 O45 25464 288 O10A 25464 0 O248 9864 288 3 2 AE r R1A0 A4 r R1A0 O135 3224 36 O136 3224 0 O26B 3224 36 3 2 AE r R4FF "PDout26" A4 r R4FF O274 A9 1976 24 A6 AA 0 0 3492 O45 1944 3488 O214 1944 3492 5 2 AE r R406 A4 r R406 O11F 10264 2848 O45 10264 2848 O45 11624 2848 O223 11624 0 O127 10264 2848 5 2 AE r RD5 A4 r RD5 O12E 31224 288 O45 31224 288 O45 31944 288 O248 31944 288 O10A 31224 0 5 2 AE r R408 A4 r R408 O148 8664 2912 O45 8664 2912 O45 13304 2912 O105 13304 2912 O215 8664 0 9 2 AE r R326 A4 r R326 O275 A9 11632 32 A6 AA 0 17304 2976 O45 18504 2976 O45 17304 2976 O45 23944 2976 O45 28904 2976 O206 28904 0 OF1 18504 2976 OF1 23944 2976 O206 17304 0 5 2 AE r R500 "PDout36" A4 r R500 O15A 16984 1440 O45 16984 1440 O45 19864 1440 O10F 19864 1440 O128 16984 0 5 2 AE r R266 A4 r R266 O125 20664 544 O45 20664 544 O45 23384 544 O276 A9 32 3520 A6 AB 0 23384 544 O102 20664 0 5 2 AE r R409 A4 r R409 O157 9944 2976 O45 9944 2976 O45 11784 2976 O206 11784 0 OF1 9944 2976 5 2 AE r R501 "/0(MiChip)/5(DataMux)*1.[23][4]" A4 r R501 O129 8184 928 O45 8184 928 O45 11544 928 OEB 11544 0 O20D 8184 928 3 2 AE r R40A A4 r R40A O277 A9 5976 24 A6 AA 0 0 36 O45 5944 32 O136 5944 0 5 2 AE r R327 A4 r R327 O15C 16424 2976 O45 16424 2976 O45 16664 2976 O206 16664 0 OF1 16424 2976 5 2 AE r R40B A4 r R40B O118 1464 3168 O45 1464 3168 O45 1784 3168 O159 1784 3168 O1FF 1464 0 5 2 AE r R40C A4 r R40C O1D3 18264 2144 O45 18264 2144 O45 27544 2144 O13E 27544 0 O12F 18264 2144 7 2 AE r R502 "Din14" A4 r R502 O278 A9 12376 24 A6 AA 0 20424 100 O45 32184 96 O45 20424 96 O45 29384 96 O124 29384 0 O279 A9 32 3964 A6 AB 0 32184 100 O124 20424 0 3 2 AE r R503 "PDout27" A4 r R503 O1F3 0 3748 O45 2424 3744 O228 2424 3748 5 2 AE r RDA A4 r RDA O111 5944 928 O45 5944 928 O45 7224 928 OEB 7224 0 O20D 5944 928 5 2 AE r RDB A4 r RDB O11C 18904 2016 O45 18904 2016 O45 20024 2016 O13A 20024 2016 O13A 18904 0 5 2 AE r R328 A4 r R328 O157 10184 3296 O45 10184 3296 O45 12024 3296 O130 12024 3296 O211 10184 0 5 2 AE r R504 "PDout37" A4 r R504 O263 14424 3616 O45 14424 3616 O45 16744 3616 O10C 16744 3616 O246 14424 0 5 2 AE r R40F A4 r R40F O15F 13144 3232 O45 13144 3232 O45 16744 3232 O205 16744 0 O22 13144 3232 5 2 AE r R505 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/2(Or6).Two" A4 r R505 O180 28184 736 O45 28184 736 O45 28584 736 O130 28584 0 O130 28184 0 5 2 AE r R410 A4 r R410 O12E 26584 1248 O45 26584 1248 O45 27304 1248 OFD 27304 0 O1CF 26584 1248 5 2 AE r R506 "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)*1.[3]" A4 r R506 O118 824 672 O45 824 672 O45 1144 672 O11D 1144 0 O226 824 672 5 2 AE r R1A3 A4 r R1A3 O27A A9 29816 24 A6 AA 0 2984 164 O45 2984 160 O45 31064 160 O250 31064 164 O1B4 2984 0 5 2 AE r R507 "/0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)*1.[3]" A4 r R507 O1F5 9144 544 O45 9144 544 O45 19624 544 O102 19624 0 O102 9144 0 5 2 AE r R32A A4 r R32A OFF 9384 2464 O45 9384 2464 O45 11384 2464 OF0 11384 2464 O10D 9384 0 5 2 AE r R508 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21).[2]" A4 r R508 O15C 14104 480 O45 14104 480 O45 14344 480 O13D 14344 0 O13D 14104 0 9 2 AE r R32C A4 r R32C O1E5 12344 1696 O45 22104 1696 O45 12344 1696 O45 26344 1696 O45 27064 1696 OEC 27064 0 O109 22104 1696 OEC 26344 0 OEC 12344 0 3 2 AE r R509 "PDout19" A4 r R509 O27B A9 6536 24 A6 AA 0 0 3428 O45 6504 3424 O203 6504 3428 5 2 AE r R50A "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11).Two" A4 r R50A O103 27704 480 O45 27704 480 O45 28264 480 O13D 28264 0 O25B 27704 480 5 2 AE r RE0 A4 r RE0 O15B 10504 3808 O45 10504 3808 O45 12984 3808 O107 12984 3808 O271 10504 0 5 2 AE r R50B "/0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)*1.[5]" A4 r R50B O1D6 14744 1632 O45 14744 1632 O45 19704 1632 OF7 19704 0 O112 14744 1632 3 2 AE r R413 A4 r R413 OFB 4264 4000 OEE 4344 4000 O253 4264 0 5 2 AE r R50C "/0(MiChip)*1.DatParErr" A4 r R50C O12E 21944 480 O45 21944 480 O45 22664 480 O13D 22664 0 O25B 21944 480 5 2 AE r R1A5 A4 r R1A5 O27C A9 27896 24 A6 AA 0 4904 228 O45 4904 224 O45 5464 224 O24C 5464 228 O217 4904 0 5 2 AE r R50D "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21).[2]" A4 r R50D O197 1544 224 O45 1544 224 O45 3144 224 O107 3144 0 O107 1544 0 5 2 AE r R414 A4 r R414 O161 7784 3360 O45 7784 3360 O45 9544 3360 O11D 9544 3360 O226 7784 0 5 2 AE r R1A6 A4 r R1A6 O17C 6264 3488 O45 6264 3488 O45 13944 3488 O102 13944 3488 O276 6264 0 5 2 AE r R26A A4 r R26A OF5 22264 1504 O45 22264 1504 O45 23784 1504 O116 23784 1504 O100 22264 0 5 2 AE r R32E A4 r R32E O183 19544 2720 O45 19544 2720 O45 27864 2720 O114 27864 2720 O1D5 19544 0 7 2 AE r R50E "Dout14" A4 r R50E O27D A9 25816 24 A6 AA 0 6984 3748 O45 28024 3744 O45 6984 3744 O45 18744 3744 O228 18744 3748 O27E A9 32 3772 A6 AB 0 28024 0 O27E 6984 0 5 2 AE r R32F A4 r R32F O179 19384 2848 O45 19384 2848 O45 28264 2848 O127 28264 2848 O223 19384 0 7 2 AE r R1A9 A4 r R1A9 O181 6904 3104 O45 7304 3104 O45 6904 3104 O45 29544 3104 OEB 29544 3104 OEB 7304 3104 O20D 6904 0 5 2 AE r R1AA A4 r R1AA O11C 23304 3680 O45 23304 3680 O45 24424 3680 OF4 24424 3680 O251 23304 0 5 2 AE r R1AB A4 r R1AB O1D4 17624 3232 O45 17624 3232 O45 30504 3232 O22 30504 3232 O205 17624 0 7 2 AE r RE5 A4 r RE5 O27F A9 7952 32 A6 AA 0 11144 2720 O45 16584 2720 O45 11144 2720 O45 19064 2720 O1D5 19064 0 O114 16584 2720 O1D5 11144 0 5 2 AE r R26C A4 r R26C O117 19464 2464 O45 19464 2464 O45 21544 2464 OF0 21544 2464 O10D 19464 0 5 2 AE r R416 A4 r R416 O222 7064 3424 O45 7064 3424 O45 15784 3424 O119 15784 3424 O24A 7064 0 5 2 AE r R417 A4 r R417 O15C 2344 160 O45 2344 160 O45 2584 160 O10E 2584 0 O280 A9 32 3904 A6 AB 0 2344 160 5 2 AE r R336 A4 r R336 O197 11224 1440 O45 11224 1440 O45 12824 1440 O128 12824 0 O128 11224 0 5 2 AE r R418 A4 r R418 O113 21304 2912 O45 21304 2912 O45 28664 2912 O215 28664 0 O105 21304 2912 5 2 AE r R419 A4 r R419 O161 6184 3552 O45 6184 3552 O45 7944 3552 O25B 7944 0 O13D 6184 3552 5 2 AE r R337 A4 r R337 O131 13064 3808 O45 13064 3808 O45 16504 3808 O107 16504 3808 O271 13064 0 3 2 AE r R41A A4 r R41A OFB 7064 4000 O253 7144 0 OEE 7064 4000 3 2 AE r R1AE A4 r R1AE OFB 5784 4000 OEE 5864 4000 O253 5784 0 5 2 AE r R50F "/0(MiChip)/7(StatusReg)*1.[20]" A4 r R50F O1BB 17864 1248 O45 17864 1248 O45 22744 1248 OFD 22744 0 OFD 17864 0 5 2 AE r R510 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21).[2]" A4 r R510 O281 A9 7472 32 A6 AA 0 6024 32 O45 6024 32 O45 13464 32 OEE 13464 0 OEE 6024 0 5 2 AE r R1B0 A4 r R1B0 O282 A9 13552 32 A6 AA 0 18104 2784 O45 18104 2784 O45 31624 2784 OFD 31624 2784 O1CF 18104 0 3 2 AE r R511 "PDin2" A4 r R511 O283 A9 3576 24 A6 AA 0 0 4004 O45 3544 4000 O26B 3544 0 5 2 AE r R1B1 A4 r R1B1 O18C 14504 2912 O45 14504 2912 O45 15304 2912 O105 15304 2912 O215 14504 0 5 2 AE r R33C A4 r R33C OF2 1224 800 O45 1224 800 O45 1704 800 O205 1704 800 O22 1224 0 5 2 AE r R41C A4 r R41C O161 14584 3680 O45 14584 3680 O45 16344 3680 OF4 16344 3680 O251 14584 0 11 2 AE r R33D A4 r R33D O284 A9 8832 32 A6 AA 0 12184 2272 O45 13224 2272 O45 16424 2272 O45 12184 2272 O45 15464 2272 O45 20984 2272 OF3 20984 0 OF3 13224 0 O14D 15464 2272 OF3 16424 0 O14D 12184 2272 5 2 AE r R512 "/0(MiChip)/2(MemCtlA)*1.[44]" A4 r R512 O111 12904 2464 O45 12904 2464 O45 14184 2464 OF0 14184 2464 O10D 12904 0 5 2 AE r R1B2 A4 r R1B2 O125 11064 672 O45 11064 672 O45 13784 672 O11D 13784 0 O226 11064 672 9 2 AE r R33E A4 r R33E O284 12344 1760 O45 13384 1760 O45 12344 1760 O45 15624 1760 O45 21144 1760 O14D 21144 0 O14D 13384 0 OF3 15624 1760 OF3 12344 1760 5 2 AE r R41D A4 r R41D O285 A9 6512 32 A6 AA 0 13864 1568 O45 13864 1568 O45 20344 1568 OF0 20344 0 O10D 13864 1568 7 2 AE r R513 "/0(MiChip)/2(MemCtlA)*1.DataCy" A4 r R513 O15F 16184 96 O45 18984 96 O45 16184 96 O45 19784 96 O286 A9 32 3968 A6 AB 0 19784 96 OFA 18984 0 OFA 16184 0 5 2 AE r R514 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[13]" A4 r R514 O143 20024 1440 O45 20024 1440 O45 21224 1440 O10F 21224 1440 O128 20024 0 5 2 AE r R340 A4 r R340 O14A 22024 3424 O45 22024 3424 O45 26024 3424 O24A 26024 0 O24A 22024 0 3 2 AE r R341 A4 r R341 O135 2744 36 O136 2744 0 O26B 2744 36 5 2 AE r R275 A4 r R275 O144 24584 672 O45 24584 672 O45 28504 672 O226 28504 672 O11D 24584 0 5 2 AE r R515 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[6]" A4 r R515 O143 10264 2528 O45 10264 2528 O45 11464 2528 O100 11464 2528 O116 10264 0 5 2 AE r R420 A4 r R420 O106 15304 2464 O45 15304 2464 O45 18824 2464 OF0 18824 2464 O10D 15304 0 5 2 AE r R41F A4 r R41F O1BC 16664 3680 O45 16664 3680 O45 20504 3680 O251 20504 0 OF4 16664 3680 3 2 AE r R516 "PDin4" A4 r R516 O239 0 740 O45 1144 736 O26E 1144 740 5 2 AE r R517 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[8][0]" A4 r R517 O15B 24264 608 O45 24264 608 O45 26744 608 O119 26744 0 O24A 24264 608 5 2 AE r R422 A4 r R422 O287 A9 3152 32 A6 AA 0 26184 928 O45 26184 928 O45 29304 928 O20D 29304 928 OEB 26184 0 5 2 AE r R423 A4 r R423 OF5 24984 992 O45 24984 992 O45 26504 992 O21E 26504 992 OF6 24984 0 5 2 AE r REE A4 r REE O288 A9 15896 24 A6 AA 0 16904 3940 O45 16904 3936 O45 24744 3936 O279 24744 0 O124 16904 3940 22 2 AE r R1B4 A4 r R1B4 O289 A9 23792 32 A6 AA 0 24 1376 O45 904 1376 O45 7464 1376 O45 19224 1376 O45 24 1376 O45 21304 1376 O45 10344 1376 O45 3304 1376 O45 1784 1376 O45 23784 1376 OFE 23784 0 O1D7 904 1376 OFE 1784 0 O1D7 3304 1376 OFE 3304 0 O1D7 3304 1376 OFE 3304 0 O1D7 7464 1376 O1D7 10344 1376 OFE 19224 0 OFE 21304 0 O1D7 24 1376 3 2 AE r R518 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[0]" A4 r R518 OFB 26904 32 OEE 26984 0 OEE 26904 0 5 2 AE r R27A A4 r R27A O184 2664 160 O45 2664 160 O45 2824 160 O280 2824 160 O10E 2664 0 5 2 AE r R519 "/0(MiChip)/2(MemCtlA)*1.[38]" A4 r R519 O141 15704 1312 O45 15704 1312 O45 17944 1312 O1D5 17944 1312 O114 15704 0 5 2 AE r R51A "/0(MiChip)/5(DataMux)/0(ParGen)*1.[16]" A4 r R51A O1BD 11064 96 O45 11064 96 O45 15864 96 O286 15864 96 OFA 11064 0 5 2 AE r R51B "/0(MiChip)/4(RefreshCtr)*1.[8][7]" A4 r R51B O14B 25864 480 O45 25864 480 O45 26824 480 O25B 26824 480 O13D 25864 0 9 2 AE r RF0 A4 r RF0 O28A A9 25312 32 A6 AA 0 4824 3168 O45 18184 3168 O45 4824 3168 O45 27944 3168 O45 30104 3168 O1FF 30104 0 O159 18184 3168 O1FF 27944 0 O1FF 4824 0 5 2 AE r RF1 A4 r RF1 O162 12584 2848 O45 12584 2848 O45 18104 2848 O127 18104 2848 O223 12584 0 9 2 AE r RF2 A4 r RF2 O28B A9 5632 32 A6 AA 0 25224 3360 O45 29144 3360 O45 25224 3360 O45 30424 3360 O45 30824 3360 O11D 30824 3360 O226 29144 0 O226 30424 0 O226 25224 0 5 2 AE r RF7 A4 r RF7 O111 1704 736 O45 1704 736 O45 2984 736 O211 2984 736 O130 1704 0 5 2 AE r R428 A4 r R428 O1F1 14664 480 O45 14664 480 O45 18424 480 O25B 18424 480 O13D 14664 0 5 2 AE r RB A4 r RB O1F5 12024 352 O45 12024 352 O45 22504 352 O251 22504 352 OF4 12024 0 5 2 AE r R27C A4 r R27C O141 10424 3616 O45 10424 3616 O45 12664 3616 O10C 12664 3616 O246 10424 0 9 2 AE r RF8 A4 r RF8 O28A 4744 2656 O45 18344 2656 O45 4744 2656 O45 27864 2656 O45 30024 2656 O1D7 30024 0 OFE 18344 2656 O1D7 27864 0 O1D7 4744 0 5 2 AE r RFF A4 r RFF O139 23704 480 O45 23704 480 O45 24344 480 O25B 24344 480 O13D 23704 0 5 2 AE r R51C "/0(MiChip)/7(StatusReg)*1.[19]" A4 r R51C O18E 4184 3488 O45 4184 3488 O45 5624 3488 O276 5624 0 O102 4184 3488 7 2 AE r R34C A4 r R34C O28C A9 5792 32 A6 AA 0 22824 1120 O45 26904 1120 O45 22824 1120 O45 28584 1120 O215 28584 1120 O215 26904 1120 O105 22824 0 5 2 AE r R51D "/0(MiChip)/2(MemCtlA)*1.[69]" A4 r R51D O139 4744 3104 O45 4744 3104 O45 5384 3104 O20D 5384 0 OEB 4744 3104 9 2 AE r R34D A4 r R34D O275 17384 1184 O45 18584 1184 O45 17384 1184 O45 24024 1184 O45 28984 1184 O127 28984 0 O223 18584 1184 O223 24024 1184 O127 17384 0 5 2 AE r R101 A4 r R101 O19A 16264 3424 O45 16264 3424 O45 21704 3424 O119 21704 3424 O24A 16264 0 5 2 AE r R51E "/0(MiChip)/4(RefreshCtr)*1.[3][1]" A4 r R51E O184 29704 352 O45 29704 352 O45 29864 352 OF4 29864 0 O251 29704 352 5 2 AE r R280 A4 r R280 O12A 18264 1888 O45 18264 1888 O45 20184 1888 O13E 20184 1888 O12F 18264 0 5 2 AE r R42B A4 r R42B O28D A9 9552 32 A6 AA 0 8504 2784 O45 8504 2784 O45 18024 2784 OFD 18024 2784 O1CF 8504 0 7 2 AE r R103 A4 r R103 O28E A9 27232 32 A6 AA 0 2664 800 O45 13544 800 O45 2664 800 O45 29864 800 O205 29864 800 O22 13544 0 O205 2664 800 5 2 AE r R51F "/0(MiChip)/2(MemCtlA)/9(fsm2p)*1.[3]" A4 r R51F O18F 24824 736 O45 24824 736 O45 28104 736 O211 28104 736 O130 24824 0 5 2 AE r R520 "/0(MiChip)/2(MemCtlA)/9(fsm2p)/0(ffP)*1.[2]" A4 r R520 O161 24904 3680 O45 24904 3680 O45 26664 3680 OF4 26664 3680 O251 24904 0 5 2 AE r R1BC A4 r R1BC O15C 13864 672 O45 13864 672 O45 14104 672 O226 14104 672 O11D 13864 0 9 2 AE r R34F A4 r R34F O1E5 12424 2528 O45 22184 2528 O45 12424 2528 O45 26424 2528 O45 27144 2528 O116 27144 0 O100 22184 2528 O116 26424 0 O116 12424 0 5 2 AE r R282 A4 r R282 O12A 6584 2912 O45 6584 2912 O45 8504 2912 O105 8504 2912 O215 6584 0 5 2 AE r R283 A4 r R283 O15B 6184 2976 O45 6184 2976 O45 8664 2976 OF1 8664 2976 O206 6184 0 5 2 AE r R1BF A4 r R1BF O263 12664 864 O45 12664 864 O45 14984 864 O1FF 14984 864 O159 12664 0 5 2 AE r R107 A4 r R107 O103 22904 352 O45 22904 352 O45 23464 352 O251 23464 352 OF4 22904 0 5 2 AE r R521 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21).[2]" A4 r R521 O28F A9 15392 32 A6 AA 0 5864 736 O45 5864 736 O45 21224 736 O130 21224 0 O130 5864 0 3 2 AE r R353 A4 r R353 OFB 20744 32 O253 20824 32 OEE 20744 0 3 2 AE r R1C2 A4 r R1C2 O135 14024 36 O136 14024 0 O26B 14024 36 5 2 AE r R285 A4 r R285 O28C 17144 2336 O45 17144 2336 O45 22904 2336 OEC 22904 2336 O109 17144 0 5 2 AE r R522 "/0(MiChip)/4(RefreshCtr)*1.[3][5]" A4 r R522 O129 27784 3424 O45 27784 3424 O45 31144 3424 O24A 31144 0 O119 27784 3424 5 2 AE r R42E A4 r R42E O290 A9 4272 32 A6 AA 0 4024 3872 O45 4024 3872 O45 8264 3872 O10E 8264 3872 O280 4024 0 5 2 AE r R354 A4 r R354 O197 15224 3936 O45 15224 3936 O45 16824 3936 OFA 16824 3936 O286 15224 0 5 2 AE r R1C6 A4 r R1C6 O139 22104 1312 O45 22104 1312 O45 22744 1312 O1D5 22744 1312 O114 22104 0 5 2 AE r R432 A4 r R432 O184 5144 736 O45 5144 736 O45 5304 736 O211 5304 736 O130 5144 0 5 2 AE r R1C7 A4 r R1C7 O14B 19304 2080 O45 19304 2080 O45 20264 2080 O11E 20264 2080 O133 19304 0 3 2 AE r R523 "PDin12" A4 r R523 O291 A9 7736 24 A6 AA 0 0 3364 O45 7704 3360 O292 A9 32 700 A6 AB 0 7704 3364 5 2 AE r R524 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][1]" A4 r R524 O157 26584 992 O45 26584 992 O45 28424 992 O21E 28424 992 OF6 26584 0 5 2 AE r R525 "/0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)*1.[3]" A4 r R525 O12E 9944 672 O45 9944 672 O45 10664 672 O11D 10664 0 O11D 9944 0 5 2 AE r R434 A4 r R434 O11C 18184 2848 O45 18184 2848 O45 19304 2848 O127 19304 2848 O223 18184 0 5 2 AE r R356 A4 r R356 O14B 6664 3296 O45 6664 3296 O45 7624 3296 O211 7624 0 O130 6664 3296 5 2 AE r R435 A4 r R435 O293 A9 9816 24 A6 AA 0 22984 3620 O45 22984 3616 O45 28824 3616 O220 28824 3620 O245 22984 0 5 2 AE r R10A A4 r R10A O1B6 13784 1504 O45 13784 1504 O45 20184 1504 O100 20184 0 O116 13784 1504 5 2 AE r R526 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[6]" A4 r R526 O294 A9 4192 32 A6 AA 0 8104 864 O45 8104 864 O45 12264 864 O159 12264 0 O159 8104 0 5 2 AE r R436 A4 r R436 O15A 18584 480 O45 18584 480 O45 21464 480 O25B 21464 480 O13D 18584 0 5 2 AE r R527 "/0(MiChip)/5(DataMux)*1.Select[1]" A4 r R527 O19D 10184 3360 O45 10184 3360 O45 16344 3360 O226 16344 0 O11D 10184 3360 5 2 AE r R359 A4 r R359 O140 9224 3808 O45 9224 3808 O45 10104 3808 O107 10104 3808 O271 9224 0 5 2 AE r R528 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)*1.nInput[5]" A4 r R528 O27F 9304 1184 O45 9304 1184 O45 17224 1184 O127 17224 0 O127 9304 0 3 2 AE r R529 "PDin17" A4 r R529 O295 A9 24056 24 A6 AA 0 0 612 O45 24024 608 O203 24024 0 5 2 AE r R10D A4 r R10D O14A 18824 2400 O45 18824 2400 O45 22824 2400 OF7 22824 2400 O112 18824 0 5 2 AE r R52A "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21).[2]" A4 r R52A O1D9 10024 1248 O45 10024 1248 O45 15064 1248 OFD 15064 0 OFD 10024 0 5 2 AE r R35A A4 r R35A O296 A9 16752 32 A6 AA 0 6344 992 O45 6344 992 O45 23064 992 OF6 23064 0 OF6 6344 0 5 2 AE r R1CA A4 r R1CA OF5 12744 3616 O45 12744 3616 O45 14264 3616 O10C 14264 3616 O246 12744 0 3 2 AE r R52B "PDin19" A4 r R52B O297 A9 296 24 A6 AA 0 0 484 O45 264 480 O268 264 484 3 2 AE r R52C "PDin25" A4 r R52C O298 A9 2056 24 A6 AA 0 0 164 O45 2024 160 O1B4 2024 0 5 2 AE r R35C A4 r R35C O284 14744 672 O45 14744 672 O45 23544 672 O11D 23544 0 O11D 14744 0 5 2 AE r R112 A4 r R112 O111 18664 1952 O45 18664 1952 O45 19944 1952 O133 19944 1952 O11E 18664 0 5 2 AE r R1CC A4 r R1CC O22A 14184 2400 O45 14184 2400 O45 17144 2400 OF7 17144 2400 O112 14184 0 5 2 AE r R52D "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21).[2]" A4 r R52D O1D9 4984 3616 O45 4984 3616 O45 10024 3616 O10C 10024 3616 O246 4984 0 5 2 AE r R1D0 A4 r R1D0 O299 A9 14992 32 A6 AA 0 16584 864 O45 16584 864 O45 31544 864 O1FF 31544 864 O159 16584 0 5 2 AE r R1CE A4 r R1CE O29A A9 6056 24 A6 AA 0 26744 3684 O45 26744 3680 O45 29064 3680 O257 29064 0 O20C 26744 3684 5 2 AE r R52E "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[1]" A4 r R52E O139 6744 672 O45 6744 672 O45 7384 672 O11D 7384 0 O11D 6744 0 3 2 AE r R52F "/0(MiChip)/5(DataMux)*1.[11][8]" A4 r R52F OFB 2824 32 O253 2904 32 OEE 2824 0 7 2 AE r R1D1 A4 r R1D1 O181 6824 3040 O45 7224 3040 O45 6824 3040 O45 29464 3040 OF6 29464 3040 OF6 7224 3040 O21E 6824 0 5 2 AE r R35D A4 r R35D OFF 22184 1440 O45 22184 1440 O45 24184 1440 O10F 24184 1440 O128 22184 0 0 0 18656 0 1 AE r R530 "MIInnerChan7" O29B A2 -32 0 32832 856 166 O24 0 0 0 2 AE r R531 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 784 0 0 2 AE r R532 "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)*1.[3]-7" A1A a A1A O24 880 0 0 2 AE r R533 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 1664 0 0 2 AE r R534 "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)*1.[4]-7" A1A a A1A O18 1744 0 0 2 AE r R535 "/0(MiChip)/5(DataMux)*1.[39][3]-7" A1A a A1A ODD 1840 0 0 2 AE r R536 "/0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 2320 0 0 2 AE r R537 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O16D 2480 0 0 2 AE r R538 "/0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer1" A1A a A1A O18 2704 0 0 2 AE r R539 "/0(MiChip)/5(DataMux)*1.[15][7]-7" A1A a A1A O18 2784 0 0 2 AE r R53A "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)*1.[3]-7" A1A a A1A O18 2864 0 0 2 AE r R53B "/0(MiChip)/5(DataMux)*1.[11][8]-7" A1A a A1A O18 2944 0 0 2 AE r R53C "/0(MiChip)/4(RefreshCtr)*1.[8][9]-7" A1A a A1A O86 3040 0 0 2 AE r R53D "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 3184 0 0 2 AE r R53E "Din13-7" A1A a A1A O24 3280 0 0 2 AE r R53F "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 4064 0 0 2 AE r R540 "/0(MiChip)/5(DataMux)*1.[23][2]-7" A1A a A1A O18 4144 0 0 2 AE r R541 "/0(MiChip)/7(StatusReg)*1.[19]-7" A1A a A1A ODD 4240 0 0 2 AE r R542 "/0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1" A1A a A1A O18 4704 0 0 2 AE r R543 "/0(MiChip)/2(MemCtlA)*1.[69]-7" A1A a A1A ODD 4800 0 0 2 AE r R544 "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1" A1A a A1A O18 5264 0 0 2 AE r R545 "/0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)*1.[3]-7" A1A a A1A O18 5344 0 0 2 AE r R546 "PDout15-7" A1A a A1A O18 5424 0 0 2 AE r R547 "Dout11-7" A1A a A1A O168 5520 0 0 2 AE r R548 "/0(MiChip)/7(StatusReg)/4(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 5824 0 0 2 AE r R549 "/0(MiChip)/5(DataMux)*1.[15][2]-7" A1A a A1A O18 5904 0 0 2 AE r R54A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[6][1]-7" A1A a A1A O29C AD -32 0 432 856 O29D A1B -32 0 432 856 1 1 O29E AD -8 0 456 856 O29F A2 -8 0 456 856 155 OA8 24 752 0 4 A10 r R23 A4 r RC A12 i 59164 A16 lor 1 RC OA9 456 328 2 1 A10 r R23 OA8 24 0 0 4 A10 r R23 A4 r RB A12 i 59162 A16 lor 1 RB O8C 368 280 0 1 A12 i 59160 OA0 208 280 0 1 A12 i 59158 O9F 128 280 0 1 A12 i 59156 O9E 48 280 0 1 A12 i 59154 O31 296 64 2 1 A10 r R3B O97 40 368 0 1 A10 r R3C O97 376 368 0 1 A10 r R3C O45 368 376 0 0 O92 400 368 2 0 O45 208 376 0 0 O92 240 368 2 0 O45 128 376 0 0 O92 160 368 2 0 O45 48 376 0 0 O92 80 368 2 0 O96 376 248 0 0 O96 296 248 0 0 O2A0 A9 264 24 A6 AA 0 56 248 0 0 O30 368 232 0 0 O91 368 224 0 0 O30 368 184 0 0 O91 368 176 0 0 O30 368 136 0 0 O91 368 128 0 0 O30 288 184 0 0 O91 288 176 0 0 O30 288 136 0 0 O91 288 128 0 0 O30 288 88 0 0 O91 288 80 0 0 O30 208 232 0 0 O91 208 224 0 0 O30 208 184 0 0 O91 208 176 0 0 O30 208 136 0 0 O91 208 128 0 0 O30 128 184 0 0 O91 128 176 0 0 O30 128 136 0 0 O91 128 128 0 0 O30 128 88 0 0 O91 128 80 0 0 O30 48 232 0 0 O91 48 224 0 0 O30 48 184 0 0 O91 48 176 0 0 O30 48 136 0 0 O91 48 128 0 0 O16C 376 312 0 0 O90 296 344 0 0 O2A0 56 464 0 0 O3E 368 472 0 0 O92 400 464 2 0 O3E 368 520 0 0 O92 400 512 2 0 O3E 368 568 0 0 O92 400 560 2 0 O3E 368 616 0 0 O92 400 608 2 0 O3E 368 664 0 0 O92 400 656 2 0 O3E 288 520 0 0 O92 320 512 2 0 O3E 288 568 0 0 O92 320 560 2 0 O3E 288 616 0 0 O92 320 608 2 0 O3E 288 664 0 0 O92 320 656 2 0 O3E 288 712 0 0 O92 320 704 2 0 O3E 48 472 0 0 O92 80 464 2 0 O3E 48 520 0 0 O92 80 512 2 0 O3E 48 568 0 0 O92 80 560 2 0 O3E 48 616 0 0 O92 80 608 2 0 O3E 48 664 0 0 O92 80 656 2 0 O20 368 792 0 1 A10 r R23 O1F 368 8 0 1 A10 r R23 O1E 344 8 0 1 A10 r R23 O1D 344 792 0 1 A10 r R23 O41 336 288 0 1 A10 r R3B O31 376 64 2 1 A10 r R3B O78 336 312 0 1 A10 r R3C O93 280 80 0 1 A10 r R3B O93 368 80 0 1 A10 r R3B O94 376 352 2 1 A10 r R3C OA2 288 368 0 1 A10 r R3C O32 308 312 0 1 A10 r R3D OA1 296 312 0 1 A10 r R3D O91 288 368 0 1 A10 r R3D O20 288 792 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O1E 264 8 0 1 A10 r R23 O95 304 312 0 1 A10 r R3D O1D 264 792 0 1 A10 r R23 O41 256 288 0 1 A10 r R3B O78 256 312 0 1 A10 r R3C O93 200 80 0 1 A10 r R3B O93 288 80 0 1 A10 r R3B O94 296 352 2 1 A10 r R3C OA2 208 368 0 1 A10 r R3C OA2 296 368 0 1 A10 r R3C O32 228 312 0 1 A10 r R3D OA1 216 312 0 1 A10 r R3D O91 208 368 0 1 A10 r R3D O20 48 792 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O1E 184 8 0 1 A10 r R23 O95 224 312 0 1 A10 r R3D O1D 184 792 0 1 A10 r R23 O41 176 288 0 1 A10 r R3B O31 216 64 2 1 A10 r R3B O78 176 312 0 1 A10 r R3C O93 120 80 0 1 A10 r R3B O93 208 80 0 1 A10 r R3B O94 216 352 2 1 A10 r R3C OA2 128 368 0 1 A10 r R3C OA2 216 368 0 1 A10 r R3C O32 148 312 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O91 128 368 0 1 A10 r R3D O20 128 792 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O1E 104 8 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1D 104 792 0 1 A10 r R23 O41 96 288 0 1 A10 r R3B O31 136 64 2 1 A10 r R3B O78 96 312 0 1 A10 r R3C O93 40 80 0 1 A10 r R3B O93 128 80 0 1 A10 r R3B O94 136 352 2 1 A10 r R3C OA2 136 368 0 1 A10 r R3C O32 68 312 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O91 48 368 0 1 A10 r R3D O20 208 792 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O1E 24 8 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1D 24 792 0 1 A10 r R23 O22 48 0 0 3 A10 r R23 A12 i 59154 A16 lor 1 R42 O22 128 0 0 3 A10 r R23 A12 i 59156 A16 lor 1 R43 O22 208 0 0 3 A10 r R23 A12 i 59158 A16 lor 1 R44 O22 368 0 0 3 A10 r R23 A12 i 59160 A16 lor 1 R3A O1B 168 16 0 1 A12 i 59162 O1C 248 800 0 1 A12 i 59164 24 0 424 832 R54B "C2OR03A.mask" 1048576000 0 1 2 A28 r R46 A17 i 74751 1 A18 a A19 0 1 A18 a A19 6000 0 0 2 AE r R54C "/0(MiChip)/7(StatusReg)/7(or3)/0(NormalizedOr3)/0(Or3)" A1A a A1A O86 6400 0 0 2 AE r R54D "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 6544 0 0 2 AE r R54E "PDout21-7" A1A a A1A O18 6624 0 0 2 AE r R54F "/0(MiChip)/5(DataMux)*1.Select[0]-7" A1A a A1A O168 6720 0 0 2 AE r R550 "/0(MiChip)/7(StatusReg)/5(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 7024 0 0 2 AE r R551 "/0(MiChip)/5(DataMux)*1.[15][1]-7" A1A a A1A OCE 7120 0 0 2 AE r R552 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver0" A1A a A1A O24 7440 0 0 2 AE r R553 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OA4 8240 0 0 2 AE r R554 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 8624 0 0 2 AE r R555 "/0(MiChip)/7(StatusReg)*1.[14][0]-7" A1A a A1A O86 8720 0 0 2 AE r R556 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 8864 0 0 2 AE r R557 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21).[2]-7" A1A a A1A ODD 8960 0 0 2 AE r R558 "/0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 9424 0 0 2 AE r R559 "PDin36-7" A1A a A1A O18 9504 0 0 2 AE r R55A "PDout39-7" A1A a A1A O18 9584 0 0 2 AE r R55B "PDout35-7" A1A a A1A OA4 9680 0 0 2 AE r R55C "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 10064 0 0 2 AE r R55D "/0(MiChip)/5(DataMux)*1.[11][5]-7" A1A a A1A O86 10160 0 0 2 AE r R55E "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/1(Inv)*1*1*1" A1A a A1A O24 10320 0 0 2 AE r R55F "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 11120 0 0 2 AE r R560 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 11264 0 0 2 AE r R561 "/0(MiChip)*1.RASX-7" A1A a A1A O18 11344 0 0 2 AE r R562 "PDout38-7" A1A a A1A O18 11424 0 0 2 AE r R563 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[6]-7" A1A a A1A ODD 11520 0 0 2 AE r R564 "/0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 11984 0 0 2 AE r R565 "/0(MiChip)/5(DataMux)*1.[23][6]-7" A1A a A1A OA4 12080 0 0 2 AE r R566 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 12480 0 0 2 AE r R567 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 12640 0 0 2 AE r R568 "/0(MiChip)/3(AddrMux)/3(Inv)*1" A1A a A1A O18 12784 0 0 2 AE r R569 "/0(MiChip)/7(StatusReg)*1.[16][2]-7" A1A a A1A O18 12864 0 0 2 AE r R56A "/0(MiChip)*1.[4]-7" A1A a A1A O18 12944 0 0 2 AE r R56B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncount-7" A1A a A1A O86 13040 0 0 2 AE r R56C "/0(MiChip)/5(DataMux)/7(DecoderS)/5(Inv)" A1A a A1A O18 13184 0 0 2 AE r R56D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][4]-7" A1A a A1A O18 13264 0 0 2 AE r R56E "/0(MiChip)/5(DataMux)*1.[23][3]-7" A1A a A1A O18 13344 0 0 2 AE r R56F "/0(MiChip)/5(DataMux)*1.[39][1]-7" A1A a A1A O18 13424 0 0 2 AE r R570 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][4]-7" A1A a A1A O18 13504 0 0 2 AE r R571 "/0(MiChip)/6(AddrCtl)*1.[13]-7" A1A a A1A O18 13584 0 0 2 AE r R572 "Din11-7" A1A a A1A O18 13664 0 0 2 AE r R573 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.nLoad-7" A1A a A1A O18 13744 0 0 2 AE r R574 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.load-7" A1A a A1A O18 13824 0 0 2 AE r R575 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]-7" A1A a A1A O18 13904 0 0 2 AE r R576 "Dout12-7" A1A a A1A O18 13984 0 0 2 AE r R577 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]-7" A1A a A1A O18 14064 0 0 2 AE r R578 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]-7" A1A a A1A O18 14144 0 0 2 AE r R579 "/0(MiChip)/2(MemCtlA)*1.[44]-7" A1A a A1A O18 14224 0 0 2 AE r R57A "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nAd[0]-7" A1A a A1A ODD 14320 0 0 2 AE r R57B "/0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1" A1A a A1A O86 14800 0 0 2 AE r R57C "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 14944 0 0 2 AE r R57D "/0(MiChip)/5(DataMux)*1.[11][0]-7" A1A a A1A OAF 15040 0 0 2 AE r R57E "/0(MiChip)/2(MemCtlA)/20(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 15264 0 0 2 AE r R57F "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two-7" A1A a A1A OA4 15360 0 0 2 AE r R580 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 15744 0 0 2 AE r R581 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[7][0]-7" A1A a A1A ODD 15840 0 0 2 AE r R582 "/0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1" A1A a A1A O18 16304 0 0 2 AE r R583 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[3]-7" A1A a A1A O86 16400 0 0 2 AE r R584 "/0(MiChip)/5(DataMux)/7(DecoderS)/6(Inv)" A1A a A1A O18 16544 0 0 2 AE r R585 "/0(MiChip)/2(MemCtlA)*1.C3-7" A1A a A1A O18 16624 0 0 2 AE r R586 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]-7" A1A a A1A O18 16704 0 0 2 AE r R587 "PDout37-7" A1A a A1A O18 16784 0 0 2 AE r R588 "/0(MiChip)/4(RefreshCtr)*1.[3][13]-7" A1A a A1A O86 16880 0 0 2 AE r R589 "/0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1*1*1" A1A a A1A O18 17024 0 0 2 AE r R58A "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nEnable-7" A1A a A1A O18 17104 0 0 2 AE r R58B "RPadEnb-7" A1A a A1A O86 17200 0 0 2 AE r R58C "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 17344 0 0 2 AE r R58D "Din7-7" A1A a A1A ODD 17440 0 0 2 AE r R58E "/0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1" A1A a A1A O18 17904 0 0 2 AE r R58F "/0(MiChip)/2(MemCtlA)*1.[38]-7" A1A a A1A O18 17984 0 0 2 AE r R590 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv).nEnable-7" A1A a A1A O18 18064 0 0 2 AE r R591 "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)*1.[5]-7" A1A a A1A O18 18144 0 0 2 AE r R592 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv).nEnable-7" A1A a A1A O18 18224 0 0 2 AE r R593 "/0(MiChip)/5(DataMux)/11(DataLatchMux)*1.[4]-7" A1A a A1A O18 18304 0 0 2 AE r R594 "/0(MiChip)*1.LdRefCtr[1]-7" A1A a A1A O18 18384 0 0 2 AE r R595 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[17]-7" A1A a A1A O86 18480 0 0 2 AE r R596 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/1(Inv)" A1A a A1A O18 18624 0 0 2 AE r R597 "Dout6-7" A1A a A1A O18 18704 0 0 2 AE r R598 "Dout14-7" A1A a A1A ODD 18800 0 0 2 AE r R599 "/0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 19280 0 0 2 AE r R59A "/0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 19744 0 0 2 AE r R59B "/0(MiChip)/2(MemCtlA)*1.DataCy-7" A1A a A1A O18 19824 0 0 2 AE r R59C "PDout36-7" A1A a A1A O18 19904 0 0 2 AE r R59D "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv).nEnable-7" A1A a A1A O18 19984 0 0 2 AE r R59E "/0(MiChip)*1.LdAddrHi[1]-7" A1A a A1A O86 20080 0 0 2 AE r R59F "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/1(Inv)*1*1" A1A a A1A O18 20224 0 0 2 AE r R5A0 "/0(MiChip)/3(AddrMux)*1.In1[1]-7" A1A a A1A ODD 20320 0 0 2 AE r R5A1 "/0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OA4 20800 0 0 2 AE r R5A2 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 21184 0 0 2 AE r R5A3 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[13]-7" A1A a A1A O18 21264 0 0 2 AE r R5A4 "/0(MiChip)/5(DataMux)*1.[15][0]-7" A1A a A1A O18 21344 0 0 2 AE r R5A5 "/0(MiChip)/2(MemCtlA)*1.S3-7" A1A a A1A O18 21424 0 0 2 AE r R5A6 "/0(MiChip)/1(ClockGen)*1.[11]-7" A1A a A1A O18 21504 0 0 2 AE r R5A7 "/0(MiChip)/2(MemCtlA)*1.C4B-7" A1A a A1A O18 21584 0 0 2 AE r R5A8 "Din2-7" A1A a A1A O18 21664 0 0 2 AE r R5A9 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[9][1]-7" A1A a A1A O86 21760 0 0 2 AE r R5AA "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv10" A1A a A1A O18 21904 0 0 2 AE r R5AB "/0(MiChip)*1.DatParErr-7" A1A a A1A OCE 22000 0 0 2 AE r R5AC "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver3" A1A a A1A O86 22320 0 0 2 AE r R5AD "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv7" A1A a A1A O86 22480 0 0 2 AE r R5AE "/0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv1" A1A a A1A O18 22624 0 0 2 AE r R5AF "PDin38-7" A1A a A1A O18 22704 0 0 2 AE r R5B0 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][0]-7" A1A a A1A O18 22784 0 0 2 AE r R5B1 "/0(MiChip)*1.LdStatus[0]-7" A1A a A1A ODD 22880 0 0 2 AE r R5B2 "/0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 23344 0 0 2 AE r R5B3 "Dout8-7" A1A a A1A O18 23424 0 0 2 AE r R5B4 "/0(MiChip)/3(AddrMux)*1.In1[0]-7" A1A a A1A O86 23520 0 0 2 AE r R5B5 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv2" A1A a A1A O18 23664 0 0 2 AE r R5B6 "Dout2-7" A1A a A1A O18 23744 0 0 2 AE r R5B7 "Dout13-7" A1A a A1A OCE 23840 0 0 2 AE r R5B8 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver2" A1A a A1A O18 24144 0 0 2 AE r R5B9 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][3]-7" A1A a A1A O18 24224 0 0 2 AE r R5BA "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[8][0]-7" A1A a A1A O18 24304 0 0 2 AE r R5BB "/0(MiChip)/3(AddrMux)*1.In0[0]-7" A1A a A1A O18 24384 0 0 2 AE r R5BC "/0(MiChip)/2(MemCtlA)*1.RefCy-7" A1A a A1A ODD 24480 0 0 2 AE r R5BD "/0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 24960 0 0 2 AE r R5BE "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 25424 0 0 2 AE r R5BF "/0(MiChip)/3(AddrMux)*1.In1[9]-7" A1A a A1A ODD 25520 0 0 2 AE r R5C0 "/0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 26000 0 0 2 AE r R5C1 "/0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 26464 0 0 2 AE r R5C2 "/0(MiChip)/4(RefreshCtr)*1.[8][12]-7" A1A a A1A O18 26544 0 0 2 AE r R5C3 "/0(MiChip)/6(AddrCtl)*1.[19]-7" A1A a A1A O18 26624 0 0 2 AE r R5C4 "/0(MiChip)/2(MemCtlA)/9(fsm2p)/0(ffP)*1.[2]-7" A1A a A1A O18 26704 0 0 2 AE r R5C5 "Dout0-7" A1A a A1A O18 26784 0 0 2 AE r R5C6 "/0(MiChip)/4(RefreshCtr)*1.[8][7]-7" A1A a A1A O24 26880 0 0 2 AE r R5C7 "/0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1" A1A a A1A O18 27664 0 0 2 AE r R5C8 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11).Two-7" A1A a A1A O18 27744 0 0 2 AE r R5C9 "/0(MiChip)/4(RefreshCtr)*1.[3][5]-7" A1A a A1A O171 27840 0 0 2 AE r R5CA "/0(MiChip)/2(MemCtlA)/9(fsm2p)/1(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A OAF 28160 0 0 2 AE r R5CB "/0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 28384 0 0 2 AE r R5CC "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][1]-7" A1A a A1A O18 28464 0 0 2 AE r R5CD "XIRQ0-7" A1A a A1A O24 28560 0 0 2 AE r R5CE "/0(MiChip)/2(MemCtlA)/55(FF)*1" A1A a A1A OCE 29360 0 0 2 AE r R5CF "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver14" A1A a A1A O86 29680 0 0 2 AE r R5D0 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv1" A1A a A1A O24 29840 0 0 2 AE r R5D1 "/0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1*1*1*1*1" A1A a A1A O86 30640 0 0 2 AE r R5D2 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv8" A1A a A1A O24 30800 0 0 2 AE r R5D3 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 31600 0 0 2 AE r R5D4 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv3" A1A a A1A O86 31760 0 0 2 AE r R5D5 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv13" A1A a A1A O24 31920 0 0 2 AE r R5D6 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1" A1A a A1A O18 32704 0 0 2 AE r R5D7 "Din10-7" A1A a A1A 0 0 32800 832 R5D8 "MIInnerIntRow7" 1030701209 0 0 0 0 22720 0 1 AE r R5D9 "Row7" O2A1 A29 0 0 32800 2976 219 0 0 32800 2976 5 2 AE r RA1 A4 r RA1 O2A2 A9 9712 32 A6 AA 0 4024 1056 O45 4024 1056 O45 13704 1056 OF1 13704 0 O12F 4024 1056 5 2 AE r R3F5 A4 r R3F5 OF5 7944 288 O45 7944 288 O45 9464 288 O10A 9464 0 O1D7 7944 288 5 2 AE r R314 A4 r R314 O161 27864 2400 O45 27864 2400 O45 29624 2400 O112 29624 0 O102 27864 2400 5 2 AE r R5DA "/0(MiChip)*1.[51]" A4 r R5DA O118 12744 608 O45 12744 608 O45 13064 608 O119 13064 0 O119 12744 0 5 2 AE r R5DB "PDin37" A4 r R5DB O118 10264 1824 O45 10264 1824 O45 10584 1824 O121 10584 0 O105 10264 1824 5 2 AE r RA4 A4 r RA4 O2A3 A9 1072 32 A6 AA 0 12424 416 O45 12424 416 O45 13464 416 O10C 13464 0 O116 12424 416 5 2 AE r RA5 A4 r RA5 O14B 10344 288 O45 10344 288 O45 11304 288 O10A 11304 0 O1D7 10344 288 3 2 AE r R4E4 A4 r R4E4 O135 22664 36 O136 22664 0 O2A4 A9 32 2940 A6 AB 0 22664 36 5 2 AE r R5DC "/0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)*1.[7]" A4 r R5DC O139 27544 2720 O45 27544 2720 O45 28184 2720 O1D5 28184 0 O107 27544 2720 5 2 AE r R5DD "/0(MiChip)/3(AddrMux)*1.[19][1]" A4 r R5DD O1BB 27784 1504 O45 27784 1504 O45 32664 1504 O100 32664 0 O128 27784 1504 5 2 AE r R316 A4 r R316 O156 23704 1120 O45 23704 1120 O45 30744 1120 O121 30744 1120 O105 23704 0 5 2 AE r R18A A4 r R18A O103 12664 352 O45 12664 352 O45 13224 352 OF4 13224 0 O10F 12664 352 5 2 AE r R4E9 A4 r R4E9 O141 10664 800 O45 10664 800 O45 12904 800 O22 12904 0 O13E 10664 800 5 2 AE r R318 A4 r R318 O2A5 A9 11232 32 A6 AA 0 9224 1504 O45 9224 1504 O45 20424 1504 O100 20424 0 O128 9224 1504 5 2 AE r R3F8 A4 r R3F8 O11C 6584 800 O45 6584 800 O45 7704 800 O13E 7704 800 O22 6584 0 5 2 AE r R24E A4 r R24E O1CD 16264 2656 O45 16264 2656 O45 27544 2656 O1D7 27544 0 O10A 16264 2656 9 2 AE r R5DE "/0(MiChip)/5(DataMux)*1.[28][3]" A4 r R5DE O1C1 744 2848 O45 12104 2848 O45 744 2848 O45 20344 2848 O45 21464 2848 OFA 21464 2848 O223 12104 0 O223 20344 0 O223 744 0 5 2 AE r R3FA A4 r R3FA O22F 16824 1376 O45 16824 1376 O45 21384 1376 OFE 21384 0 OF0 16824 1376 3 2 AE r R5DF "PDout12" A4 r R5DF O2A6 A9 4536 24 A6 AA 0 0 164 O45 4504 160 O1D2 4504 164 5 2 AE r R31E A4 r R31E O2A7 A9 5712 32 A6 AA 0 4024 928 O45 4024 928 O45 9704 928 O13A 9704 928 OEB 4024 0 5 2 AE r R31D A4 r R31D O15C 13304 1888 O45 13304 1888 O45 13544 1888 O12F 13544 0 OF1 13304 1888 5 2 AE r R3FB A4 r R3FB O2A2 20104 480 O45 20104 480 O45 29784 480 O10D 29784 480 O13D 20104 0 5 2 AE r R18F A4 r R18F O1E0 22264 1248 O45 22264 1248 O45 30424 1248 OEC 30424 1248 OFD 22264 0 5 2 AE r R255 A4 r R255 O2A8 A9 6992 32 A6 AA 0 15384 736 O45 15384 736 O45 22344 736 O130 22344 0 O130 15384 0 5 2 AE r R5E0 "/0(MiChip)/5(DataMux)/3(TstBuffer)*1.nInput[1]" A4 r R5E0 O15C 22344 1120 O45 22344 1120 O45 22584 1120 O105 22584 0 O121 22344 1120 5 2 AE r R5E1 "/0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)*1.[3]" A4 r R5E1 O143 23304 1568 O45 23304 1568 O45 24504 1568 OF0 24504 0 OF0 23304 0 5 2 AE r R4EF A4 r R4EF O190 4824 1696 O45 4824 1696 O45 20904 1696 OFD 20904 1696 OEC 4824 0 5 2 AE r R4F1 A4 r R4F1 O2A9 A9 4512 32 A6 AA 0 4424 608 O45 4424 608 O45 8904 608 O119 8904 0 O109 4424 608 5 2 AE r R4F0 A4 r R4F0 O2AA A9 14912 32 A6 AA 0 17864 1824 O45 17864 1824 O45 32744 1824 O121 32744 0 O105 17864 1824 5 2 AE r R4F5 A4 r R4F5 O12A 3624 32 O45 3624 32 O45 5544 32 OEE 5544 0 O215 3624 32 5 2 AE r RBD A4 r RBD OFF 24104 1888 O45 24104 1888 O45 26104 1888 OF1 26104 1888 O12F 24104 0 5 2 AE r R5E2 "PDout4" A4 r R5E2 O2AB A9 17336 24 A6 AA 0 0 1188 O45 17064 1184 O45 17304 1184 O2AC A9 32 1212 A6 AB 0 17304 0 O2AD A9 32 1788 A6 AB 0 17064 1188 5 2 AE r RBE A4 r RBE O140 17064 1056 O45 17064 1056 O45 17944 1056 O12F 17944 1056 OF1 17064 0 5 2 AE r R5E3 "/0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)*1.[5]" A4 r R5E3 O2AE A9 18032 32 A6 AA 0 1704 480 O45 1704 480 O45 19704 480 O13D 19704 0 O10D 1704 480 5 2 AE r R4F7 A4 r R4F7 O15C 8824 1248 O45 8824 1248 O45 9064 1248 OFD 9064 0 OFD 8824 0 5 2 AE r R3FE A4 r R3FE OF2 12344 1952 O45 12344 1952 O45 12824 1952 O11E 12824 0 OF6 12344 1952 5 2 AE r RC0 A4 r RC0 O113 13624 1952 O45 13624 1952 O45 20984 1952 OF6 20984 1952 O11E 13624 0 7 2 AE r R25C A4 r R25C O263 15064 2016 O45 16744 2016 O45 15064 2016 O45 17384 2016 OEB 17384 2016 OEB 16744 2016 O13A 15064 0 5 2 AE r RC2 A4 r RC2 OF2 18184 2016 O45 18184 2016 O45 18664 2016 O13A 18664 0 OEB 18184 2016 3 2 AE r RC4 A4 r RC4 O135 25464 36 O136 25464 0 O2A4 25464 36 5 2 AE r R4FA A4 r R4FA O103 14344 96 O45 14344 96 O45 14904 96 OFA 14904 0 OFA 14344 0 5 2 AE r R4FB A4 r R4FB O18C 4584 160 O45 4584 160 O45 5384 160 O10E 5384 0 O1CF 4584 160 5 2 AE r R324 A4 r R324 O252 21624 864 O45 21624 864 O45 31064 864 O133 31064 864 O159 21624 0 5 2 AE r R5E4 "/0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)*1.[3]" A4 r R5E4 O1D3 2264 416 O45 2264 416 O45 11544 416 O10C 11544 0 O10C 2264 0 5 2 AE r R5E5 "/0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)*1.[5]" A4 r R5E5 O103 24024 32 O45 24024 32 O45 24584 32 OEE 24584 0 O215 24024 32 5 2 AE r R4FC A4 r R4FC O141 8984 608 O45 8984 608 O45 11224 608 O119 11224 0 O119 8984 0 5 2 AE r R4FD A4 r R4FD O11C 1384 96 O45 1384 96 O45 2504 96 OFA 2504 0 O223 1384 96 5 2 AE r R262 A4 r R262 OF2 9144 1632 O45 9144 1632 O45 9624 1632 OF7 9624 0 O114 9144 1632 5 2 AE r RCB A4 r RCB O14B 8424 1760 O45 8424 1760 O45 9384 1760 O127 9384 1760 O14D 8424 0 5 2 AE r R325 A4 r R325 O12E 15144 416 O45 15144 416 O45 15864 416 O116 15864 416 O10C 15144 0 5 2 AE r RCF A4 r RCF O10B 19304 1248 O45 19304 1248 O45 20984 1248 OFD 20984 0 OEC 19304 1248 5 2 AE r R5E6 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21).[2]" A4 r R5E6 O162 3064 224 O45 3064 224 O45 8584 224 O107 8584 0 O107 3064 0 5 2 AE r R405 A4 r R405 O2AF A9 6112 32 A6 AA 0 4104 736 O45 4104 736 O45 10184 736 O11B 10184 736 O130 4104 0 5 2 AE r R19F A4 r R19F O2B0 A9 7872 32 A6 AA 0 17384 1184 O45 17384 1184 O45 25224 1184 O14D 25224 1184 O127 17384 0 5 2 AE r R4FE A4 r R4FE O184 13224 608 O45 13224 608 O45 13384 608 O119 13384 0 O109 13224 608 5 2 AE r R4FF A4 r R4FF O180 1544 352 O45 1544 352 O45 1944 352 OF4 1944 0 O10F 1544 352 5 2 AE r R1A0 A4 r R1A0 O118 3224 736 O45 3224 736 O45 3544 736 O11B 3544 736 O130 3224 0 5 2 AE r R1A1 A4 r R1A1 O2B1 A9 23176 24 A6 AA 0 9624 1764 O45 9624 1760 O45 9864 1760 O2AD 9864 0 O2AC 9624 1764 7 2 AE r R406 A4 r R406 O143 9064 1376 O45 9784 1376 O45 9064 1376 O45 10264 1376 OFE 10264 0 OFE 9784 0 OF0 9064 1376 3 2 AE r R5E7 "Din9" A4 r R5E7 O2B2 A9 21016 24 A6 AA 0 11784 164 O45 11784 160 O1D2 11784 164 5 2 AE r RD5 A4 r RD5 O290 27704 736 O45 27704 736 O45 31944 736 O130 31944 0 O11B 27704 736 5 2 AE r R408 A4 r R408 O290 13304 1632 O45 13304 1632 O45 17544 1632 O114 17544 1632 OF7 13304 0 5 2 AE r R326 A4 r R326 O161 22184 2144 O45 22184 2144 O45 23944 2144 O13E 23944 0 O22 22184 2144 5 2 AE r R266 A4 r R266 O118 23064 1120 O45 23064 1120 O45 23384 1120 O105 23384 0 O121 23064 1120 5 2 AE r R500 A4 r R500 OF2 19384 1632 O45 19384 1632 O45 19864 1632 OF7 19864 0 O114 19384 1632 5 2 AE r R409 A4 r R409 O14B 8984 1824 O45 8984 1824 O45 9944 1824 O121 9944 0 O105 8984 1824 5 2 AE r R501 A4 r R501 O180 7784 32 O45 7784 32 O45 8184 32 OEE 8184 0 O215 7784 32 5 2 AE r R40B A4 r R40B O103 1224 224 O45 1224 224 O45 1784 224 O107 1784 0 O1D5 1224 224 5 2 AE r R5E8 "/0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)*1.[5]" A4 r R5E8 O141 9384 1248 O45 9384 1248 O45 11624 1248 OFD 11624 0 OFD 9384 0 5 2 AE r R40C A4 r R40C O2B3 A9 12032 32 A6 AA 0 18264 1056 O45 18264 1056 O45 30264 1056 O12F 30264 1056 OF1 18264 0 5 2 AE r R503 A4 r R503 O103 1864 224 O45 1864 224 O45 2424 224 O107 2424 0 O107 1864 0 5 2 AE r R502 A4 r R502 O118 31864 2592 O45 31864 2592 O45 32184 2592 O10F 32184 0 OF4 31864 2592 3 2 AE r RDA A4 r RDA OFB 5944 96 O223 6024 96 OFA 5944 0 5 2 AE r RDB A4 r RDB O2B4 A9 4112 32 A6 AA 0 20024 2016 O45 20024 2016 O45 24104 2016 OEB 24104 2016 O13A 20024 0 5 2 AE r R5E9 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21).[2]" A4 r R5E9 O118 20824 1504 O45 20824 1504 O45 21144 1504 O100 21144 0 O128 20824 1504 3 2 AE r R5EA "Dout9" A4 r R5EA O2B5 A9 17176 24 A6 AA 0 15624 100 O45 15624 96 O213 15624 100 5 2 AE r R328 A4 r R328 O12E 11304 608 O45 11304 608 O45 12024 608 O119 12024 0 O109 11304 608 5 2 AE r R504 A4 r R504 O15C 16744 1056 O45 16744 1056 O45 16984 1056 O12F 16984 1056 OF1 16744 0 3 2 AE r R5EB "PDout18" A4 r R5EB O2B6 A9 5096 24 A6 AA 0 0 292 O45 5064 288 O1DB 5064 292 5 2 AE r R40F A4 r R40F O15A 13144 800 O45 13144 800 O45 16024 800 O13E 16024 800 O22 13144 0 5 2 AE r R5EC "/0(MiChip)/5(DataMux)*1.[23][7]" A4 r R5EC O180 9704 288 O45 9704 288 O45 10104 288 O1D7 10104 288 O10A 9704 0 5 2 AE r R5ED "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21).[2]" A4 r R5ED O139 14184 2144 O45 14184 2144 O45 14824 2144 O13E 14824 0 O22 14184 2144 5 2 AE r R410 A4 r R410 O12E 26584 736 O45 26584 736 O45 27304 736 O11B 27304 736 O130 26584 0 3 2 AE r R506 A4 r R506 O2B7 A9 352 32 A6 AB 0 824 32 O215 1144 32 OEE 824 0 5 2 AE r R1A3 A4 r R1A3 O14B 30104 480 O45 30104 480 O45 31064 480 O13D 31064 0 O10D 30104 480 3 2 AE r R5EE "PDout28" A4 r R5EE O2B8 A9 12856 24 A6 AA 0 0 2020 O45 12824 2016 O2B9 A9 32 956 A6 AB 0 12824 2020 5 2 AE r R5EF "/0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)*1.[3]" A4 r R5EF O18C 3464 608 O45 3464 608 O45 4264 608 O119 4264 0 O109 3464 608 5 2 AE r R32A A4 r R32A O139 10744 928 O45 10744 928 O45 11384 928 OEB 11384 0 O13A 10744 928 5 2 AE r R509 A4 r R509 O131 3064 800 O45 3064 800 O45 6504 800 O22 6504 0 O13E 3064 800 5 2 AE r R32C A4 r R32C O14B 21144 1568 O45 21144 1568 O45 22104 1568 OF0 22104 0 OFE 21144 1568 5 2 AE r R5F0 "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)*1.[5]" A4 r R5F0 O14B 4264 864 O45 4264 864 O45 5224 864 O159 5224 0 O133 4264 864 5 2 AE r R50A A4 r R50A O2A3 27704 544 O45 27704 544 O45 28744 544 O112 28744 544 O102 27704 0 5 2 AE r RE0 A4 r RE0 O180 12584 1248 O45 12584 1248 O45 12984 1248 OFD 12984 0 OEC 12584 1248 3 2 AE r R5F1 "Dout10" A4 r R5F1 O29A 26744 1572 O45 26744 1568 O2BA A9 32 1404 A6 AB 0 26744 1572 5 2 AE r R50C A4 r R50C O12A 21944 1376 O45 21944 1376 O45 23864 1376 OF0 23864 1376 OFE 21944 0 5 2 AE r R5F2 "/0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)*1.[5]" A4 r R5F2 OF2 17864 1632 O45 17864 1632 O45 18344 1632 O114 18344 1632 OF7 17864 0 5 2 AE r R1A5 A4 r R1A5 OF5 5464 160 O45 5464 160 O45 6984 160 O1CF 6984 160 O10E 5464 0 5 2 AE r R414 A4 r R414 OF5 8024 800 O45 8024 800 O45 9544 800 O22 9544 0 O13E 8024 800 5 2 AE r R1A6 A4 r R1A6 O26A 13944 612 O45 13944 608 O45 19704 608 O2BB A9 32 2364 A6 AB 0 19704 612 O203 13944 0 5 2 AE r R26A A4 r R26A O139 23784 1952 O45 23784 1952 O45 24424 1952 OF6 24424 1952 O11E 23784 0 5 2 AE r R5F3 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21).[2]" A4 r R5F3 O184 8744 1376 O45 8744 1376 O45 8904 1376 OF0 8904 1376 OFE 8744 0 5 2 AE r R32E A4 r R32E O2BC A9 10752 32 A6 AA 0 17144 2336 O45 17144 2336 O45 27864 2336 O109 27864 0 O119 17144 2336 5 2 AE r R50E A4 r R50E O1BC 18744 1888 O45 18744 1888 O45 22584 1888 OF1 22584 1888 O12F 18744 0 5 2 AE r R32F A4 r R32F O1D3 18984 352 O45 18984 352 O45 28264 352 OF4 28264 0 O10F 18984 352 5 2 AE r R5F4 "Dout15" A4 r R5F4 O2BD A9 25416 24 A6 AA 0 7384 1444 O45 7384 1440 O45 12504 1440 O2BE A9 32 1532 A6 AB 0 12504 1444 O207 7384 0 5 2 AE r R1A9 A4 r R1A9 O11C 29544 544 O45 29544 544 O45 30664 544 O112 30664 544 O102 29544 0 3 2 AE r R1AA A4 r R1AA OFB 24424 1632 O114 24504 1632 OF7 24424 0 5 2 AE r R1AB A4 r R1AB O140 29624 2464 O45 29624 2464 O45 30504 2464 O10D 30504 0 O13D 29624 2464 5 2 AE r RE5 A4 r RE5 O15B 16584 800 O45 16584 800 O45 19064 800 O13E 19064 800 O22 16584 0 7 2 AE r R26C A4 r R26C O2BF A9 13152 32 A6 AA 0 16344 672 O45 21544 672 O45 16344 672 O45 29464 672 OF3 29464 672 O11D 21544 0 OF3 16344 672 7 2 AE r R416 A4 r R416 O2C0 A9 7152 32 A6 AA 0 15784 2208 O45 19784 2208 O45 15784 2208 O45 22904 2208 O130 22904 2208 O130 19784 2208 O11B 15784 0 5 2 AE r R5F5 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21).[2]" A4 r R5F5 O2C1 A9 3232 32 A6 AA 0 12504 1376 O45 12504 1376 O45 15704 1376 OFE 15704 0 OFE 12504 0 5 2 AE r R5F6 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[2]" A4 r R5F6 O131 22984 736 O45 22984 736 O45 26424 736 O130 26424 0 O130 22984 0 5 2 AE r R418 A4 r R418 O104 15304 1120 O45 15304 1120 O45 21304 1120 O105 21304 0 O121 15304 1120 5 2 AE r R337 A4 r R337 O103 15944 1376 O45 15944 1376 O45 16504 1376 OFE 16504 0 OF0 15944 1376 5 2 AE r R41A A4 r R41A O15C 7064 32 O45 7064 32 O45 7304 32 O215 7304 32 OEE 7064 0 5 2 AE r R1AE A4 r R1AE O111 5864 864 O45 5864 864 O45 7144 864 O133 7144 864 O159 5864 0 5 2 AE r R5F7 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[3]" A4 r R5F7 O1DC 17464 2400 O45 17464 2400 O45 24984 2400 O112 24984 0 O102 17464 2400 5 2 AE r R5F8 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[2]" A4 r R5F8 O1CD 4664 1312 O45 4664 1312 O45 15944 1312 O114 15944 0 O114 4664 0 5 2 AE r R1B0 A4 r R1B0 O2C2 A9 25792 32 A6 AA 0 5864 992 O45 5864 992 O45 31624 992 OF6 31624 0 O11E 5864 992 5 2 AE r R1B1 A4 r R1B1 O111 15304 1056 O45 15304 1056 O45 16584 1056 O12F 16584 1056 OF1 15304 0 5 2 AE r R33C A4 r R33C O180 1304 416 O45 1304 416 O45 1704 416 O10C 1704 0 O116 1304 416 5 2 AE r R41C A4 r R41C O18E 16344 416 O45 16344 416 O45 17784 416 O116 17784 416 O10C 16344 0 5 2 AE r R33D A4 r R33D O2C3 A9 2432 32 A6 AA 0 9784 1632 O45 9784 1632 O45 12184 1632 OF7 12184 0 O114 9784 1632 5 2 AE r R512 A4 r R512 O2C4 A9 7232 32 A6 AA 0 14184 2080 O45 14184 2080 O45 21384 2080 O159 21384 2080 O133 14184 0 5 2 AE r R5F9 "/0(MiChip)/2(MemCtlA)*1.[25]" A4 r R5F9 O2C5 A9 2192 32 A6 AA 0 25784 1312 O45 25784 1312 O45 27944 1312 O114 27944 0 OF7 25784 1312 5 2 AE r R33E A4 r R33E O2C3 9944 1888 O45 9944 1888 O45 12344 1888 O12F 12344 0 OF1 9944 1888 7 2 AE r R41D A4 r R41D O1DC 6344 1120 O45 11384 1120 O45 6344 1120 O45 13864 1120 O105 13864 0 O121 11384 1120 O121 6344 1120 5 2 AE r R513 A4 r R513 O103 19224 2016 O45 19224 2016 O45 19784 2016 O13A 19784 0 OEB 19224 2016 5 2 AE r R514 A4 r R514 O2A3 21224 1696 O45 21224 1696 O45 22264 1696 OFD 22264 1696 OEC 21224 0 5 2 AE r R5FA "/0(MiChip)/7(StatusReg)*1.[12]" A4 r R5FA O140 6104 32 O45 6104 32 O45 6984 32 OEE 6984 0 OEE 6104 0 5 2 AE r R341 A4 r R341 O184 2744 224 O45 2744 224 O45 2904 224 O1D5 2904 224 O107 2744 0 5 2 AE r R275 A4 r R275 O11C 27384 32 O45 27384 32 O45 28504 32 OEE 28504 0 O215 27384 32 5 2 AE r R5FB "/0(MiChip)/5(DataMux)/0(ParGen)*1.[7]" A4 r R5FB O28B 11944 288 O45 11944 288 O45 17544 288 O10A 17544 0 O10A 11944 0 5 2 AE r R515 A4 r R515 O139 10824 1376 O45 10824 1376 O45 11464 1376 OFE 11464 0 OF0 10824 1376 5 2 AE r R41F A4 r R41F O2C6 A9 5232 32 A6 AA 0 11464 1824 O45 11464 1824 O45 16664 1824 O121 16664 0 O105 11464 1824 5 2 AE r R5FC "/0(MiChip)/7(StatusReg)*1.[15]" A4 r R5FC O15C 5784 32 O45 5784 32 O45 6024 32 OEE 6024 0 OEE 5784 0 3 2 AE r R517 A4 r R517 O135 24264 36 O136 24264 0 O2A4 24264 36 5 2 AE r R5FD "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)*1.[3]" A4 r R5FD O139 24744 1312 O45 24744 1312 O45 25384 1312 O114 25384 0 OF7 24744 1312 5 2 AE r R423 A4 r R423 O118 26504 544 O45 26504 544 O45 26824 544 O112 26824 544 O102 26504 0 5 2 AE r R5FE "/0(MiChip)/5(DataMux)/0(ParGen)*1.[9]" A4 r R5FE O10B 15784 2272 O45 15784 2272 O45 17464 2272 OF3 17464 0 O11D 15784 2272 5 2 AE r REE A4 r REE O118 16904 1824 O45 16904 1824 O45 17224 1824 O105 17224 1824 O121 16904 0 5 2 AE r R5FF "/0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)*1.[3]" A4 r R5FF O2C7 A9 5312 32 A6 AA 0 20744 544 O45 20744 544 O45 26024 544 O102 26024 0 O102 20744 0 3 2 AE r R1B4 A4 r R1B4 O2B7 24 32 O215 344 32 OEE 24 0 3 2 AE r R600 "/0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)*1.[5]" A4 r R600 O135 18904 36 O136 18904 0 O2A4 18904 36 5 2 AE r R27A A4 r R27A OF5 2824 352 O45 2824 352 O45 4344 352 O10F 4344 352 OF4 2824 0 5 2 AE r R519 A4 r R519 O15C 17704 288 O45 17704 288 O45 17944 288 O10A 17944 0 O1D7 17704 288 5 2 AE r R51B A4 r R51B O111 25544 416 O45 25544 416 O45 26824 416 O10C 26824 0 O116 25544 416 5 2 AE r RF0 A4 r RF0 O120 15544 1888 O45 15544 1888 O45 18184 1888 O12F 18184 0 OF1 15544 1888 5 2 AE r RF1 A4 r RF1 O2C8 A9 6752 32 A6 AA 0 18104 416 O45 18104 416 O45 24824 416 O116 24824 416 O10C 18104 0 5 2 AE r RF2 A4 r RF2 O2C9 A9 19312 32 A6 AA 0 11544 928 O45 11544 928 O45 30824 928 OEB 30824 0 O13A 11544 928 5 2 AE r R601 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21).[2]" A4 r R601 O104 6424 352 O45 6424 352 O45 12424 352 OF4 12424 0 OF4 6424 0 5 2 AE r RF7 A4 r RF7 O140 2984 96 O45 2984 96 O45 3864 96 O223 3864 96 OFA 2984 0 5 2 AE r R602 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[10]" A4 r R602 O14A 21864 800 O45 21864 800 O45 25864 800 O13E 25864 800 O22 21864 0 5 2 AE r R428 A4 r R428 O2CA A9 3712 32 A6 AA 0 18424 2144 O45 18424 2144 O45 22104 2144 O22 22104 2144 O13E 18424 0 5 2 AE r RB A4 r RB O140 21624 2080 O45 21624 2080 O45 22504 2080 O133 22504 0 O159 21624 2080 5 2 AE r R603 "/0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)*1.[5]" A4 r R603 O184 25944 800 O45 25944 800 O45 26104 800 O22 26104 0 O22 25944 0 5 2 AE r RF8 A4 r RF8 O15A 15464 1248 O45 15464 1248 O45 18344 1248 OFD 18344 0 OEC 15464 1248 5 2 AE r R604 "/0(MiChip)/2(MemCtlA)*1.[78]" A4 r R604 OF2 15224 2144 O45 15224 2144 O45 15704 2144 O22 15704 2144 O13E 15224 0 5 2 AE r RFF A4 r RFF O2CB A9 2592 32 A6 AA 0 24344 1376 O45 24344 1376 O45 26904 1376 OF0 26904 1376 OFE 24344 0 5 2 AE r R51C A4 r R51C O180 3784 864 O45 3784 864 O45 4184 864 O159 4184 0 O133 3784 864 3 2 AE r R51D A4 r R51D O135 4744 36 O136 4744 0 O2A4 4744 36 5 2 AE r R34C A4 r R34C O15C 28584 32 O45 28584 32 O45 28824 32 O215 28824 32 OEE 28584 0 5 2 AE r R605 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[13]" A4 r R605 O11F 30504 2528 O45 30504 2528 O45 31864 2528 O116 31864 0 O10C 30504 2528 5 2 AE r R101 A4 r R101 O157 19864 2464 O45 19864 2464 O45 21704 2464 O10D 21704 0 O13D 19864 2464 5 2 AE r R606 "/0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)*1.[4]" A4 r R606 OF5 25624 1184 O45 25624 1184 O45 27144 1184 O127 27144 0 O14D 25624 1184 5 2 AE r R607 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[11]" A4 r R607 O184 19224 800 O45 19224 800 O45 19384 800 O22 19384 0 O22 19224 0 5 2 AE r R608 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[14]" A4 r R608 O161 27624 416 O45 27624 416 O45 29384 416 O10C 29384 0 O116 27624 416 5 2 AE r R609 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[3]" A4 r R609 OF2 21544 1120 O45 21544 1120 O45 22024 1120 O105 22024 0 O121 21544 1120 5 2 AE r R60A "/0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)*1.nInput[2]" A4 r R60A O15C 23624 32 O45 23624 32 O45 23864 32 OEE 23864 0 OEE 23624 0 3 2 AE r R60B "PDin9" A4 r R60B O2CC A9 8376 24 A6 AA 0 0 1636 O45 8344 1632 O2CD A9 32 1340 A6 AB 0 8344 1636 5 2 AE r R42B A4 r R42B O2CE A9 12352 32 A6 AA 0 18024 288 O45 18024 288 O45 30344 288 O1D7 30344 288 O10A 18024 0 7 2 AE r R280 A4 r R280 O2CF A9 12592 32 A6 AA 0 8344 1568 O45 20184 1568 O45 8344 1568 O45 20904 1568 OF0 20904 0 OF0 20184 0 OF0 8344 0 5 2 AE r R103 A4 r R103 O282 2664 672 O45 2664 672 O45 16184 672 OF3 16184 672 O11D 2664 0 5 2 AE r R520 A4 r R520 OFF 24664 32 O45 24664 32 O45 26664 32 OEE 26664 0 O215 24664 32 5 2 AE r R1BC A4 r R1BC O15C 14104 352 O45 14104 352 O45 14344 352 O10F 14344 352 OF4 14104 0 5 2 AE r R282 A4 r R282 O2CF 8504 864 O45 8504 864 O45 21064 864 O159 21064 0 O159 8504 0 5 2 AE r R34F A4 r R34F O14B 21224 1952 O45 21224 1952 O45 22184 1952 O11E 22184 0 OF6 21224 1952 5 2 AE r R283 A4 r R283 O161 8664 224 O45 8664 224 O45 10424 224 O1D5 10424 224 O107 8664 0 5 2 AE r R1BF A4 r R1BF O15F 14984 352 O45 14984 352 O45 18584 352 O10F 18584 352 OF4 14984 0 5 2 AE r R107 A4 r R107 O141 23464 1696 O45 23464 1696 O45 25704 1696 OFD 25704 1696 OEC 23464 0 5 2 AE r R353 A4 r R353 O263 18504 1312 O45 18504 1312 O45 20824 1312 O114 20824 0 OF7 18504 1312 5 2 AE r R1C2 A4 r R1C2 O15C 14024 1056 O45 14024 1056 O45 14264 1056 O12F 14264 1056 OF1 14024 0 7 2 AE r R60C "/0(MiChip)/7(StatusReg)*1.[14][2]" A4 r R60C O143 5624 288 O45 5944 288 O45 5624 288 O45 6824 288 O10A 6824 0 O1D7 5944 288 O10A 5624 0 5 2 AE r R42E A4 r R42E O1E6 8264 32 O45 8264 32 O45 23544 32 OEE 23544 0 OEE 8264 0 5 2 AE r R522 A4 r R522 O139 27144 1376 O45 27144 1376 O45 27784 1376 OFE 27784 0 OF0 27144 1376 5 2 AE r R354 A4 r R354 O18E 16824 1312 O45 16824 1312 O45 18264 1312 OF7 18264 1312 O114 16824 0 5 2 AE r R432 A4 r R432 O180 4904 352 O45 4904 352 O45 5304 352 OF4 5304 0 O10F 4904 352 5 2 AE r R1C6 A4 r R1C6 O157 22744 1312 O45 22744 1312 O45 24584 1312 OF7 24584 1312 O114 22744 0 5 2 AE r R1C7 A4 r R1C7 O15B 20264 1632 O45 20264 1632 O45 22744 1632 O114 22744 1632 OF7 20264 0 5 2 AE r R60D "/0(MiChip)/5(DataMux)/12(ParGen)*1.[17]" A4 r R60D O184 24904 416 O45 24904 416 O45 25064 416 O10C 25064 0 O10C 24904 0 5 2 AE r R524 A4 r R524 OFF 26424 800 O45 26424 800 O45 28424 800 O22 28424 0 O13E 26424 800 5 2 AE r R60E "/0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)*1.[3]" A4 r R60E O19A 16264 2592 O45 16264 2592 O45 21704 2592 OF4 21704 2592 O10F 16264 0 5 2 AE r R60F "/0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)*1.[4]" A4 r R60F O161 28344 352 O45 28344 352 O45 30104 352 OF4 30104 0 OF4 28344 0 5 2 AE r R434 A4 r R434 O2D0 A9 17712 32 A6 AA 0 1624 544 O45 1624 544 O45 19304 544 O102 19304 0 O102 1624 0 5 2 AE r R356 A4 r R356 O180 6264 1248 O45 6264 1248 O45 6664 1248 OFD 6664 0 OEC 6264 1248 5 2 AE r R10A A4 r R10A O2D1 A9 9872 32 A6 AA 0 3944 96 O45 3944 96 O45 13784 96 OFA 13784 0 O223 3944 96 5 2 AE r R359 A4 r R359 O15A 7224 160 O45 7224 160 O45 10104 160 O10E 10104 0 O1CF 7224 160 5 2 AE r R527 A4 r R527 O18C 10184 160 O45 10184 160 O45 10984 160 O1CF 10984 160 O10E 10184 0 5 2 AE r R610 "/0(MiChip)/4(RefreshCtr)*1.[3][8]" A4 r R610 O14B 29704 416 O45 29704 416 O45 30664 416 O10C 30664 0 O116 29704 416 3 2 AE r R611 "PDin21" A4 r R611 O283 0 36 O45 3544 32 O136 3544 0 5 2 AE r R436 A4 r R436 OF5 19944 2720 O45 19944 2720 O45 21464 2720 O1D5 21464 0 O107 19944 2720 3 2 AE r R612 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[0]" A4 r R612 OFB 7064 96 OFA 7144 0 O223 7064 96 5 2 AE r R10D A4 r R10D O2D2 A9 2832 32 A6 AA 0 20024 2912 O45 20024 2912 O45 22824 2912 O215 22824 0 OEE 20024 2912 3 2 AE r R613 "PDin18" A4 r R613 O2D3 A9 616 24 A6 AA 0 0 100 O45 584 96 O213 584 100 5 2 AE r R1CA A4 r R1CA O2D4 A9 3072 32 A6 AA 0 11224 736 O45 11224 736 O45 14264 736 O130 14264 0 O11B 11224 736 5 2 AE r R614 "/0(MiChip)*1.XIRQ1" A4 r R614 O15C 31544 2336 O45 31544 2336 O45 31784 2336 O109 31784 0 O119 31544 2336 5 2 AE r R615 "/0(MiChip)/7(StatusReg)*1.[14][7]" A4 r R615 O2A3 20744 800 O45 20744 800 O45 21784 800 O22 21784 0 O13E 20744 800 3 2 AE r R616 "HOSTRESET" A4 r R616 O2D5 A9 22296 24 A6 AA 0 10504 228 O45 10504 224 O1DE 10504 228 5 2 AE r R1CC A4 r R1CC OF2 16664 2144 O45 16664 2144 O45 17144 2144 O13E 17144 0 O22 16664 2144 5 2 AE r R112 A4 r R112 O14A 19944 2528 O45 19944 2528 O45 23944 2528 O10C 23944 2528 O116 19944 0 5 2 AE r R617 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)*1.nInput[7]" A4 r R617 O11F 21064 1312 O45 21064 1312 O45 22424 1312 O114 22424 0 OF7 21064 1312 5 2 AE r R1CE A4 r R1CE O19A 21304 1504 O45 21304 1504 O45 26744 1504 O100 26744 0 O128 21304 1504 5 2 AE r R1D0 A4 r R1D0 O2BF 18424 2272 O45 18424 2272 O45 31544 2272 OF3 31544 0 O11D 18424 2272 3 2 AE r R52F A4 r R52F OFB 2904 160 O1CF 2984 160 O10E 2904 0 5 2 AE r R1D1 A4 r R1D1 O11C 29464 32 O45 29464 32 O45 30584 32 O215 30584 32 OEE 29464 0 5 2 AE r R35D A4 r R35D OFF 24184 1632 O45 24184 1632 O45 26184 1632 O114 26184 1632 OF7 24184 0 3 2 AE r R618 "PDin28" A4 r R618 O2D6 A9 28216 24 A6 AA 0 0 2788 O45 28184 2784 O1B4 28184 2788 5 2 AE r R619 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[3]" A4 r R619 OF5 30184 352 O45 30184 352 O45 31704 352 OF4 31704 0 O10F 30184 352 0 0 23552 0 1 AE r R61A "MIInnerChan8" O2D7 A2 0 0 32800 864 163 O2D8 A2 0 0 320 832 2 O2D9 A2 0 0 320 80 1 O2DA A9 320 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 320 80 R2 1059061760 0 0 0 0 0 0 0 O2DB A2 0 0 320 80 1 O2DA 0 0 0 2 A4 r RC AE r RC 0 0 320 80 R2 1059061760 0 0 0 0 752 0 0 0 0 320 832 R61B "MIInnerLeft8" 1031153506 0 1 0 0 0 0 0 O24 320 0 0 2 AE r R61C "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 1104 0 0 2 AE r R61D "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)*1.[3]-8" A1A a A1A O18 1184 0 0 2 AE r R61E "/0(MiChip)/5(DataMux)*1.[39][3]-8" A1A a A1A O18 1264 0 0 2 AE r R61F "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)*1.[4]-8" A1A a A1A O18 1344 0 0 2 AE r R620 "CLOCKOUT-8" A1A a A1A O86 1440 0 0 2 AE r R621 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 1600 0 0 2 AE r R622 "/0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 2080 0 0 2 AE r R623 "/0(MiChip)/5(DataMux)/15(FF)*1" A1A a A1A O18 2864 0 0 2 AE r R624 "/0(MiChip)/5(DataMux)*1.[15][7]-8" A1A a A1A O18 2944 0 0 2 AE r R625 "/0(MiChip)/5(DataMux)*1.[11][8]-8" A1A a A1A ODD 3040 0 0 2 AE r R626 "/0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1" A1A a A1A O18 3504 0 0 2 AE r R627 "Din13-8" A1A a A1A OCA 3600 0 0 2 AE r R628 "/0(MiChip)/7(StatusReg)/0(ffrs1)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A OA4 3840 0 0 2 AE r R629 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1*1*1*1*1" A1A a A1A O18 4224 0 0 2 AE r R62A "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)*1.[5]-8" A1A a A1A O18 4304 0 0 2 AE r R62B "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)*1.[3]-8" A1A a A1A O86 4400 0 0 2 AE r R62C "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 4544 0 0 2 AE r R62D "PDout15-8" A1A a A1A OAF 4640 0 0 2 AE r R62E "/0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 4864 0 0 2 AE r R62F "/0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)*1.[3]-8" A1A a A1A O86 4960 0 0 2 AE r R630 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 5120 0 0 2 AE r R631 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 5904 0 0 2 AE r R632 "/0(MiChip)/7(StatusReg)*1.[14][2]-8" A1A a A1A OCA 6000 0 0 2 AE r R633 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0(counterCLP2NL)/2(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O86 6240 0 0 2 AE r R634 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/1(Inv)*1*1*1*1*1" A1A a A1A O168 6400 0 0 2 AE r R635 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/0(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A OCE 6720 0 0 2 AE r R636 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver4" A1A a A1A O18 7024 0 0 2 AE r R637 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[0]-8" A1A a A1A O18 7104 0 0 2 AE r R638 "/0(MiChip)/5(DataMux)*1.[15][2]-8" A1A a A1A O18 7184 0 0 2 AE r R639 "/0(MiChip)/5(DataMux)*1.[11][5]-8" A1A a A1A O18 7264 0 0 2 AE r R63A "/0(MiChip)/5(DataMux)*1.[15][1]-8" A1A a A1A OCA 7360 0 0 2 AE r R63B "/0(MiChip)/7(StatusReg)/3(ffrs1)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O86 7600 0 0 2 AE r R63C "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 7760 0 0 2 AE r R63D "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv4" A1A a A1A O18 7904 0 0 2 AE r R63E "PDin36-8" A1A a A1A O18 7984 0 0 2 AE r R63F "PDout39-8" A1A a A1A O24 8080 0 0 2 AE r R640 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 8864 0 0 2 AE r R641 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21).[2]-8" A1A a A1A O18 8944 0 0 2 AE r R642 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]-8" A1A a A1A O18 9024 0 0 2 AE r R643 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]-8" A1A a A1A O18 9104 0 0 2 AE r R644 "PDout35-8" A1A a A1A OA4 9200 0 0 2 AE r R645 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 9584 0 0 2 AE r R646 "Din8-8" A1A a A1A OA4 9680 0 0 2 AE r R647 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 10064 0 0 2 AE r R648 "/0(MiChip)/5(DataMux)*1.[23][7]-8" A1A a A1A O18 10144 0 0 2 AE r R649 "/0(MiChip)/5(DataMux)*1.[23][2]-8" A1A a A1A O18 10224 0 0 2 AE r R64A "PDin37-8" A1A a A1A O18 10304 0 0 2 AE r R64B "/0(MiChip)*1.RASX-8" A1A a A1A O98 10400 0 0 2 AE r R64C "/0(MiChip)/7(StatusReg)/3(ffrs1)/1(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O18 10704 0 0 2 AE r R64D "PDout38-8" A1A a A1A O18 10784 0 0 2 AE r R64E "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[6]-8" A1A a A1A O168 10880 0 0 2 AE r R64F "/0(MiChip)/5(DataMux)/8(DataLatchMux)/0(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 11184 0 0 2 AE r R650 "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)*1.nAd[0]-8" A1A a A1A O18 11264 0 0 2 AE r R651 "/0(MiChip)/5(DataMux)*1.[23][6]-8" A1A a A1A O86 11360 0 0 2 AE r R652 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/0(Inv)*1*1*1*1*1" A1A a A1A O24 11520 0 0 2 AE r R653 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 12304 0 0 2 AE r R654 "/0(MiChip)/7(StatusReg)*1.[16][2]-8" A1A a A1A O18 12384 0 0 2 AE r R655 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][4]-8" A1A a A1A O18 12464 0 0 2 AE r R656 "Dout15-8" A1A a A1A O18 12544 0 0 2 AE r R657 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncount-8" A1A a A1A O18 12624 0 0 2 AE r R658 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][4]-8" A1A a A1A ODD 12720 0 0 2 AE r R659 "/0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 13184 0 0 2 AE r R65A "/0(MiChip)/5(DataMux)*1.[39][1]-8" A1A a A1A O18 13264 0 0 2 AE r R65B "/0(MiChip)/6(AddrCtl)*1.[13]-8" A1A a A1A O24 13360 0 0 2 AE r R65C "/0(MiChip)/2(MemCtlA)/51(FF)*1" A1A a A1A O18 14144 0 0 2 AE r R65D "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21).[2]-8" A1A a A1A O18 14224 0 0 2 AE r R65E "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]-8" A1A a A1A O18 14304 0 0 2 AE r R65F "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]-8" A1A a A1A O86 14400 0 0 2 AE r R660 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv6" A1A a A1A O24 14560 0 0 2 AE r R661 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 15360 0 0 2 AE r R662 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver6" A1A a A1A O18 15664 0 0 2 AE r R663 "/0(MiChip)/2(MemCtlA)*1.[78]-8" A1A a A1A O18 15744 0 0 2 AE r R664 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[9]-8" A1A a A1A O18 15824 0 0 2 AE r R665 "/0(MiChip)/2(MemCtlA)*1.WrHCy-8" A1A a A1A OCA 15920 0 0 2 AE r R666 "/0(MiChip)/5(DataMux)/7(DecoderS)/2(NormalizedNor2)/0(Nor2)" A1A a A1A O18 16144 0 0 2 AE r R667 "/0(MiChip)*1.[27][2]-8" A1A a A1A O171 16240 0 0 2 AE r R668 "/0(MiChip)/2(MemCtlA)/29(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O18 16544 0 0 2 AE r R669 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two-8" A1A a A1A O18 16624 0 0 2 AE r R66A "RPadEnb-8" A1A a A1A OCA 16720 0 0 2 AE r R66B "/0(MiChip)/2(MemCtlA)/15(ffrs1)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 16944 0 0 2 AE r R66C "PDout37-8" A1A a A1A O18 17024 0 0 2 AE r R66D "PDout4-8" A1A a A1A O98 17120 0 0 2 AE r R66E "/0(MiChip)/2(MemCtlA)/15(ffrs1)/1(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A O18 17424 0 0 2 AE r R66F "/0(MiChip)/5(DataMux)/12(ParGen)*1.[3]-8" A1A a A1A O86 17520 0 0 2 AE r R670 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv3" A1A a A1A O18 17664 0 0 2 AE r R671 "/0(MiChip)/2(MemCtlA)*1.[38]-8" A1A a A1A O18 17744 0 0 2 AE r R672 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[3]-8" A1A a A1A O18 17824 0 0 2 AE r R673 "Din10-8" A1A a A1A O18 17904 0 0 2 AE r R674 "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nEnable-8" A1A a A1A O86 18000 0 0 2 AE r R675 "/0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1*1*1*1*1*1*1*1" A1A a A1A O18 18144 0 0 2 AE r R676 "Dout6-8" A1A a A1A O18 18224 0 0 2 AE r R677 "/0(MiChip)/4(RefreshCtr)*1.[3][13]-8" A1A a A1A O18 18304 0 0 2 AE r R678 "/0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)*1.[5]-8" A1A a A1A O18 18384 0 0 2 AE r R679 "/0(MiChip)/4(RefreshCtr)*1.[3].Cin-8" A1A a A1A ODD 18480 0 0 2 AE r R67A "/0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 18944 0 0 2 AE r R67B "/0(MiChip)/2(MemCtlA)*1.C0-8" A1A a A1A O86 19040 0 0 2 AE r R67C "/0(MiChip)/2(MemCtlA)/35(Inv)*1" A1A a A1A O18 19184 0 0 2 AE r R67D "/0(MiChip)/2(MemCtlA)*1.DataCy-8" A1A a A1A O18 19264 0 0 2 AE r R67E "Din6-8" A1A a A1A O18 19344 0 0 2 AE r R67F "PDout36-8" A1A a A1A OCE 19440 0 0 2 AE r R680 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver3" A1A a A1A O86 19760 0 0 2 AE r R681 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/2/0(Inv)*1" A1A a A1A O18 19904 0 0 2 AE r R682 "/0(MiChip)/1(ClockGen)*1.[11]-8" A1A a A1A O24 20000 0 0 2 AE r R683 "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple10//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple9//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple8//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple7//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 20800 0 0 2 AE r R684 "/0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 20944 0 0 2 AE r R685 "Din11-8" A1A a A1A OCE 21040 0 0 2 AE r R686 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver7" A1A a A1A O18 21344 0 0 2 AE r R687 "/0(MiChip)/2(MemCtlA)*1.[44]-8" A1A a A1A O86 21440 0 0 2 AE r R688 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv3" A1A a A1A O18 21584 0 0 2 AE r R689 "Gnd-8" A1A a A1A ODD 21680 0 0 2 AE r R68A "/0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1" A1A a A1A O18 22144 0 0 2 AE r R68B "/0(MiChip)/5(DataMux)/6(DataLatchMux)*1.[4]-8" A1A a A1A O18 22224 0 0 2 AE r R68C "/0(MiChip)/5(DataMux)/0(ParGen)*1.[13]-8" A1A a A1A OCE 22320 0 0 2 AE r R68D "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver1" A1A a A1A O18 22624 0 0 2 AE r R68E "PDin38-8" A1A a A1A O18 22704 0 0 2 AE r R68F "/0(MiChip)/3(AddrMux)*1.In1[1]-8" A1A a A1A OAF 22800 0 0 2 AE r R690 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/2/1(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 23024 0 0 2 AE r R691 "Dout8-8" A1A a A1A O24 23120 0 0 2 AE r R692 "/0(MiChip)/5(DataMux)/14(FF)*1" A1A a A1A O18 23904 0 0 2 AE r R693 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv).nEnable-8" A1A a A1A O18 23984 0 0 2 AE r R694 "/0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)*1.[5]-8" A1A a A1A O18 24064 0 0 2 AE r R695 "/0(MiChip)*1.LdAddrHi[1]-8" A1A a A1A OAF 24160 0 0 2 AE r R696 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/2/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 24384 0 0 2 AE r R697 "Dout13-8" A1A a A1A O18 24464 0 0 2 AE r R698 "/0(MiChip)/2(MemCtlA)*1.RefCy-8" A1A a A1A O18 24544 0 0 2 AE r R699 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][0]-8" A1A a A1A O18 24624 0 0 2 AE r R69A "/0(MiChip)/2(MemCtlA)/9(fsm2p)/0(ffP)*1.[2]-8" A1A a A1A ODD 24720 0 0 2 AE r R69B "/0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 25184 0 0 2 AE r R69C "Din7-8" A1A a A1A O86 25280 0 0 2 AE r R69D "/0(MiChip)/2(MemCtlA)/12(fsmc1)/0(Decoder)/2(Inv)" A1A a A1A O18 25424 0 0 2 AE r R69E "/0(MiChip)/3(AddrMux)*1.In1[9]-8" A1A a A1A O18 25504 0 0 2 AE r R69F "/0(MiChip)/4(RefreshCtr)*1.[8][7]-8" A1A a A1A O18 25584 0 0 2 AE r R6A0 "/0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)*1.[4]-8" A1A a A1A O18 25664 0 0 2 AE r R6A1 "/0(MiChip)/3(AddrMux)*1.In1[0]-8" A1A a A1A O18 25744 0 0 2 AE r R6A2 "/0(MiChip)/2(MemCtlA)*1.[25]-8" A1A a A1A OCE 25840 0 0 2 AE r R6A3 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver10" A1A a A1A OCA 26160 0 0 2 AE r R6A4 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/3/1(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 26384 0 0 2 AE r R6A5 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][1]-8" A1A a A1A OCE 26480 0 0 2 AE r R6A6 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver5" A1A a A1A O18 26784 0 0 2 AE r R6A7 "/0(MiChip)/4(RefreshCtr)*1.[8][12]-8" A1A a A1A O18 26864 0 0 2 AE r R6A8 "/0(MiChip)/3(AddrMux)*1.In0[0]-8" A1A a A1A O86 26960 0 0 2 AE r R6A9 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/1(Inv)" A1A a A1A O86 27120 0 0 2 AE r R6AA "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv5" A1A a A1A O18 27264 0 0 2 AE r R6AB "/0(MiChip)/6(AddrCtl)*1.[19]-8" A1A a A1A O18 27344 0 0 2 AE r R6AC "XIRQ0-8" A1A a A1A O86 27440 0 0 2 AE r R6AD "/0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1*1*1*1*1" A1A a A1A O18 27584 0 0 2 AE r R6AE "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[14]-8" A1A a A1A O18 27664 0 0 2 AE r R6AF "/0(MiChip)*1.LdAddrHi[0]-8" A1A a A1A O18 27744 0 0 2 AE r R6B0 "/0(MiChip)/3(AddrMux)*1.[19][1]-8" A1A a A1A O18 27824 0 0 2 AE r R6B1 "Dout1-8" A1A a A1A O24 27920 0 0 2 AE r R6B2 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 28704 0 0 2 AE r R6B3 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11).Two-8" A1A a A1A O24 28800 0 0 2 AE r R6B4 "/0(MiChip)/2(MemCtlA)/44(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/43(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 29584 0 0 2 AE r R6B5 "/0(MiChip)/2(MemCtlA)*1.C1-8" A1A a A1A O18 29664 0 0 2 AE r R6B6 "/0(MiChip)/4(RefreshCtr)*1.[3][8]-8" A1A a A1A O168 29760 0 0 2 AE r R6B7 "/0(MiChip)/5(DataMux)/2(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 30064 0 0 2 AE r R6B8 "Din15-8" A1A a A1A OCE 30160 0 0 2 AE r R6B9 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver3" A1A a A1A OCE 30480 0 0 2 AE r R6BA "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver13" A1A a A1A O24 30800 0 0 2 AE r R6BB "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple13//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple12//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple11//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple10//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple9//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple8//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple7//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 31600 0 0 2 AE r R6BC "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O2DC A2 0 0 400 832 2 O2DD A2 0 0 400 80 1 O2DE A9 400 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 400 80 R2 1059061760 0 0 0 0 0 0 0 O2DF A2 0 0 400 80 1 O2DE 0 0 0 2 A4 r RC AE r RC 0 0 400 80 R2 1059061760 0 0 0 0 752 0 0 0 0 400 832 R6BD "MIInnerRight8" 1031153506 0 1 0 32400 0 0 0 0 0 32800 832 R6BE "MIInnerIntRow8" 1030556027 0 0 0 0 26528 0 1 AE r R6BF "Row8" O2E0 A29 0 0 32800 3168 193 0 0 32800 3168 5 2 AE r R6C0 "PDin35" A4 r R6C0 O157 5384 608 O45 5384 608 O45 7224 608 O116 7224 608 O119 5384 0 5 2 AE r R314 A4 r R314 O139 27864 416 O45 27864 416 O45 28504 416 O1D5 28504 416 O10C 27864 0 5 2 AE r R3F5 A4 r R3F5 O2CB 7944 2272 O45 7944 2272 O45 10504 2272 O159 10504 2272 OF3 7944 0 7 2 AE r RA1 A4 r RA1 O2E1 A9 20512 32 A6 AA 0 4024 3104 O45 9624 3104 O45 4024 3104 O45 24504 3104 OEE 24504 3104 OEE 9624 3104 O20D 4024 0 5 2 AE r R5DB A4 r R5DB O15B 10264 2848 O45 10264 2848 O45 12744 2848 O10A 12744 2848 O223 10264 0 5 2 AE r RA4 A4 r RA4 O111 12424 992 O45 12424 992 O45 13704 992 O13E 13704 992 OF6 12424 0 3 2 AE r R4E4 A4 r R4E4 OFB 22664 1632 O100 22744 1632 OF7 22664 0 5 2 AE r RA5 A4 r RA5 O120 10344 1760 O45 10344 1760 O45 12984 1760 OFE 12984 1760 O14D 10344 0 5 2 AE r R5DD A4 r R5DD OF2 27304 928 O45 27304 928 O45 27784 928 OEB 27784 0 O11B 27304 928 5 2 AE r R18A A4 r R18A O197 12664 2528 O45 12664 2528 O45 14264 2528 O119 14264 2528 O116 12664 0 7 2 AE r R4E9 A4 r R4E9 O1BD 7384 992 O45 10664 992 O45 7384 992 O45 12184 992 O13E 12184 992 OF6 10664 0 OF6 7384 0 5 2 AE r R318 A4 r R318 O1E0 1064 160 O45 1064 160 O45 9224 160 O10E 9224 0 O10E 1064 0 5 2 AE r R3FA A4 r R3FA O104 10824 736 O45 10824 736 O45 16824 736 O130 16824 0 O112 10824 736 5 2 AE r R5DF A4 r R5DF O287 1384 544 O45 1384 544 O45 4504 544 O102 4504 0 O10F 1384 544 5 2 AE r R6C1 "/0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)*1.[3]" A4 r R6C1 O22F 1624 1376 O45 1624 1376 O45 6184 1376 O14D 6184 1376 OFE 1624 0 7 2 AE r R6C2 "/0(MiChip)/5(DataMux)*1.[2]" A4 r R6C2 O2E2 A9 7632 32 A6 AA 0 22424 672 O45 22504 672 O45 22424 672 O45 30024 672 O11D 30024 0 O10D 22504 672 O11D 22424 0 5 2 AE r R31D A4 r R31D O113 13304 1376 O45 13304 1376 O45 20664 1376 O14D 20664 1376 OFE 13304 0 5 2 AE r R3FB A4 r R3FB O14B 28824 1696 O45 28824 1696 O45 29784 1696 OEC 29784 0 O128 28824 1696 5 2 AE r R6C3 "/0(MiChip)/5(DataMux)*1.[3]" A4 r R6C3 O161 23384 544 O45 23384 544 O45 25144 544 O102 25144 0 O102 23384 0 3 2 AE r R6C4 "PDout13" A4 r R6C4 O2E3 A9 1336 24 A6 AA 0 0 484 O45 1304 480 O1DB 1304 484 5 2 AE r R4F0 A4 r R4F0 O1F2 6984 2656 O45 6984 2656 O45 17864 2656 O1D7 17864 0 O13D 6984 2656 5 2 AE r R4F5 A4 r R4F5 O2CA 3624 672 O45 3624 672 O45 7304 672 O10D 7304 672 O11D 3624 0 5 2 AE r R6C5 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2).[1]" A4 r R6C5 OF5 4104 224 O45 4104 224 O45 5624 224 O215 5624 224 O107 4104 0 5 2 AE r R6C6 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[5]" A4 r R6C6 O12E 26504 96 O45 26504 96 O45 27224 96 OFA 27224 0 OFA 26504 0 10 2 AE r RBD A4 r RBD O2E4 A9 1376 32 A6 AA 0 25080 2464 O45 25080 2464 O45 26424 2464 O11D 26424 2464 O2E5 A9 32 800 A6 AB 0 25080 1696 O2E6 A9 1056 32 A6 AA 0 25080 1696 O45 25080 1696 O45 26104 1696 OEC 26104 0 O2E5 25080 1696 5 2 AE r R5E2 A4 r R5E2 O2C1 13864 864 O45 13864 864 O45 17064 864 O159 17064 0 OF3 13864 864 5 2 AE r RBE A4 r RBE O2B4 17944 992 O45 17944 992 O45 22024 992 O13E 22024 992 OF6 17944 0 5 2 AE r R6C7 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2).[2]" A4 r R6C7 OF2 4184 480 O45 4184 480 O45 4664 480 O1D7 4664 480 O13D 4184 0 5 2 AE r R6C8 "/0(MiChip)/2(MemCtlA)/12(fsmc1)/0(Decoder)*1.nnAd[0]" A4 r R6C8 O184 25384 3104 O45 25384 3104 O45 25544 3104 OEE 25544 3104 O20D 25384 0 5 2 AE r R6C9 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[6]" A4 r R6C9 O140 14504 608 O45 14504 608 O45 15384 608 O119 15384 0 O119 14504 0 5 2 AE r RC0 A4 r RC0 O1D1 20984 416 O45 20984 416 O45 27544 416 O1D5 27544 416 O10C 20984 0 5 2 AE r R3FE A4 r R3FE O2CB 12344 1888 O45 12344 1888 O45 14904 1888 OFD 14904 1888 O12F 12344 0 5 2 AE r RC2 A4 r RC2 O2CB 18184 416 O45 18184 416 O45 20744 416 O1D5 20744 416 O10C 18184 0 5 2 AE r RC4 A4 r RC4 O2E7 A9 8672 32 A6 AA 0 16824 2720 O45 16824 2720 O45 25464 2720 O1D5 25464 0 O10C 16824 2720 5 2 AE r R4FB A4 r R4FB O180 4184 608 O45 4184 608 O45 4584 608 O119 4584 0 O116 4184 608 7 2 AE r R324 A4 r R324 O2E8 A9 21232 32 A6 AA 0 9864 1248 O45 19704 1248 O45 9864 1248 O45 31064 1248 OFD 31064 0 O12F 19704 1248 OFD 9864 0 5 2 AE r R5E5 A4 r R5E5 O15B 24024 2592 O45 24024 2592 O45 26504 2592 O102 26504 2592 O10F 24024 0 5 2 AE r R4FD A4 r R4FD O103 1384 96 O45 1384 96 O45 1944 96 O21E 1944 96 OFA 1384 0 5 2 AE r R262 A4 r R262 O12A 9144 224 O45 9144 224 O45 11064 224 O215 11064 224 O107 9144 0 7 2 AE r RCB A4 r RCB O1F2 9384 2912 O45 10264 2912 O45 9384 2912 O45 20264 2912 O215 20264 0 O107 10264 2912 O215 9384 0 5 2 AE r RCF A4 r RCF O2D4 16264 2464 O45 16264 2464 O45 19304 2464 O10D 19304 0 O11D 16264 2464 5 2 AE r R325 A4 r R325 O184 15704 2592 O45 15704 2592 O45 15864 2592 O10F 15864 0 O102 15704 2592 5 2 AE r R405 A4 r R405 O2E9 A9 6272 32 A6 AA 0 10184 160 O45 10184 160 O45 16424 160 O206 16424 160 O10E 10184 0 7 2 AE r R19F A4 r R19F O2EA A9 9232 32 A6 AA 0 21784 1120 O45 25224 1120 O45 21784 1120 O45 30984 1120 O13A 30984 1120 O105 25224 0 O13A 21784 1120 5 2 AE r R4FE A4 r R4FE O129 9864 1376 O45 9864 1376 O45 13224 1376 OFE 13224 0 O14D 9864 1376 5 2 AE r R1A0 A4 r R1A0 O18C 3544 416 O45 3544 416 O45 4344 416 O1D5 4344 416 O10C 3544 0 5 2 AE r R1A1 A4 r R1A1 O1F2 9624 1696 O45 9624 1696 O45 20504 1696 O128 20504 1696 OEC 9624 0 5 2 AE r R406 A4 r R406 O2C5 6904 224 O45 6904 224 O45 9064 224 O107 9064 0 O215 6904 224 5 2 AE r R326 A4 r R326 O2EB A9 6832 32 A6 AA 0 22184 288 O45 22184 288 O45 28984 288 O223 28984 288 O10A 22184 0 5 2 AE r R408 A4 r R408 O143 16344 480 O45 16344 480 O45 17544 480 O13D 17544 0 O1D7 16344 480 5 2 AE r R5E7 A4 r R5E7 O275 11784 1504 O45 11784 1504 O45 23384 1504 OF7 23384 1504 O100 11784 0 5 2 AE r RD5 A4 r RD5 O2EC A9 10592 32 A6 AA 0 17144 2016 O45 17144 2016 O45 27704 2016 O13A 27704 0 O105 17144 2016 5 2 AE r R266 A4 r R266 O2C5 23064 2208 O45 23064 2208 O45 25224 2208 OEB 25224 2208 O11B 23064 0 5 2 AE r R500 A4 r R500 O143 19384 2336 O45 19384 2336 O45 20584 2336 O22 20584 2336 O109 19384 0 5 2 AE r R409 A4 r R409 O12A 7064 1632 O45 7064 1632 O45 8984 1632 OF7 8984 0 O100 7064 1632 5 2 AE r R501 A4 r R501 O180 7784 672 O45 7784 672 O45 8184 672 O10D 8184 672 O11D 7784 0 5 2 AE r R40B A4 r R40B O14B 1224 352 O45 1224 352 O45 2184 352 O1CF 2184 352 OF4 1224 0 5 2 AE r R6CA "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[6][0]" A4 r R6CA O2ED A9 18272 32 A6 AA 0 6104 800 O45 6104 800 O45 24344 800 O22 24344 0 O22 6104 0 3 2 AE r R6CB "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv).nEnable" A4 r R6CB OFB 22504 608 O116 22584 608 O119 22504 0 5 2 AE r R40C A4 r R40C O10B 28584 160 O45 28584 160 O45 30264 160 O10E 30264 0 O206 28584 160 5 2 AE r R6CC "/0(MiChip)/5(DataMux)*1.[36]" A4 r R6CC O118 2024 96 O45 2024 96 O45 2344 96 OFA 2344 0 OFA 2024 0 5 2 AE r R502 A4 r R502 O2EE A9 17312 32 A6 AA 0 14584 224 O45 14584 224 O45 31864 224 O107 31864 0 O215 14584 224 5 2 AE r R6CD "/0(MiChip)/5(DataMux)*1.[39][4]" A4 r R6CD O111 27384 608 O45 27384 608 O45 28664 608 O119 28664 0 O116 27384 608 7 2 AE r RDB A4 r RDB O2EF A9 3952 32 A6 AA 0 24104 1888 O45 27064 1888 O45 24104 1888 O45 28024 1888 OFD 28024 1888 OFD 27064 1888 O12F 24104 0 7 2 AE r R6CE "/0(MiChip)/5(DataMux)*1.[17]" A4 r R6CE O2F0 A9 21072 32 A6 AA 0 2104 1952 O45 15304 1952 O45 2104 1952 O45 23144 1952 O11E 23144 0 O127 15304 1952 O11E 2104 0 5 2 AE r R5EA A4 r R5EA O275 15624 608 O45 15624 608 O45 27224 608 O116 27224 608 O119 15624 0 5 2 AE r R328 A4 r R328 O2F1 A9 2752 32 A6 AA 0 11304 608 O45 11304 608 O45 14024 608 O116 14024 608 O119 11304 0 3 2 AE r R504 A4 r R504 O135 16984 36 O136 16984 0 O229 16984 36 5 2 AE r R5EB A4 r R5EB O12A 3144 288 O45 3144 288 O45 5064 288 O10A 5064 0 O10A 3144 0 5 2 AE r R5EC A4 r R5EC O129 6744 1120 O45 6744 1120 O45 10104 1120 O105 10104 0 O13A 6744 1120 5 2 AE r R5ED A4 r R5ED O103 14184 1184 O45 14184 1184 O45 14744 1184 O11E 14744 1184 O127 14184 0 9 2 AE r R6CF "/0(MiChip)/5(DataMux)/8(DataLatchMux)*1.[4]" A4 r R6CF O2F2 A9 12752 32 A6 AA 0 6824 1568 O45 8344 1568 O45 6824 1568 O45 11144 1568 O45 19544 1568 OF0 19544 0 OF0 8344 1568 OF0 11144 0 OF0 6824 0 5 2 AE r R6D0 "/0(MiChip)/2(MemCtlA)*1.[10]" A4 r R6D0 O180 16904 736 O45 16904 736 O45 17304 736 O130 17304 0 O130 16904 0 5 2 AE r R410 A4 r R410 O14B 27304 800 O45 27304 800 O45 28264 800 O109 28264 800 O22 27304 0 5 2 AE r R506 A4 r R506 O12E 1144 288 O45 1144 288 O45 1864 288 O223 1864 288 O10A 1144 0 5 2 AE r R1A3 A4 r R1A3 O2F3 A9 11472 32 A6 AA 0 18664 864 O45 18664 864 O45 30104 864 O159 30104 0 OF3 18664 864 5 2 AE r R5EE A4 r R5EE O2F4 A9 13072 32 A6 AA 0 12824 2848 O45 12824 2848 O45 25864 2848 O10A 25864 2848 O223 12824 0 5 2 AE r R32A A4 r R32A O2B4 10744 2720 O45 10744 2720 O45 14824 2720 O10C 14824 2720 O1D5 10744 0 7 2 AE r R32C A4 r R32C O2F5 A9 20352 32 A6 AA 0 6664 1440 O45 21144 1440 O45 6664 1440 O45 26984 1440 O128 26984 0 O128 21144 0 O128 6664 0 3 2 AE r R5F0 A4 r R5F0 O135 4264 36 O136 4264 0 O229 4264 36 5 2 AE r R50A A4 r R50A O12A 28744 608 O45 28744 608 O45 30664 608 O116 30664 608 O119 28744 0 5 2 AE r RE0 A4 r RE0 O209 12584 1120 O45 12584 1120 O45 20824 1120 O13A 20824 1120 O105 12584 0 7 2 AE r R5F1 A4 r R5F1 O162 22664 1824 O45 26744 1824 O45 22664 1824 O45 28184 1824 O114 28184 1824 O121 26744 0 O114 22664 1824 5 2 AE r R6D1 "PDout29" A4 r R6D1 O131 12744 2784 O45 12744 2784 O45 16184 2784 OF4 16184 2784 O1CF 12744 0 5 2 AE r R5F2 A4 r R5F2 OF2 18344 2336 O45 18344 2336 O45 18824 2336 O22 18824 2336 O109 18344 0 5 2 AE r R1A5 A4 r R1A5 O2F6 A9 8592 32 A6 AA 0 6984 2592 O45 6984 2592 O45 15544 2592 O102 15544 2592 O10F 6984 0 5 2 AE r R414 A4 r R414 O2AF 8024 1184 O45 8024 1184 O45 14104 1184 O11E 14104 1184 O127 8024 0 5 2 AE r R1A6 A4 r R1A6 O2F7 A9 4352 32 A6 AA 0 15384 1184 O45 15384 1184 O45 19704 1184 O127 19704 0 O11E 15384 1184 5 2 AE r R26A A4 r R26A O14B 23464 1952 O45 23464 1952 O45 24424 1952 O11E 24424 0 O127 23464 1952 3 2 AE r R6D2 "/0(MiChip)/2(MemCtlA)*1.[2]" A4 r R6D2 OFB 19144 2848 O10A 19224 2848 O223 19144 0 5 2 AE r R5F3 A4 r R5F3 O118 8584 672 O45 8584 672 O45 8904 672 O11D 8904 0 O10D 8584 672 5 2 AE r R50E A4 r R50E O2F8 A9 14112 32 A6 AA 0 8504 544 O45 8504 544 O45 22584 544 O102 22584 0 O10F 8504 544 5 2 AE r R5F4 A4 r R5F4 O2F9 A9 8992 32 A6 AA 0 12504 2272 O45 12504 2272 O45 21464 2272 O159 21464 2272 OF3 12504 0 5 2 AE r R32F A4 r R32F O2C4 11784 2976 O45 11784 2976 O45 18984 2976 O206 18984 0 O10E 11784 2976 7 2 AE r R1A9 A4 r R1A9 O2FA A9 12192 32 A6 AA 0 18504 480 O45 26024 480 O45 18504 480 O45 30664 480 O13D 30664 0 O13D 26024 0 O1D7 18504 480 5 2 AE r R1AA A4 r R1AA O290 20264 2976 O45 20264 2976 O45 24504 2976 O206 24504 0 O10E 20264 2976 5 2 AE r R1AB A4 r R1AB O111 28344 32 O45 28344 32 O45 29624 32 OEE 29624 0 O20D 28344 32 3 2 AE r R6D3 "CLOCK2" A4 r R6D3 O2FB A9 9976 24 A6 AA 0 22824 996 O45 22824 992 O2FC A9 32 2172 A6 AB 0 22824 996 7 2 AE r R6D4 "/0(MiChip)*1.RdDone" A4 r R6D4 O2FD A9 8112 32 A6 AA 0 14024 288 O45 16024 288 O45 14024 288 O45 22104 288 O223 22104 288 O223 16024 288 O10A 14024 0 5 2 AE r R418 A4 r R418 O2FE A9 6352 32 A6 AA 0 15304 1888 O45 15304 1888 O45 21624 1888 OFD 21624 1888 O12F 15304 0 5 2 AE r R6D5 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[3]" A4 r R6D5 O157 17624 160 O45 17624 160 O45 19464 160 O10E 19464 0 O10E 17624 0 3 2 AE r R6D6 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0(counterCLP2NL).[6]" A4 r R6D6 OFB 6184 1312 O121 6264 1312 O114 6184 0 5 2 AE r R41A A4 r R41A O2CA 7304 608 O45 7304 608 O45 10984 608 O116 10984 608 O119 7304 0 5 2 AE r R1AE A4 r R1AE O22A 7144 1504 O45 7144 1504 O45 10104 1504 OF7 10104 1504 O100 7144 0 5 2 AE r R5F7 A4 r R5F7 O28D 7944 2336 O45 7944 2336 O45 17464 2336 O109 17464 0 O22 7944 2336 5 2 AE r R6D7 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[4]" A4 r R6D7 O11C 6744 864 O45 6744 864 O45 7864 864 O159 7864 0 O159 6744 0 5 2 AE r R1B1 A4 r R1B1 O18C 16584 160 O45 16584 160 O45 17384 160 O206 17384 160 O10E 16584 0 5 2 AE r R33C A4 r R33C OF2 1304 416 O45 1304 416 O45 1784 416 O1D5 1784 416 O10C 1304 0 5 2 AE r R41C A4 r R41C O11F 17784 3040 O45 17784 3040 O45 19144 3040 OFA 19144 3040 O21E 17784 0 5 2 AE r R33D A4 r R33D OF2 9304 160 O45 9304 160 O45 9784 160 O10E 9784 0 O10E 9304 0 5 2 AE r R512 A4 r R512 O2FF A9 8032 32 A6 AA 0 21384 1376 O45 21384 1376 O45 29384 1376 O14D 29384 1376 OFE 21384 0 3 2 AE r R5F9 A4 r R5F9 OFB 25704 2016 O13A 25784 0 O105 25704 2016 5 2 AE r R33E A4 r R33E OF2 9464 672 O45 9464 672 O45 9944 672 O11D 9944 0 O11D 9464 0 5 2 AE r R41D A4 r R41D O190 11384 2400 O45 11384 2400 O45 27464 2400 O130 27464 2400 O112 11384 0 5 2 AE r R513 A4 r R513 O263 16904 2784 O45 16904 2784 O45 19224 2784 O1CF 19224 0 OF4 16904 2784 5 2 AE r R6D8 "/0(MiChip)/7(StatusReg)*1.[8]" A4 r R6D8 O2D4 7544 288 O45 7544 288 O45 10584 288 O10A 10584 0 O10A 7544 0 5 2 AE r R514 A4 r R514 O11C 21144 1568 O45 21144 1568 O45 22264 1568 OF0 22264 0 OF0 21144 1568 5 2 AE r R6D9 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21).[2]" A4 r R6D9 O2C3 7624 352 O45 7624 352 O45 10024 352 OF4 10024 0 OF4 7624 0 5 2 AE r R341 A4 r R341 O12E 2904 736 O45 2904 736 O45 3624 736 O112 3624 736 O130 2904 0 5 2 AE r R275 A4 r R275 O1D8 27384 100 O45 27384 96 O45 29704 96 O300 A9 32 3068 A6 AB 0 29704 100 O124 27384 0 5 2 AE r R6DA "/0(MiChip)*1.TagParErr" A4 r R6DA O140 2824 96 O45 2824 96 O45 3704 96 OFA 3704 0 OFA 2824 0 5 2 AE r R515 A4 r R515 O287 10824 288 O45 10824 288 O45 13944 288 O223 13944 288 O10A 10824 0 5 2 AE r R41F A4 r R41F O138 11464 2144 O45 11464 2144 O45 27624 2144 OF6 27624 2144 O13E 11464 0 5 2 AE r R6DB "/0(MiChip)/2(MemCtlA)*1.Accept" A4 r R6DB O111 15224 992 O45 15224 992 O45 16504 992 OF6 16504 0 O13E 15224 992 7 2 AE r R6DC "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[8][1]" A4 r R6DC O2B4 22824 928 O45 24184 928 O45 22824 928 O45 26904 928 O11B 26904 928 OEB 24184 0 OEB 22824 0 5 2 AE r R6DD "/0(MiChip)/2(MemCtlA)*1.[27]" A4 r R6DD O2A3 14104 992 O45 14104 992 O45 15144 992 O13E 15144 992 OF6 14104 0 5 2 AE r R423 A4 r R423 O197 26824 160 O45 26824 160 O45 28424 160 O206 28424 160 O10E 26824 0 5 2 AE r R5FE A4 r R5FE O263 13464 2464 O45 13464 2464 O45 15784 2464 O10D 15784 0 O11D 13464 2464 9 2 AE r REE A4 r REE O301 A9 10272 32 A6 AA 0 17224 1760 O45 17304 1760 O45 17224 1760 O45 18024 1760 O45 27464 1760 O14D 27464 0 OFE 17304 1760 O14D 18024 0 O14D 17224 0 13 2 AE r R1B4 A4 r R1B4 O302 A9 27632 32 A6 AA 0 344 32 O45 2664 32 O45 8104 32 O45 344 32 O45 14584 32 O45 5144 32 O45 27944 32 OEE 27944 0 O20D 2664 32 OEE 5144 0 OEE 8104 0 OEE 14584 0 OEE 344 0 5 2 AE r R6DE "/0(MiChip)/4(RefreshCtr)*1.[8][6]" A4 r R6DE O197 12184 864 O45 12184 864 O45 13784 864 OF3 13784 864 O159 12184 0 5 2 AE r R27A A4 r R27A O2C1 4344 352 O45 4344 352 O45 7544 352 O1CF 7544 352 OF4 4344 0 5 2 AE r R519 A4 r R519 O139 17064 992 O45 17064 992 O45 17704 992 OF6 17704 0 O13E 17064 992 5 2 AE r R6DF "/0(MiChip)/2(MemCtlA)*1.[19]" A4 r R6DF O15B 13624 1760 O45 13624 1760 O45 16104 1760 OFE 16104 1760 O14D 13624 0 7 2 AE r RF0 A4 r RF0 O303 A9 11152 32 A6 AA 0 15544 2528 O45 21384 2528 O45 15544 2528 O45 26664 2528 O116 26664 0 O119 21384 2528 O116 15544 0 5 2 AE r R51B A4 r R51B O143 24344 3040 O45 24344 3040 O45 25544 3040 O21E 25544 0 OFA 24344 3040 7 2 AE r RF2 A4 r RF2 O304 A9 19232 32 A6 AA 0 11544 352 O45 19464 352 O45 11544 352 O45 30744 352 O1CF 30744 352 O1CF 19464 352 OF4 11544 0 5 2 AE r RB A4 r RB O305 A9 3312 32 A6 AA 0 21624 1696 O45 21624 1696 O45 24904 1696 O128 24904 1696 OEC 21624 0 7 2 AE r RF8 A4 r RF8 O303 15464 1312 O45 21304 1312 O45 15464 1312 O45 26584 1312 O114 26584 0 O121 21304 1312 O114 15464 0 3 2 AE r R604 A4 r R604 OFB 15624 672 O11D 15704 0 O10D 15624 672 5 2 AE r RFF A4 r RFF O120 26904 544 O45 26904 544 O45 29544 544 O10F 29544 544 O102 26904 0 7 2 AE r R6E0 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[9][0]" A4 r R6E0 O2C1 22984 2336 O45 25944 2336 O45 22984 2336 O45 26184 2336 O22 26184 2336 O22 25944 2336 O109 22984 0 5 2 AE r R6E1 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21).[2]" A4 r R6E1 OFF 1464 224 O45 1464 224 O45 3464 224 O215 3464 224 O107 1464 0 9 2 AE r R34C A4 r R34C O2D0 11144 1632 O45 13384 1632 O45 11144 1632 O45 23544 1632 O45 28824 1632 OF7 28824 0 OF7 13384 0 O100 23544 1632 O100 11144 1632 5 2 AE r R6E2 "/0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)*1.[4]" A4 r R6E2 O140 4824 96 O45 4824 96 O45 5704 96 O21E 5704 96 OFA 4824 0 5 2 AE r R6E3 "/0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21).[2]" A4 r R6E3 O22F 4984 736 O45 4984 736 O45 9544 736 O130 9544 0 O130 4984 0 5 2 AE r R101 A4 r R101 O306 A9 6432 32 A6 AA 0 19864 96 O45 19864 96 O45 26264 96 OFA 26264 0 OFA 19864 0 5 2 AE r R606 A4 r R606 O184 25464 2912 O45 25464 2912 O45 25624 2912 O215 25624 0 O107 25464 2912 5 2 AE r R608 A4 r R608 O2C5 27624 1760 O45 27624 1760 O45 29784 1760 OFE 29784 1760 O14D 27624 0 3 2 AE r R6E4 "/0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)*1.[5]" A4 r R6E4 O135 13144 36 O136 13144 0 O229 13144 36 7 2 AE r R6E5 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv).nEnable" A4 r R6E5 O2F2 6904 96 O45 8424 96 O45 6904 96 O45 19624 96 OFA 19624 0 O21E 8424 96 OFA 6904 0 5 2 AE r R42B A4 r R42B O10B 28664 800 O45 28664 800 O45 30344 800 O22 30344 0 O109 28664 800 9 2 AE r R103 A4 r R103 O2F8 2104 2016 O45 4424 2016 O45 2104 2016 O45 8664 2016 O45 16184 2016 O13A 16184 0 O105 4424 2016 O105 8664 2016 O105 2104 2016 3 2 AE r R6E6 "IORDY" A4 r R6E6 O307 A9 9736 24 A6 AA 0 23064 2276 O45 23064 2272 O231 23064 2276 5 2 AE r R520 A4 r R520 O140 23784 2464 O45 23784 2464 O45 24664 2464 O10D 24664 0 O11D 23784 2464 7 2 AE r R1BC A4 r R1BC O308 A9 11552 32 A6 AA 0 10184 672 O45 14344 672 O45 10184 672 O45 21704 672 O10D 21704 672 O11D 14344 0 O10D 10184 672 5 2 AE r R34F A4 r R34F O309 A9 5872 32 A6 AA 0 21224 1184 O45 21224 1184 O45 27064 1184 O127 27064 0 O127 21224 0 5 2 AE r R107 A4 r R107 O30A A9 2112 32 A6 AA 0 25704 1952 O45 25704 1952 O45 27784 1952 O127 27784 1952 O11E 25704 0 5 2 AE r R6E7 "/0(MiChip)/7(StatusReg)*1.[14][1]" A4 r R6E7 O140 6584 1184 O45 6584 1184 O45 7464 1184 O127 7464 0 O11E 6584 1184 7 2 AE r R6E8 "/0(MiChip)/2(MemCtlA)/12(fsmc1)/0(Decoder)*1.nAd[0]" A4 r R6E8 O1BB 20424 160 O45 24984 160 O45 20424 160 O45 25304 160 O10E 25304 0 O206 24984 160 O206 20424 160 7 2 AE r R1C2 A4 r R1C2 O308 10344 1824 O45 14264 1824 O45 10344 1824 O45 21864 1824 O114 21864 1824 O121 14264 0 O114 10344 1824 5 2 AE r R60C A4 r R60C OF5 5944 1312 O45 5944 1312 O45 7464 1312 O121 7464 1312 O114 5944 0 5 2 AE r R354 A4 r R354 O12A 18264 2208 O45 18264 2208 O45 20184 2208 OEB 20184 2208 O11B 18264 0 5 2 AE r R1C6 A4 r R1C6 O10B 24584 800 O45 24584 800 O45 26264 800 O109 26264 800 O22 24584 0 5 2 AE r R6E9 "/0(MiChip)/2(MemCtlA)/44(fsm1)/0(ffR)*1.[4]" A4 r R6E9 O180 29064 288 O45 29064 288 O45 29464 288 O223 29464 288 O10A 29064 0 5 2 AE r R432 A4 r R432 O2C1 4904 544 O45 4904 544 O45 8104 544 O10F 8104 544 O102 4904 0 5 2 AE r R1C7 A4 r R1C7 O1BC 22744 1568 O45 22744 1568 O45 26584 1568 OF0 26584 1568 OF0 22744 0 5 2 AE r R6EA "/0(MiChip)/4(RefreshCtr)*1.[3][6]" A4 r R6EA O2C5 12264 224 O45 12264 224 O45 14424 224 O107 14424 0 O107 12264 0 5 2 AE r R524 A4 r R524 O118 26104 2080 O45 26104 2080 O45 26424 2080 O133 26424 0 OF1 26104 2080 5 2 AE r R6EB "/0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)*1.[7]" A4 r R6EB O30B A9 13472 32 A6 AA 0 4664 416 O45 4664 416 O45 18104 416 O10C 18104 0 O10C 4664 0 5 2 AE r R356 A4 r R356 O161 6264 1248 O45 6264 1248 O45 8024 1248 O12F 8024 1248 OFD 6264 0 9 2 AE r R6EC "/0(MiChip)*1.[40]" A4 r R6EC O30C A9 23472 32 A6 AA 0 6424 1056 O45 10904 1056 O45 6424 1056 O45 28744 1056 O45 29864 1056 OF1 29864 0 OF1 10904 0 O133 28744 1056 OF1 6424 0 7 2 AE r R10A A4 r R10A O2E1 3944 2080 O45 9544 2080 O45 3944 2080 O45 24424 2080 OF1 24424 2080 OF1 9544 2080 O133 3944 0 5 2 AE r R359 A4 r R359 O11F 5864 288 O45 5864 288 O45 7224 288 O10A 7224 0 O223 5864 288 7 2 AE r R527 A4 r R527 O30D A9 9632 32 A6 AA 0 6504 480 O45 10984 480 O45 6504 480 O45 16104 480 O13D 16104 0 O13D 10984 0 O13D 6504 0 5 2 AE r R610 A4 r R610 O161 29704 32 O45 29704 32 O45 31464 32 O20D 31464 32 OEE 29704 0 5 2 AE r R436 A4 r R436 O2C1 19944 2464 O45 19944 2464 O45 23144 2464 O11D 23144 2464 O10D 19944 0 5 2 AE r R6ED "/0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)*1.[5]" A4 r R6ED O12E 21064 928 O45 21064 928 O45 21784 928 OEB 21784 0 O11B 21064 928 5 2 AE r R612 A4 r R612 O118 7064 1376 O45 7064 1376 O45 7384 1376 O14D 7384 1376 OFE 7064 0 9 2 AE r R10D A4 r R10D O275 20024 2784 O45 26344 2784 O45 20024 2784 O45 30824 2784 O45 31624 2784 O1CF 31624 0 OF4 26344 2784 O1CF 30824 0 O1CF 20024 0 5 2 AE r R1CA A4 r R1CA O10B 11224 2464 O45 11224 2464 O45 12904 2464 O11D 12904 2464 O10D 11224 0 5 2 AE r R616 A4 r R616 O2C8 10504 2208 O45 10504 2208 O45 17224 2208 OEB 17224 2208 O11B 10504 0 7 2 AE r R112 A4 r R112 O294 23944 1504 O45 27144 1504 O45 23944 1504 O45 28104 1504 OF7 28104 1504 OF7 27144 1504 O100 23944 0 5 2 AE r R1CC A4 r R1CC O2F1 16664 2592 O45 16664 2592 O45 19384 2592 O102 19384 2592 O10F 16664 0 3 2 AE r R6EE "PDin26" A4 r R6EE O30E A9 2936 24 A6 AA 0 0 804 O45 2904 800 O2BB 2904 804 7 2 AE r R1D0 A4 r R1D0 O30F A9 14592 32 A6 AA 0 6344 928 O45 18424 928 O45 6344 928 O45 20904 928 O11B 20904 928 OEB 18424 0 O11B 6344 928 5 2 AE r R1CE A4 r R1CE O15C 21304 1120 O45 21304 1120 O45 21544 1120 O13A 21544 1120 O105 21304 0 5 2 AE r R6EF "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][2]" A4 r R6EF O2FF 18344 2656 O45 18344 2656 O45 26344 2656 O1D7 26344 0 O13D 18344 2656 5 2 AE r R52F A4 r R52F O103 2984 480 O45 2984 480 O45 3544 480 O1D7 3544 480 O13D 2984 0 7 2 AE r R1D1 A4 r R1D1 O2B3 18584 736 O45 25944 736 O45 18584 736 O45 30584 736 O130 30584 0 O130 25944 0 O112 18584 736 5 2 AE r R6F0 "PDin32" A4 r R6F0 O139 14824 2528 O45 14824 2528 O45 15464 2528 O119 15464 2528 O116 14824 0 5 2 AE r R35D A4 r R35D O103 26184 2208 O45 26184 2208 O45 26744 2208 OEB 26744 2208 O11B 26184 0 7 2 AE r R6F1 "/0(MiChip)/5(DataMux)*1.[11][9]" A4 r R6F1 O28B 8824 1312 O45 9944 1312 O45 8824 1312 O45 14424 1312 O121 14424 1312 O121 9944 1312 O114 8824 0 0 0 27360 0 1 AE r R6F2 "MIInnerChan9" O310 A2 0 0 32800 856 146 O311 A2 0 0 1280 832 2 O312 A2 0 0 1280 80 1 O313 A9 1280 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 1280 80 R2 1059061760 0 0 0 0 0 0 0 O314 A2 0 0 1280 80 1 O313 0 0 0 2 A4 r RC AE r RC 0 0 1280 80 R2 1059061760 0 0 0 0 752 0 0 0 0 1280 832 R6F3 "MIInnerLeft9" 1031153506 0 1 0 0 0 0 0 ODD 1280 0 0 2 AE r R6F4 "/0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1" A1A a A1A O18 1744 0 0 2 AE r R6F5 "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)*1.[4]-9" A1A a A1A O18 1824 0 0 2 AE r R6F6 "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)*1.[3]-9" A1A a A1A O16D 1920 0 0 2 AE r R6F7 "/0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer0" A1A a A1A ODD 2160 0 0 2 AE r R6F8 "/0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 2640 0 0 2 AE r R6F9 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 3424 0 0 2 AE r R6FA "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21).[2]-9" A1A a A1A O18 3504 0 0 2 AE r R6FB "/0(MiChip)/5(DataMux)*1.[11][8]-9" A1A a A1A O18 3584 0 0 2 AE r R6FC "/0(MiChip)/5(DataMux)*1.[15][7]-9" A1A a A1A ODD 3680 0 0 2 AE r R6FD "/0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 4144 0 0 2 AE r R6FE "PDout15-9" A1A a A1A O18 4224 0 0 2 AE r R6FF "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)*1.[5]-9" A1A a A1A O18 4304 0 0 2 AE r R700 "Din13-9" A1A a A1A O24 4400 0 0 2 AE r R701 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1*1*1*1*1" A1A a A1A OB6 5200 0 0 2 AE r R702 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1*1*1*1*1" A1A a A1A O18 5664 0 0 2 AE r R703 "/0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)*1.[4]-9" A1A a A1A ODD 5760 0 0 2 AE r R704 "/0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O168 6240 0 0 2 AE r R705 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0(counterCLP2NL)/3(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O86 6560 0 0 2 AE r R706 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv4" A1A a A1A O18 6704 0 0 2 AE r R707 "/0(MiChip)/5(DataMux)*1.[23][7]-9" A1A a A1A OA4 6800 0 0 2 AE r R708 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 7184 0 0 2 AE r R709 "PDin35-9" A1A a A1A O86 7280 0 0 2 AE r R70A "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv0" A1A a A1A O18 7424 0 0 2 AE r R70B "/0(MiChip)/7(StatusReg)*1.[14][2]-9" A1A a A1A ODD 7520 0 0 2 AE r R70C "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 7984 0 0 2 AE r R70D "/0(MiChip)/5(DataMux)*1.Select[0]-9" A1A a A1A O18 8064 0 0 2 AE r R70E "/0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)*1.[3]-9" A1A a A1A O18 8144 0 0 2 AE r R70F "/0(MiChip)/5(DataMux)*1.[23][4]-9" A1A a A1A OCE 8240 0 0 2 AE r R710 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver1" A1A a A1A O18 8544 0 0 2 AE r R711 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21).[2]-9" A1A a A1A O24 8640 0 0 2 AE r R712 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1" A1A a A1A OA4 9440 0 0 2 AE r R713 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1" A1A a A1A O18 9824 0 0 2 AE r R714 "/0(MiChip)/5(DataMux)*1.[39][1]-9" A1A a A1A O86 9920 0 0 2 AE r R715 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv1" A1A a A1A OA4 10080 0 0 2 AE r R716 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 10464 0 0 2 AE r R717 "PDin36-9" A1A a A1A O86 10560 0 0 2 AE r R718 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv5" A1A a A1A OAF 10720 0 0 2 AE r R719 "/0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 10944 0 0 2 AE r R71A "/0(MiChip)/5(DataMux)*1.[15][1]-9" A1A a A1A O18 11024 0 0 2 AE r R71B "PDout35-9" A1A a A1A O24 11120 0 0 2 AE r R71C "/0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1*1*1*1" A1A a A1A O24 11920 0 0 2 AE r R71D "/0(MiChip)/1(ClockGen)/9(FF)*1" A1A a A1A O18 12704 0 0 2 AE r R71E "PDin37-9" A1A a A1A O86 12800 0 0 2 AE r R71F "/0(MiChip)/2(MemCtlA)/41(fsmc1)/0(Decoder)/3(Inv)" A1A a A1A O18 12944 0 0 2 AE r R720 "/0(MiChip)*1.RASX-9" A1A a A1A ODD 13040 0 0 2 AE r R721 "/0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OAF 13520 0 0 2 AE r R722 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/4/6/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 13744 0 0 2 AE r R723 "/0(MiChip)/4(RefreshCtr)*1.[8][6]-9" A1A a A1A O18 13824 0 0 2 AE r R724 "PDout4-9" A1A a A1A O18 13904 0 0 2 AE r R725 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[6]-9" A1A a A1A O18 13984 0 0 2 AE r R726 "/0(MiChip)/5(DataMux)*1.[23][6]-9" A1A a A1A O18 14064 0 0 2 AE r R727 "PDout39-9" A1A a A1A OAF 14160 0 0 2 AE r R728 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/4/6/1(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A OA4 14400 0 0 2 AE r R729 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 14784 0 0 2 AE r R72A "PDout38-9" A1A a A1A O18 14864 0 0 2 AE r R72B "/0(MiChip)/7(StatusReg)*1.[16][2]-9" A1A a A1A O86 14960 0 0 2 AE r R72C "/0(MiChip)/2(MemCtlA)/45(Inv)*1" A1A a A1A O18 15104 0 0 2 AE r R72D "/0(MiChip)/2(MemCtlA)*1.[27]-9" A1A a A1A O18 15184 0 0 2 AE r R72E "/0(MiChip)/2(MemCtlA)*1.Accept-9" A1A a A1A O18 15264 0 0 2 AE r R72F "/0(MiChip)/5(DataMux)*1.[17]-9" A1A a A1A O18 15344 0 0 2 AE r R730 "Dout12-9" A1A a A1A O18 15424 0 0 2 AE r R731 "PDin32-9" A1A a A1A O18 15504 0 0 2 AE r R732 "Dout11-9" A1A a A1A O18 15584 0 0 2 AE r R733 "/0(MiChip)/2(MemCtlA)*1.[78]-9" A1A a A1A O18 15664 0 0 2 AE r R734 "/0(MiChip)/2(MemCtlA)*1.WrHCy-9" A1A a A1A OA4 15760 0 0 2 AE r R735 "/0(MiChip)/2(MemCtlA)/48(A22o2i)*1" A1A a A1A O18 16144 0 0 2 AE r R736 "PDout29-9" A1A a A1A O18 16224 0 0 2 AE r R737 "Din6-9" A1A a A1A ODD 16320 0 0 2 AE r R738 "/0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 16784 0 0 2 AE r R739 "/0(MiChip)/3(AddrMux)*1.In1[9]-9" A1A a A1A O18 16864 0 0 2 AE r R73A "/0(MiChip)/2(MemCtlA)*1.DataCy-9" A1A a A1A O18 16944 0 0 2 AE r R73B "PDout37-9" A1A a A1A O18 17024 0 0 2 AE r R73C "/0(MiChip)/2(MemCtlA)*1.[38]-9" A1A a A1A O18 17104 0 0 2 AE r R73D "/0(MiChip)*1.LdAddrHi[0]-9" A1A a A1A O18 17184 0 0 2 AE r R73E "HOSTRESET-9" A1A a A1A O18 17264 0 0 2 AE r R73F "LPRESET-9" A1A a A1A O18 17344 0 0 2 AE r R740 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two-9" A1A a A1A O24 17440 0 0 2 AE r R741 "/0(MiChip)/1(ClockGen)/8(FF)*1" A1A a A1A OAF 18240 0 0 2 AE r R742 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/6/1(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 18464 0 0 2 AE r R743 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv).nEnable-9" A1A a A1A O18 18544 0 0 2 AE r R744 "/0(MiChip)*1.LdStatus[1]-9" A1A a A1A O18 18624 0 0 2 AE r R745 "Din15-9" A1A a A1A ODD 18720 0 0 2 AE r R746 "/0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1" A1A a A1A O86 19200 0 0 2 AE r R747 "/0(MiChip)/2(MemCtlA)/30(Inv)*1" A1A a A1A O18 19344 0 0 2 AE r R748 "RPadEnb-9" A1A a A1A O24 19440 0 0 2 AE r R749 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 20224 0 0 2 AE r R74A "/0(MiChip)/2(MemCtlA)*1.RefCy-9" A1A a A1A O86 20320 0 0 2 AE r R74B "/0(MiChip)/2(MemCtlA)/12(fsmc1)/0(Decoder)/3(Inv)" A1A a A1A O18 20464 0 0 2 AE r R74C "Din8-9" A1A a A1A O18 20544 0 0 2 AE r R74D "PDout36-9" A1A a A1A O18 20624 0 0 2 AE r R74E "/0(MiChip)/6(AddrCtl)*1.[13]-9" A1A a A1A O18 20704 0 0 2 AE r R74F "Dout6-9" A1A a A1A O18 20784 0 0 2 AE r R750 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncount-9" A1A a A1A O86 20880 0 0 2 AE r R751 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/0(InverterSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv0" A1A a A1A O18 21024 0 0 2 AE r R752 "/0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)*1.[5]-9" A1A a A1A O18 21104 0 0 2 AE r R753 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[13]-9" A1A a A1A OCE 21200 0 0 2 AE r R754 "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver0" A1A a A1A O18 21504 0 0 2 AE r R755 "Dout0-9" A1A a A1A OA4 21600 0 0 2 AE r R756 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 21984 0 0 2 AE r R757 "/0(MiChip)/6(AddrCtl)/10(Decoder)*1.nEnable-9" A1A a A1A O171 22080 0 0 2 AE r R758 "/0(MiChip)/6(AddrCtl)/1(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A OCE 22400 0 0 2 AE r R759 "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver5" A1A a A1A O18 22704 0 0 2 AE r R75A "PDin38-9" A1A a A1A O86 22800 0 0 2 AE r R75B "/0(MiChip)/1(ClockGen)/10(Inv)*1" A1A a A1A O86 22960 0 0 2 AE r R75C "/0(MiChip)/6(AddrCtl)/6(Inv)*1" A1A a A1A O18 23104 0 0 2 AE r R75D "/0(MiChip)/1(ClockGen)*1.[11]-9" A1A a A1A O86 23200 0 0 2 AE r R75E "/0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1" A1A a A1A O18 23344 0 0 2 AE r R75F "Din9-9" A1A a A1A O18 23424 0 0 2 AE r R760 "Dout13-9" A1A a A1A O24 23520 0 0 2 AE r R761 "/0(MiChip)/2(MemCtlA)/9(fsm2p)/0(ffP)/0(FF)*1" A1A a A1A OA4 24320 0 0 2 AE r R762 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1*1*1*1*1*1*1" A1A a A1A O86 24720 0 0 2 AE r R763 "/0(MiChip)/2(MemCtlA)/12(fsmc1)/0(Decoder)/4(Inv)" A1A a A1A O18 24864 0 0 2 AE r R764 "Gnd-9" A1A a A1A OCA 24960 0 0 2 AE r R765 "/0(MiChip)/2(MemCtlA)/12(fsmc1)/0(Decoder)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 25184 0 0 2 AE r R766 "Dout8-9" A1A a A1A OAF 25280 0 0 2 AE r R767 "/0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A OCA 25520 0 0 2 AE r R768 "/0(MiChip)/2(MemCtlA)/12(fsmc1)/0(Decoder)/1(NormalizedNor2)/0(Nor2)" A1A a A1A O86 25760 0 0 2 AE r R769 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 25920 0 0 2 AE r R76A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/3//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/3//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/3/0(Inv)*1*1*1" A1A a A1A OCA 26080 0 0 2 AE r R76B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/3/1(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 26304 0 0 2 AE r R76C "/0(MiChip)*1.LdStatus[0]-9" A1A a A1A O18 26384 0 0 2 AE r R76D "Dout5-9" A1A a A1A O18 26464 0 0 2 AE r R76E "/0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)*1.[5]-9" A1A a A1A O86 26560 0 0 2 AE r R76F "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv6" A1A a A1A OCA 26720 0 0 2 AE r R770 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/3/2(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A OCE 26960 0 0 2 AE r R771 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver6" A1A a A1A O18 27264 0 0 2 AE r R772 "/0(MiChip)/3(AddrMux)*1.[19][1]-9" A1A a A1A OA4 27360 0 0 2 AE r R773 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 27760 0 0 2 AE r R774 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv5" A1A a A1A OCE 27920 0 0 2 AE r R775 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver5" A1A a A1A O18 28224 0 0 2 AE r R776 "/0(MiChip)/6(AddrCtl)*1.[19]-9" A1A a A1A O18 28304 0 0 2 AE r R777 "/0(MiChip)/2(MemCtlA)*1.C1-9" A1A a A1A O18 28384 0 0 2 AE r R778 "/0(MiChip)/4(RefreshCtr)*1.[8][12]-9" A1A a A1A O18 28464 0 0 2 AE r R779 "Dout1-9" A1A a A1A O18 28544 0 0 2 AE r R77A "/0(MiChip)/5(DataMux)/11(DataLatchMux)*1.[4]-9" A1A a A1A O18 28624 0 0 2 AE r R77B "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv).nEnable-9" A1A a A1A O168 28720 0 0 2 AE r R77C "/0(MiChip)/5(DataMux)/6(DataLatchMux)/0(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A OAF 29040 0 0 2 AE r R77D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/6/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A OAF 29280 0 0 2 AE r R77E "/0(MiChip)/2(MemCtlA)/44(fsm1)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O86 29520 0 0 2 AE r R77F "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv15" A1A a A1A O86 29680 0 0 2 AE r R780 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv14" A1A a A1A O24 29840 0 0 2 AE r R781 "/0(MiChip)/1(ClockGen)/6(FF)*1" A1A a A1A O18 30624 0 0 2 AE r R782 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11).Two-9" A1A a A1A O24 30720 0 0 2 AE r R783 "/0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O315 A2 0 0 1280 832 2 O316 A2 0 0 1280 80 1 O313 0 0 0 2 A4 r RB AE r RB 0 0 1280 80 R2 1059061760 0 0 0 0 0 0 0 O317 A2 0 0 1280 80 1 O313 0 0 0 2 A4 r RC AE r RC 0 0 1280 80 R2 1059061760 0 0 0 0 752 0 0 0 0 1280 832 R784 "MIInnerRight9" 1031153506 0 1 0 31520 0 0 0 0 0 32800 832 R785 "MIInnerIntRow9" 1030701209 0 0 0 0 30528 0 1 AE r R786 "Row9" O318 A29 0 0 32800 2528 183 0 0 32800 2528 5 2 AE r R6C0 A4 r R6C0 O184 7064 800 O45 7064 800 O45 7224 800 O22 7224 0 OEC 7064 800 5 2 AE r R314 A4 r R314 O319 A9 10352 32 A6 AA 0 18184 608 O45 18184 608 O45 28504 608 O119 28504 0 O12F 18184 608 7 2 AE r R787 "/0(MiChip)/1(ClockGen)*1.[16]" A4 r R787 O31A A9 10992 32 A6 AA 0 11944 1504 O45 17464 1504 O45 11944 1504 O45 22904 1504 O100 22904 0 O100 17464 0 O100 11944 0 5 2 AE r RA1 A4 r RA1 O263 9624 1760 O45 9624 1760 O45 11944 1760 O130 11944 1760 O14D 9624 0 5 2 AE r R3F5 A4 r R3F5 O184 10344 2208 O45 10344 2208 O45 10504 2208 O11B 10504 0 O10A 10344 2208 5 2 AE r R5DB A4 r R5DB O184 12584 928 O45 12584 928 O45 12744 928 OEB 12744 0 OF0 12584 928 5 2 AE r RA5 A4 r RA5 O31B A9 5152 32 A6 AA 0 7864 864 O45 7864 864 O45 12984 864 O159 12984 0 OF7 7864 864 5 2 AE r R4E4 A4 r R4E4 O14B 21784 1120 O45 21784 1120 O45 22744 1120 O105 22744 0 OFE 21784 1120 7 2 AE r R788 "/0(MiChip)/2(MemCtlA)*1.Done" A4 r R788 O14A 15864 736 O45 19304 736 O45 15864 736 O45 19864 736 O14D 19864 736 O130 19304 0 O130 15864 0 5 2 AE r R789 "/0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)*1.[7]" A4 r R789 O18E 9304 1504 O45 9304 1504 O45 10744 1504 O100 10744 0 OF6 9304 1504 5 2 AE r R5DD A4 r R5DD O18E 27304 1696 O45 27304 1696 O45 28744 1696 O22 28744 1696 OEC 27304 0 5 2 AE r R18A A4 r R18A O1BB 14264 96 O45 14264 96 O45 19144 96 O112 19144 96 OFA 14264 0 5 2 AE r R4E9 A4 r R4E9 O18C 11384 1568 O45 11384 1568 O45 12184 1568 OF0 12184 0 OEB 11384 1568 5 2 AE r R78A "/0(MiChip)/2(MemCtlA)*1.S0" A4 r R78A O103 24184 736 O45 24184 736 O45 24744 736 O130 24744 0 O130 24184 0 5 2 AE r R78B "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21).[2]" A4 r R78B O2A7 1464 96 O45 1464 96 O45 7144 96 OFA 7144 0 O112 1464 96 5 2 AE r R78C "/0(MiChip)/4(RefreshCtr)/4(TstBuffer)*1.nInput[0]" A4 r R78C O15C 20984 736 O45 20984 736 O45 21224 736 O130 21224 0 O130 20984 0 3 2 AE r R78D "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[4]" A4 r R78D OFB 6664 544 O11E 6744 544 O102 6664 0 5 2 AE r R78E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2).[1]" A4 r R78E O111 9704 2400 O45 9704 2400 O45 10984 2400 OFA 10984 2400 O112 9704 0 5 2 AE r R6C2 A4 r R6C2 O180 22104 1248 O45 22104 1248 O45 22504 1248 OFD 22504 0 OFD 22104 1248 5 2 AE r R31D A4 r R31D O22F 20664 1760 O45 20664 1760 O45 25224 1760 O130 25224 1760 O14D 20664 0 5 2 AE r R78F "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2).[2]" A4 r R78F O140 8904 96 O45 8904 96 O45 9784 96 OFA 9784 0 OFA 8904 0 5 2 AE r R6C4 A4 r R6C4 O15C 1304 32 O45 1304 32 O45 1544 32 O10D 1544 32 OEE 1304 0 5 2 AE r R790 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21).[2]" A4 r R790 O12A 25784 480 O45 25784 480 O45 27704 480 O13D 27704 0 O13D 25784 0 5 2 AE r R4F0 A4 r R4F0 O2C4 6984 1440 O45 6984 1440 O45 14184 1440 OF1 14184 1440 O128 6984 0 7 2 AE r R791 "/0(MiChip)/2(MemCtlA)*1.WrSel" A4 r R791 O2CB 12424 1696 O45 12824 1696 O45 12424 1696 O45 14984 1696 OEC 14984 0 OEC 12824 0 O22 12424 1696 5 2 AE r RBD A4 r RBD O111 26424 928 O45 26424 928 O45 27704 928 OF0 27704 928 OEB 26424 0 5 2 AE r R5E2 A4 r R5E2 O2C6 8664 1184 O45 8664 1184 O45 13864 1184 O127 13864 0 O114 8664 1184 5 2 AE r RBE A4 r RBE OFF 22024 1184 O45 22024 1184 O45 24024 1184 O114 24024 1184 O127 22024 0 3 2 AE r R792 "PDout14" A4 r R792 O227 0 2276 O45 10504 2272 O31C A9 32 252 A6 AB 0 10504 2276 5 2 AE r RC0 A4 r RC0 O2A5 16344 1376 O45 16344 1376 O45 27544 1376 OFE 27544 0 O105 16344 1376 5 2 AE r R3FE A4 r R3FE O157 13064 2144 O45 13064 2144 O45 14904 2144 O13E 14904 0 OF4 13064 2144 5 2 AE r R793 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2).[1]" A4 r R793 OF2 24584 864 O45 24584 864 O45 25064 864 OF7 25064 864 O159 24584 0 3 2 AE r R794 "IOW'" A4 r R794 O2FB 22824 1252 O45 22824 1248 O31D A9 32 1276 A6 AB 0 22824 1252 5 2 AE r RC2 A4 r RC2 O2E2 13144 864 O45 13144 864 O45 20744 864 O159 20744 0 OF7 13144 864 3 2 AE r R795 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2).[2]" A4 r R795 OFB 24584 928 OEB 24664 0 OF0 24584 928 5 2 AE r RC4 A4 r RC4 O31E A9 7712 32 A6 AA 0 9144 1248 O45 9144 1248 O45 16824 1248 OFD 16824 0 OFD 9144 1248 5 2 AE r R4FB A4 r R4FB O10B 2504 544 O45 2504 544 O45 4184 544 O102 4184 0 O11E 2504 544 5 2 AE r R796 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[15]" A4 r R796 O18C 29624 32 O45 29624 32 O45 30424 32 O10D 30424 32 OEE 29624 0 5 2 AE r R5E5 A4 r R5E5 O1DC 18984 672 O45 18984 672 O45 26504 672 O11D 26504 0 O121 18984 672 7 2 AE r R4FD A4 r R4FD O31F A9 24272 32 A6 AA 0 1944 288 O45 23704 288 O45 1944 288 O45 26184 288 O11B 26184 288 O11B 23704 288 O10A 1944 0 5 2 AE r R797 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21).[2]" A4 r R797 O161 10424 2464 O45 10424 2464 O45 12184 2464 OEE 12184 2464 O10D 10424 0 5 2 AE r R798 "/0(MiChip)/6(AddrCtl)*1.[26]" A4 r R798 O2CB 19624 928 O45 19624 928 O45 22184 928 OEB 22184 0 OF0 19624 928 5 2 AE r R799 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2).[6]" A4 r R799 O28D 5304 1376 O45 5304 1376 O45 14824 1376 O105 14824 1376 OFE 5304 0 5 2 AE r R262 A4 r R262 O180 11064 1504 O45 11064 1504 O45 11464 1504 OF6 11464 1504 O100 11064 0 5 2 AE r R325 A4 r R325 O139 15064 1376 O45 15064 1376 O45 15704 1376 OFE 15704 0 O105 15064 1376 5 2 AE r RCF A4 r RCF O131 12824 2016 O45 12824 2016 O45 16264 2016 O13A 16264 0 O13D 12824 2016 5 2 AE r R405 A4 r R405 OF5 16424 1696 O45 16424 1696 O45 17944 1696 O22 17944 1696 OEC 16424 0 5 2 AE r R79A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[4]" A4 r R79A O263 18424 1120 O45 18424 1120 O45 20744 1120 OFE 20744 1120 O105 18424 0 5 2 AE r R4FE A4 r R4FE O2EF 9864 1824 O45 9864 1824 O45 13784 1824 O11D 13784 1824 O121 9864 0 5 2 AE r R1A1 A4 r R1A1 O1BC 20504 480 O45 20504 480 O45 24344 480 O13A 24344 480 O13D 20504 0 5 2 AE r R1A0 A4 r R1A0 O111 4344 32 O45 4344 32 O45 5624 32 O10D 5624 32 OEE 4344 0 7 2 AE r R406 A4 r R406 O2E2 6904 416 O45 11224 416 O45 6904 416 O45 14504 416 O10C 14504 0 O133 11224 416 O10C 6904 0 5 2 AE r RD5 A4 r RD5 O320 A9 12672 32 A6 AA 0 4504 160 O45 4504 160 O45 17144 160 O10E 17144 0 O109 4504 160 5 2 AE r R5E7 A4 r R5E7 O281 23384 1440 O45 23384 1440 O45 30824 1440 OF1 30824 1440 O128 23384 0 7 2 AE r R79B "/0(MiChip)/5(DataMux)*1.[39][2]" A4 r R79B O2C1 2264 352 O45 3384 352 O45 2264 352 O45 5464 352 O13E 5464 352 OF4 3384 0 OF4 2264 0 5 2 AE r R500 A4 r R500 O18C 19784 1312 O45 19784 1312 O45 20584 1312 O114 20584 0 O127 19784 1312 5 2 AE r R266 A4 r R266 O10B 23544 1696 O45 23544 1696 O45 25224 1696 OEC 25224 0 O22 23544 1696 7 2 AE r R409 A4 r R409 O2E2 7064 736 O45 11144 736 O45 7064 736 O45 14664 736 O130 14664 0 O14D 11144 736 O130 7064 0 5 2 AE r R79C "/0(MiChip)/2(MemCtlA)*1.RQ" A4 r R79C O18E 18904 480 O45 18904 480 O45 20344 480 O13D 20344 0 O13A 18904 480 5 2 AE r R501 A4 r R501 O103 7624 800 O45 7624 800 O45 8184 800 O22 8184 0 OEC 7624 800 5 2 AE r R40B A4 r R40B O2F7 2184 416 O45 2184 416 O45 6504 416 O133 6504 416 O10C 2184 0 5 2 AE r R79D "/0(MiChip)/5(DataMux)/3(TstBuffer)*1.nInput[5]" A4 r R79D O12E 21704 864 O45 21704 864 O45 22424 864 O159 22424 0 OF7 21704 864 5 2 AE r R6CB A4 r R6CB O180 22184 1312 O45 22184 1312 O45 22584 1312 O114 22584 0 O127 22184 1312 5 2 AE r R79E "/0(MiChip)/6(AddrCtl)*1.[18]" A4 r R79E O139 22344 928 O45 22344 928 O45 22984 928 OEB 22984 0 OEB 22344 0 5 2 AE r R40C A4 r R40C O2A3 27544 1504 O45 27544 1504 O45 28584 1504 O100 28584 0 OF6 27544 1504 7 2 AE r R79F "/0(MiChip)/5(DataMux)*1.[23][5]" A4 r R79F O2EF 6664 608 O45 6824 608 O45 6664 608 O45 10584 608 O119 10584 0 O119 6824 0 O12F 6664 608 5 2 AE r R6CD A4 r R6CD O321 A9 5072 32 A6 AA 0 22344 992 O45 22344 992 O45 27384 992 OF6 27384 0 O100 22344 992 5 2 AE r RDB A4 r RDB O252 17624 352 O45 17624 352 O45 27064 352 OF4 27064 0 O13E 17624 352 5 2 AE r R6CE A4 r R6CE O31B 10184 2080 O45 10184 2080 O45 15304 2080 O133 15304 0 O10C 10184 2080 5 2 AE r R5EA A4 r R5EA O1E0 19064 1056 O45 19064 1056 O45 27224 1056 OF1 27224 0 O128 19064 1056 5 2 AE r R328 A4 r R328 O322 A9 3792 32 A6 AA 0 10264 800 O45 10264 800 O45 14024 800 O22 14024 0 OEC 10264 800 5 2 AE r R504 A4 r R504 O184 16824 1824 O45 16824 1824 O45 16984 1824 O121 16984 0 O11D 16824 1824 5 2 AE r R7A0 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[8]" A4 r R7A0 O323 A9 14752 32 A6 AA 0 14344 800 O45 14344 800 O45 29064 800 OEC 29064 800 O22 14344 0 7 2 AE r R7A1 "/0(MiChip)/4(RefreshCtr)*1.[9]" A4 r R7A1 O324 A9 10512 32 A6 AA 0 6104 352 O45 6504 352 O45 6104 352 O45 16584 352 O13E 16584 352 OF4 6504 0 O13E 6104 352 5 2 AE r R6CF A4 r R6CF O294 8344 928 O45 8344 928 O45 12504 928 OF0 12504 928 OEB 8344 0 5 2 AE r R5EC A4 r R5EC O2F7 2424 480 O45 2424 480 O45 6744 480 O13D 6744 0 O13A 2424 480 5 2 AE r R410 A4 r R410 O15A 25384 864 O45 25384 864 O45 28264 864 O159 28264 0 OF7 25384 864 5 2 AE r R506 A4 r R506 O30A 1864 32 O45 1864 32 O45 3944 32 O10D 3944 32 OEE 1864 0 5 2 AE r R1A3 A4 r R1A3 O301 8424 1056 O45 8424 1056 O45 18664 1056 OF1 18664 0 O128 8424 1056 5 2 AE r R7A2 "/0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)*1.[3]" A4 r R7A2 O184 18584 1312 O45 18584 1312 O45 18744 1312 O114 18744 0 O127 18584 1312 5 2 AE r R32A A4 r R32A O141 14824 1312 O45 14824 1312 O45 17064 1312 O127 17064 1312 O114 14824 0 5 2 AE r R5F0 A4 r R5F0 O15C 4024 32 O45 4024 32 O45 4264 32 OEE 4264 0 O10D 4024 32 5 2 AE r R50A A4 r R50A O184 30504 32 O45 30504 32 O45 30664 32 OEE 30664 0 O10D 30504 32 5 2 AE r RE0 A4 r RE0 O184 20664 1952 O45 20664 1952 O45 20824 1952 O11E 20824 0 O102 20664 1952 5 2 AE r R6D1 A4 r R6D1 O197 16184 1120 O45 16184 1120 O45 17784 1120 OFE 17784 1120 O105 16184 0 5 2 AE r R5F1 A4 r R5F1 O18E 22664 864 O45 22664 864 O45 24104 864 OF7 24104 864 O159 22664 0 5 2 AE r R1A5 A4 r R1A5 O2C8 15544 992 O45 15544 992 O45 22264 992 O100 22264 992 OF6 15544 0 5 2 AE r R1A6 A4 r R1A6 O2C7 10104 1952 O45 10104 1952 O45 15384 1952 O11E 15384 0 O102 10104 1952 5 2 AE r R414 A4 r R414 O15A 14104 2272 O45 14104 2272 O45 16984 2272 O107 16984 2272 OF3 14104 0 5 2 AE r R7A3 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[1]" A4 r R7A3 O161 8264 800 O45 8264 800 O45 10024 800 O22 10024 0 O22 8264 0 5 2 AE r R26A A4 r R26A O2EF 19544 96 O45 19544 96 O45 23464 96 OFA 23464 0 O112 19544 96 3 2 AE r R5F3 A4 r R5F3 O135 8584 36 O136 8584 0 O325 A9 32 2492 A6 AB 0 8584 36 5 2 AE r R50E A4 r R50E O12E 7784 96 O45 7784 96 O45 8504 96 OFA 8504 0 O112 7784 96 5 2 AE r R5F4 A4 r R5F4 O161 19704 1184 O45 19704 1184 O45 21464 1184 O127 21464 0 O114 19704 1184 5 2 AE r R1A9 A4 r R1A9 O275 6904 480 O45 6904 480 O45 18504 480 O13D 18504 0 O13A 6904 480 5 2 AE r R1AA A4 r R1AA O118 19944 736 O45 19944 736 O45 20264 736 O130 20264 0 O14D 19944 736 5 2 AE r R1AB A4 r R1AB OFF 28344 160 O45 28344 160 O45 30344 160 O109 30344 160 O10E 28344 0 9 2 AE r R6D3 A4 r R6D3 O156 22824 1120 O45 25464 1120 O45 22824 1120 O45 29224 1120 O45 29864 1120 O105 29864 0 OFE 25464 1120 OFE 29224 1120 O105 22824 0 5 2 AE r R7A4 "PDTPin" A4 r R7A4 O184 5784 352 O45 5784 352 O45 5944 352 O13E 5944 352 OF4 5784 0 7 2 AE r R7A5 "/0(MiChip)/2(MemCtlA)/12(fsmc1)/0(Decoder)*1.nEnable" A4 r R7A5 O18C 24824 480 O45 25064 480 O45 24824 480 O45 25624 480 O13D 25624 0 O13D 25064 0 O13D 24824 0 5 2 AE r R41A A4 r R41A O10B 10984 2208 O45 10984 2208 O45 12664 2208 O10A 12664 2208 O11B 10984 0 5 2 AE r R1AE A4 r R1AE O326 A9 17232 32 A6 AA 0 10104 1888 O45 10104 1888 O45 27304 1888 O119 27304 1888 O12F 10104 0 5 2 AE r R7A6 "/0(MiChip)/2(MemCtlA)*1.[9]" A4 r R7A6 O15C 25144 736 O45 25144 736 O45 25384 736 O130 25384 0 O130 25144 0 5 2 AE r R1B1 A4 r R1B1 OF2 17384 32 O45 17384 32 O45 17864 32 O10D 17864 32 OEE 17384 0 5 2 AE r R33C A4 r R33C O184 1624 32 O45 1624 32 O45 1784 32 OEE 1784 0 O10D 1624 32 5 2 AE r R7A7 "/0(MiChip)/1(ClockGen)*1.[1]" A4 r R7A7 O197 21624 736 O45 21624 736 O45 23224 736 O130 23224 0 O14D 21624 736 3 2 AE r R7A8 "/0(MiChip)/4(RefreshCtr)*1.[1][5]" A4 r R7A8 OFB 5144 32 OEE 5224 0 OEE 5144 0 5 2 AE r R7A9 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[5]" A4 r R7A9 O180 10664 1568 O45 10664 1568 O45 11064 1568 OEB 11064 1568 OF0 10664 0 11 2 AE r R41D A4 r R41D O327 A9 21952 32 A6 AA 0 5544 2336 O45 8344 2336 O45 24264 2336 O45 5544 2336 O45 14104 2336 O45 27464 2336 O109 27464 0 O10E 8344 2336 O10E 14104 2336 O10E 24264 2336 O10E 5544 2336 5 2 AE r R513 A4 r R513 O15B 14424 1184 O45 14424 1184 O45 16904 1184 O127 16904 0 O114 14424 1184 5 2 AE r R514 A4 r R514 O140 20264 1440 O45 20264 1440 O45 21144 1440 O128 21144 0 OF1 20264 1440 5 2 AE r R7AA "/0(MiChip)/2(MemCtlA)*1.[64]" A4 r R7AA O139 15304 2144 O45 15304 2144 O45 15944 2144 O13E 15944 0 OF4 15304 2144 5 2 AE r R7AB "/0(MiChip)/1(ClockGen)*1.[2]" A4 r R7AB OF2 30104 224 O45 30104 224 O45 30584 224 O107 30584 0 OF3 30104 224 5 2 AE r R341 A4 r R341 O161 3624 224 O45 3624 224 O45 5384 224 OF3 5384 224 O107 3624 0 5 2 AE r R515 A4 r R515 O2C3 11544 96 O45 11544 96 O45 13944 96 OFA 13944 0 O112 11544 96 11 2 AE r R41F A4 r R41F O327 5704 224 O45 8504 224 O45 24424 224 O45 5704 224 O45 14264 224 O45 27624 224 O107 27624 0 OF3 8504 224 OF3 14264 224 OF3 24424 224 OF3 5704 224 5 2 AE r R6DB A4 r R6DB O111 13944 992 O45 13944 992 O45 15224 992 OF6 15224 0 O100 13944 992 5 2 AE r R7AC "/0(MiChip)/4(RefreshCtr)*1.[1][9]" A4 r R7AC O143 9384 1568 O45 9384 1568 O45 10584 1568 OEB 10584 1568 OF0 9384 0 3 2 AE r R6DD A4 r R6DD OFB 15144 1056 O128 15224 1056 OF1 15144 0 5 2 AE r R7AD "/0(MiChip)/4(RefreshCtr)*1.Output[4]" A4 r R7AD O120 26504 1184 O45 26504 1184 O45 29144 1184 O127 29144 0 O114 26504 1184 5 2 AE r R423 A4 r R423 O143 27224 1312 O45 27224 1312 O45 28424 1312 O114 28424 0 O127 27224 1312 5 2 AE r R7AE "/0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)*1.[3]" A4 r R7AE O328 A9 3552 32 A6 AA 0 13224 928 O45 13224 928 O45 16744 928 OEB 16744 0 OF0 13224 928 5 2 AE r REE A4 r REE O1CD 6024 32 O45 6024 32 O45 17304 32 OEE 17304 0 O10D 6024 32 7 2 AE r R7AF "/0(MiChip)/4(RefreshCtr)*1.Output[5]" A4 r R7AF O329 A9 24032 32 A6 AA 0 5064 544 O45 18264 544 O45 5064 544 O45 29064 544 O102 29064 0 O102 18264 0 O102 5064 0 5 2 AE r R7B0 "/0(MiChip)/4(RefreshCtr)*1.[8][13]" A4 r R7B0 O32A A9 10672 32 A6 AA 0 9464 1632 O45 9464 1632 O45 20104 1632 OF7 20104 0 OF7 9464 0 5 2 AE r R1B4 A4 r R1B4 O14B 1704 224 O45 1704 224 O45 2664 224 O107 2664 0 OF3 1704 224 5 2 AE r R7B1 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[7]" A4 r R7B1 O287 4104 864 O45 4104 864 O45 7224 864 OF7 7224 864 O159 4104 0 5 2 AE r R6DE A4 r R6DE OFF 11784 992 O45 11784 992 O45 13784 992 OF6 13784 0 O100 11784 992 5 2 AE r R519 A4 r R519 O197 17064 1184 O45 17064 1184 O45 18664 1184 O114 18664 1184 O127 17064 0 5 2 AE r R7B2 "/0(MiChip)/4(RefreshCtr)*1.[8][8]" A4 r R7B2 O290 27144 288 O45 27144 288 O45 31384 288 O10A 31384 0 O11B 27144 288 5 2 AE r R7B3 "/0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)*1.[3]" A4 r R7B3 O12E 12344 1568 O45 12344 1568 O45 13064 1568 OF0 13064 0 OEB 12344 1568 5 2 AE r R7B4 "/0(MiChip)/2(MemCtlA)*1.[68]" A4 r R7B4 O12E 15064 736 O45 15064 736 O45 15784 736 O130 15784 0 O130 15064 0 5 2 AE r RB A4 r RB O161 23144 1312 O45 23144 1312 O45 24904 1312 O114 24904 0 O127 23144 1312 5 2 AE r R604 A4 r R604 O111 15624 1440 O45 15624 1440 O45 16904 1440 OF1 16904 1440 O128 15624 0 3 2 AE r R7B5 "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)*1.[5]" A4 r R7B5 OFB 7544 32 OEE 7624 0 O10D 7544 32 3 2 AE r R7B6 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[5]" A4 r R7B6 OFB 27864 32 OEE 27944 0 OEE 27864 0 5 2 AE r R6E1 A4 r R6E1 O263 3464 672 O45 3464 672 O45 5784 672 O121 5784 672 O11D 3464 0 5 2 AE r R34C A4 r R34C O15A 23544 1504 O45 23544 1504 O45 26424 1504 OF6 26424 1504 O100 23544 0 5 2 AE r R6E2 A4 r R6E2 O184 5704 32 O45 5704 32 O45 5864 32 O10D 5864 32 OEE 5704 0 5 2 AE r R7B7 "/0(MiChip)/1(ClockGen)/3(ffR)*1.[7]" A4 r R7B7 O118 23304 736 O45 23304 736 O45 23624 736 O14D 23624 736 O130 23304 0 5 2 AE r R7B8 "/0(MiChip)/1(ClockGen)*1.[7]" A4 r R7B8 O285 11624 608 O45 11624 608 O45 18104 608 O119 18104 0 O12F 11624 608 5 2 AE r R7B9 "/0(MiChip)/4(RefreshCtr)*1.Output[8]" A4 r R7B9 O32B A9 14832 32 A6 AA 0 13624 1568 O45 13624 1568 O45 28424 1568 OEB 28424 1568 OF0 13624 0 5 2 AE r R6E5 A4 r R6E5 O305 8424 992 O45 8424 992 O45 11704 992 O100 11704 992 OF6 8424 0 5 2 AE r R42B A4 r R42B O2A3 27624 352 O45 27624 352 O45 28664 352 OF4 28664 0 O13E 27624 352 5 2 AE r R7BA "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[6]" A4 r R7BA O118 26664 288 O45 26664 288 O45 26984 288 O10A 26984 0 O10A 26664 0 5 2 AE r R103 A4 r R103 O32C A9 6912 32 A6 AA 0 8664 1120 O45 8664 1120 O45 15544 1120 OFE 15544 1120 O105 8664 0 5 2 AE r R1BC A4 r R1BC O2CB 10184 2016 O45 10184 2016 O45 12744 2016 O13D 12744 2016 O13A 10184 0 5 2 AE r R7BB "/0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)*1.[3]" A4 r R7BB O11C 2584 608 O45 2584 608 O45 3704 608 O119 3704 0 O119 2584 0 5 2 AE r R7BC "/0(MiChip)/1(ClockGen)*1.[8]" A4 r R7BC O1CD 18184 32 O45 18184 32 O45 29464 32 O10D 29464 32 OEE 18184 0 7 2 AE r R7BD "/0(MiChip)/4(RefreshCtr)*1.Output[9]" A4 r R7BD O1BB 9304 1312 O45 13544 1312 O45 9304 1312 O45 14184 1312 O114 14184 0 O114 13544 0 O114 9304 0 5 2 AE r R7BE "/0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)*1.[7]" A4 r R7BE O184 25144 864 O45 25144 864 O45 25304 864 O159 25304 0 OF7 25144 864 5 2 AE r R107 A4 r R107 O140 27784 480 O45 27784 480 O45 28664 480 O13A 28664 480 O13D 27784 0 5 2 AE r R6E7 A4 r R6E7 O111 5304 1440 O45 5304 1440 O45 6584 1440 O128 6584 0 OF1 5304 1440 3 2 AE r R7BF "/0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)*1.[5]" A4 r R7BF OFB 3784 32 O10D 3864 32 OEE 3784 0 5 2 AE r R1C2 A4 r R1C2 O2CB 10344 2144 O45 10344 2144 O45 12904 2144 OF4 12904 2144 O13E 10344 0 5 2 AE r R60C A4 r R60C O15C 7464 96 O45 7464 96 O45 7704 96 O112 7704 96 OFA 7464 0 5 2 AE r R7C0 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21).[2]" A4 r R7C0 O2A9 17464 1824 O45 17464 1824 O45 21944 1824 O121 21944 0 O11D 17464 1824 5 2 AE r R7C1 "/0(MiChip)/1(ClockGen)*1.[9]" A4 r R7C1 O321 12664 1760 O45 12664 1760 O45 17704 1760 O14D 17704 0 O14D 12664 0 5 2 AE r R1C7 A4 r R1C7 O32D A9 4752 32 A6 AA 0 26584 96 O45 26584 96 O45 31304 96 O112 31304 96 OFA 26584 0 5 2 AE r R432 A4 r R432 O111 8104 1632 O45 8104 1632 O45 9384 1632 O159 9384 1632 OF7 8104 0 5 2 AE r R524 A4 r R524 OF2 26104 736 O45 26104 736 O45 26584 736 O14D 26584 736 O130 26104 0 3 2 AE r R356 A4 r R356 O135 8024 36 O136 8024 0 O325 8024 36 5 2 AE r R6EC A4 r R6EC O2E2 21144 1632 O45 21144 1632 O45 28744 1632 OF7 28744 0 O159 21144 1632 3 2 AE r R7C2 "PDin15" A4 r R7C2 O274 0 356 O45 1944 352 O2FC 1944 356 5 2 AE r R10A A4 r R10A O263 9544 1696 O45 9544 1696 O45 11864 1696 O22 11864 1696 OEC 9544 0 7 2 AE r R436 A4 r R436 O287 23144 928 O45 26104 928 O45 23144 928 O45 26264 928 OF0 26264 928 OF0 26104 928 OEB 23144 0 5 2 AE r R7C3 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][1]" A4 r R7C3 O2C5 23864 96 O45 23864 96 O45 26024 96 OFA 26024 0 O112 23864 96 5 2 AE r R6ED A4 r R6ED OF2 20584 1632 O45 20584 1632 O45 21064 1632 OF7 21064 0 O159 20584 1632 5 2 AE r R10D A4 r R10D O32E A9 11792 32 A6 AA 0 14584 416 O45 14584 416 O45 26344 416 O10C 26344 0 O133 14584 416 5 2 AE r R7C4 "/0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)*1.[5]" A4 r R7C4 O11F 1704 160 O45 1704 160 O45 3064 160 O109 3064 160 O10E 1704 0 5 2 AE r R7C5 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][2]" A4 r R7C5 O2C3 26824 416 O45 26824 416 O45 29224 416 O10C 29224 0 O10C 26824 0 5 2 AE r R7C6 "/0(MiChip)/2(MemCtlA)/44(fsm1)/0(ffR)*1.[7]" A4 r R7C6 O12E 28584 1568 O45 28584 1568 O45 29304 1568 OF0 29304 0 OEB 28584 1568 3 2 AE r R7C7 "/0(MiChip)/1(ClockGen)*1.[12]" A4 r R7C7 O32F A9 192 32 A6 AB 0 29944 32 OEE 30104 0 O10D 29944 32 5 2 AE r R616 A4 r R616 O290 17224 1248 O45 17224 1248 O45 21464 1248 OFD 21464 1248 OFD 17224 0 5 2 AE r R112 A4 r R112 O30D 17544 160 O45 17544 160 O45 27144 160 O10E 27144 0 O109 17544 160 5 2 AE r R1CC A4 r R1CC O111 18104 928 O45 18104 928 O45 19384 928 OEB 19384 0 OF0 18104 928 5 2 AE r R1CE A4 r R1CE O2B0 13704 2208 O45 13704 2208 O45 21544 2208 O11B 21544 0 O10A 13704 2208 5 2 AE r R6EF A4 r R6EF O131 14904 2400 O45 14904 2400 O45 18344 2400 O112 18344 0 OFA 14904 2400 5 2 AE r R52F A4 r R52F O140 3544 160 O45 3544 160 O45 4424 160 O109 4424 160 O10E 3544 0 5 2 AE r R1D1 A4 r R1D1 O32E 6824 672 O45 6824 672 O45 18584 672 O11D 18584 0 O121 6824 672 5 2 AE r R6F0 A4 r R6F0 O118 15144 1440 O45 15144 1440 O45 15464 1440 O128 15464 0 OF1 15144 1440 5 2 AE r R7C8 "/0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)*1.[4]" A4 r R7C8 OF2 10904 608 O45 10904 608 O45 11384 608 O119 11384 0 O119 10904 0 5 2 AE r R6F1 A4 r R6F1 O11F 9944 96 O45 9944 96 O45 11304 96 O112 11304 96 OFA 9944 0 0 0 31360 0 1 AE r R7C9 "MIInnerChan10" O330 A2 0 0 32800 856 140 O331 A2 0 0 1440 832 4 O332 A2 0 0 1440 80 1 O333 A9 1440 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 1440 80 R2 1059061760 0 0 0 0 0 0 0 O334 A2 0 0 1440 80 1 O333 0 0 0 2 A4 r RB AE r RB 0 0 1440 80 R2 1059061760 0 0 0 0 0 0 0 O335 A2 0 0 1440 80 1 O333 0 0 0 2 A4 r RC AE r RC 0 0 1440 80 R2 1059061760 0 0 0 0 752 0 0 O336 A2 0 0 1440 80 1 O333 0 0 0 2 A4 r RC AE r RC 0 0 1440 80 R2 1059061760 0 0 0 0 752 0 0 0 0 1440 832 R7CA "MIInnerLeft10" 1031153506 0 1 0 0 0 0 0 O86 1440 0 0 2 AE r R7CB "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 1584 0 0 2 AE r R7CC "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)*1.[4]-10" A1A a A1A O24 1680 0 0 2 AE r R7CD "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 2480 0 0 2 AE r R7CE "/0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1" A1A a A1A ODD 2960 0 0 2 AE r R7CF "/0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1" A1A a A1A ODD 3440 0 0 2 AE r R7D0 "/0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 3920 0 0 2 AE r R7D1 "/0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1" A1A a A1A O18 4384 0 0 2 AE r R7D2 "/0(MiChip)/5(DataMux)*1.[11][8]-10" A1A a A1A O24 4480 0 0 2 AE r R7D3 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1" A1A a A1A O18 5264 0 0 2 AE r R7D4 "/0(MiChip)/7(StatusReg)*1.[14][1]-10" A1A a A1A O18 5344 0 0 2 AE r R7D5 "/0(MiChip)/5(DataMux)*1.[15][7]-10" A1A a A1A OA4 5440 0 0 2 AE r R7D6 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 5824 0 0 2 AE r R7D7 "/0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)*1.[4]-10" A1A a A1A O18 5904 0 0 2 AE r R7D8 "PDTPin-10" A1A a A1A O171 6000 0 0 2 AE r R7D9 "/0(MiChip)/4(RefreshCtr)/0(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O86 6320 0 0 2 AE r R7DA "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/13(counterUpCtrl2)/5(Inv)*1" A1A a A1A O86 6480 0 0 2 AE r R7DB "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv3" A1A a A1A O18 6624 0 0 2 AE r R7DC "/0(MiChip)/5(DataMux)*1.[23][5]-10" A1A a A1A OCE 6720 0 0 2 AE r R7DD "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver4" A1A a A1A O18 7024 0 0 2 AE r R7DE "PDin35-10" A1A a A1A ODD 7120 0 0 2 AE r R7DF "/0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 7584 0 0 2 AE r R7E0 "/0(MiChip)/5(DataMux)*1.[23][4]-10" A1A a A1A O18 7664 0 0 2 AE r R7E1 "/0(MiChip)/7(StatusReg)*1.[14][2]-10" A1A a A1A O18 7744 0 0 2 AE r R7E2 "Dout14-10" A1A a A1A O18 7824 0 0 2 AE r R7E3 "/0(MiChip)*1.RASX-10" A1A a A1A O168 7920 0 0 2 AE r R7E4 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/0(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A OA4 8240 0 0 2 AE r R7E5 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 8640 0 0 2 AE r R7E6 "/0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1" A1A a A1A O86 9120 0 0 2 AE r R7E7 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv14" A1A a A1A O18 9264 0 0 2 AE r R7E8 "/0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)*1.[7]-10" A1A a A1A ODD 9360 0 0 2 AE r R7E9 "/0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1" A1A a A1A OCE 9840 0 0 2 AE r R7EA "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver3" A1A a A1A O18 10144 0 0 2 AE r R7EB "/0(MiChip)/5(DataMux)*1.[17]-10" A1A a A1A O18 10224 0 0 2 AE r R7EC "/0(MiChip)/5(DataMux)*1.[23][6]-10" A1A a A1A O18 10304 0 0 2 AE r R7ED "PDin36-10" A1A a A1A O86 10400 0 0 2 AE r R7EE "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OB6 10560 0 0 2 AE r R7EF "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1" A1A a A1A O18 11024 0 0 2 AE r R7F0 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[5]-10" A1A a A1A O18 11104 0 0 2 AE r R7F1 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[1]-10" A1A a A1A O18 11184 0 0 2 AE r R7F2 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)*1.decoded[0]-10" A1A a A1A O18 11264 0 0 2 AE r R7F3 "/0(MiChip)/5(DataMux)*1.[11][9]-10" A1A a A1A O18 11344 0 0 2 AE r R7F4 "/0(MiChip)*1.[4]-10" A1A a A1A O18 11424 0 0 2 AE r R7F5 "PDout35-10" A1A a A1A O18 11504 0 0 2 AE r R7F6 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[6]-10" A1A a A1A O18 11584 0 0 2 AE r R7F7 "/0(MiChip)/1(ClockGen)*1.[7]-10" A1A a A1A O18 11664 0 0 2 AE r R7F8 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv).nEnable-10" A1A a A1A OA4 11760 0 0 2 AE r R7F9 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 12160 0 0 2 AE r R7FA "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 12304 0 0 2 AE r R7FB "/0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)*1.[3]-10" A1A a A1A O18 12384 0 0 2 AE r R7FC "/0(MiChip)/2(MemCtlA)*1.WrSel-10" A1A a A1A O18 12464 0 0 2 AE r R7FD "/0(MiChip)/5(DataMux)/8(DataLatchMux)*1.[4]-10" A1A a A1A O18 12544 0 0 2 AE r R7FE "PDin37-10" A1A a A1A OA4 12640 0 0 2 AE r R7FF "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 13024 0 0 2 AE r R800 "/0(MiChip)/7(StatusReg)*1.[16][2]-10" A1A a A1A O18 13104 0 0 2 AE r R801 "Dout6-10" A1A a A1A ODD 13200 0 0 2 AE r R802 "/0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 13664 0 0 2 AE r R803 "Dout0-10" A1A a A1A O86 13760 0 0 2 AE r R804 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv1" A1A a A1A O18 13904 0 0 2 AE r R805 "/0(MiChip)/2(MemCtlA)*1.Accept-10" A1A a A1A OA4 14000 0 0 2 AE r R806 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 14400 0 0 2 AE r R807 "/0(MiChip)/2(MemCtlA)/33(Inv)*1" A1A a A1A O18 14544 0 0 2 AE r R808 "/0(MiChip)*1.LdStatus[0]-10" A1A a A1A OCA 14640 0 0 2 AE r R809 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O86 14880 0 0 2 AE r R80A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/3/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/4/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/5/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/2/0(Inv)*1*1*1*1*1" A1A a A1A O18 15024 0 0 2 AE r R80B "/0(MiChip)/2(MemCtlA)*1.WrHCy-10" A1A a A1A O18 15104 0 0 2 AE r R80C "PDin32-10" A1A a A1A O168 15200 0 0 2 AE r R80D "/0(MiChip)/2(MemCtlA)/42(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O24 15520 0 0 2 AE r R80E "/0(MiChip)/4(RefreshCtr)/1(ffRP)/0(FF)*1" A1A a A1A O18 16304 0 0 2 AE r R80F "Din11-10" A1A a A1A OA4 16400 0 0 2 AE r R810 "/0(MiChip)/4(RefreshCtr)/1(ffRP)/1(A22o2i)*1" A1A a A1A O18 16784 0 0 2 AE r R811 "PDout37-10" A1A a A1A O18 16864 0 0 2 AE r R812 "/0(MiChip)/2(MemCtlA)*1.[78]-10" A1A a A1A ODD 16960 0 0 2 AE r R813 "/0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 17424 0 0 2 AE r R814 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21).[2]-10" A1A a A1A O18 17504 0 0 2 AE r R815 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv).nEnable-10" A1A a A1A O18 17584 0 0 2 AE r R816 "/0(MiChip)*1.LdAddrHi[1]-10" A1A a A1A O86 17680 0 0 2 AE r R817 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 17824 0 0 2 AE r R818 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two-10" A1A a A1A O86 17920 0 0 2 AE r R819 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv2" A1A a A1A O18 18064 0 0 2 AE r R81A "RPadEnb-10" A1A a A1A O18 18144 0 0 2 AE r R81B "Dout1-10" A1A a A1A O168 18240 0 0 2 AE r R81C "/0(MiChip)/2(MemCtlA)/22(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 18544 0 0 2 AE r R81D "/0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)*1.[3]-10" A1A a A1A O171 18640 0 0 2 AE r R81E "/0(MiChip)/2(MemCtlA)/26(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O18 18944 0 0 2 AE r R81F "/0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)*1.[5]-10" A1A a A1A O18 19024 0 0 2 AE r R820 "Dout9-10" A1A a A1A O86 19120 0 0 2 AE r R821 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/4/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/5/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/2/0(Inv)*1*1*1" A1A a A1A OCA 19280 0 0 2 AE r R822 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 19504 0 0 2 AE r R823 "Dout13-10" A1A a A1A O18 19584 0 0 2 AE r R824 "/0(MiChip)/6(AddrCtl)*1.[26]-10" A1A a A1A O18 19664 0 0 2 AE r R825 "Dout15-10" A1A a A1A O18 19744 0 0 2 AE r R826 "PDout36-10" A1A a A1A O168 19840 0 0 2 AE r R827 "/0(MiChip)/2(MemCtlA)/27(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A ODD 20160 0 0 2 AE r R828 "/0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1" A1A a A1A OCA 20640 0 0 2 AE r R829 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O171 20880 0 0 2 AE r R82A "/0(MiChip)/6(AddrCtl)/3(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O86 21200 0 0 2 AE r R82B "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/1(Inv)" A1A a A1A O171 21360 0 0 2 AE r R82C "/0(MiChip)/1(ClockGen)/4(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O18 21664 0 0 2 AE r R82D "/0(MiChip)/5(DataMux)/3(TstBuffer)*1.nInput[5]-10" A1A a A1A O18 21744 0 0 2 AE r R82E "PDin38-10" A1A a A1A O86 21840 0 0 2 AE r R82F "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv7" A1A a A1A OCE 22000 0 0 2 AE r R830 "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver4" A1A a A1A O86 22320 0 0 2 AE r R831 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv4" A1A a A1A OCE 22480 0 0 2 AE r R832 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver4" A1A a A1A O86 22800 0 0 2 AE r R833 "/0(MiChip)/6(AddrCtl)/11(Inv)*1" A1A a A1A O86 22960 0 0 2 AE r R834 "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/1(Inv)" A1A a A1A O86 23120 0 0 2 AE r R835 "/0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv7" A1A a A1A OCE 23280 0 0 2 AE r R836 "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver7" A1A a A1A OAF 23600 0 0 2 AE r R837 "/0(MiChip)/1(ClockGen)/3(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O18 23824 0 0 2 AE r R838 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[11][1]-10" A1A a A1A O86 23920 0 0 2 AE r R839 "/0(MiChip)/6(AddrCtl)/10(Decoder)/8(Inv)" A1A a A1A O18 24064 0 0 2 AE r R83A "Dout10-10" A1A a A1A OA4 24160 0 0 2 AE r R83B "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 24544 0 0 2 AE r R83C "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2).[2]-10" A1A a A1A OB6 24640 0 0 2 AE r R83D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1*1*1*1*1*1*1" A1A a A1A O18 25104 0 0 2 AE r R83E "/0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)*1.[7]-10" A1A a A1A OCA 25200 0 0 2 AE r R83F "/0(MiChip)/6(AddrCtl)/4(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O24 25440 0 0 2 AE r R840 "/0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1" A1A a A1A O16D 26240 0 0 2 AE r R841 "/0(MiChip)/1(ClockGen)/0(B)/Buffer0" A1A a A1A O18 26464 0 0 2 AE r R842 "/0(MiChip)/4(RefreshCtr)*1.Output[4]-10" A1A a A1A O18 26544 0 0 2 AE r R843 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][1]-10" A1A a A1A OB6 26640 0 0 2 AE r R844 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1*1*1*1*1*1" A1A a A1A O18 27104 0 0 2 AE r R845 "/0(MiChip)/4(RefreshCtr)*1.[8][8]-10" A1A a A1A O18 27184 0 0 2 AE r R846 "/0(MiChip)/4(RefreshCtr)*1.[8][12]-10" A1A a A1A O86 27280 0 0 2 AE r R847 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv2" A1A a A1A OCE 27440 0 0 2 AE r R848 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver2" A1A a A1A O24 27760 0 0 2 AE r R849 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1*1" A1A a A1A O18 28544 0 0 2 AE r R84A "/0(MiChip)/2(MemCtlA)/44(fsm1)/0(ffR)*1.[7]-10" A1A a A1A O18 28624 0 0 2 AE r R84B "/0(MiChip)/3(AddrMux)*1.In1[0]-10" A1A a A1A O18 28704 0 0 2 AE r R84C "/0(MiChip)/3(AddrMux)*1.[19][1]-10" A1A a A1A O86 28800 0 0 2 AE r R84D "/0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv3" A1A a A1A OCA 28960 0 0 2 AE r R84E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O24 29200 0 0 2 AE r R84F "/0(MiChip)/1(ClockGen)/7(FF)*1" A1A a A1A O168 30000 0 0 2 AE r R850 "/0(MiChip)/1(ClockGen)/5(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 30304 0 0 2 AE r R851 "/0(MiChip)/2(MemCtlA)*1.C1-10" A1A a A1A O18 30384 0 0 2 AE r R852 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[15]-10" A1A a A1A O18 30464 0 0 2 AE r R853 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11).Two-10" A1A a A1A O24 30560 0 0 2 AE r R854 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1" A1A a A1A O337 A2 0 0 1440 832 2 O338 A2 0 0 1440 80 1 O333 0 0 0 2 A4 r RB AE r RB 0 0 1440 80 R2 1059061760 0 0 0 0 0 0 0 O339 A2 0 0 1440 80 1 O333 0 0 0 2 A4 r RC AE r RC 0 0 1440 80 R2 1059061760 0 0 0 0 752 0 0 0 0 1440 832 R855 "MIInnerRight10" 1031153506 0 1 0 31360 0 0 0 0 0 32800 832 R856 "MIInnerIntRow10" 1030701209 0 0 0 0 33888 0 1 AE r R857 "Row10" O33A A29 0 0 32800 3104 170 0 0 32800 3104 5 2 AE r R6C0 A4 r R6C0 O28B 7064 2848 O45 7064 2848 O45 12664 2848 O107 12664 2848 O223 7064 0 3 2 AE r R858 "IOR'" A4 r R858 O33B A9 7576 24 A6 AA 0 25224 3044 O45 25224 3040 O136 25224 3044 5 2 AE r R314 A4 r R314 O284 9384 1248 O45 9384 1248 O45 18184 1248 OFD 18184 0 O121 9384 1248 7 2 AE r RA1 A4 r RA1 O33C A9 15792 32 A6 AA 0 11944 224 O45 26424 224 O45 11944 224 O45 27704 224 O223 27704 224 O223 26424 224 O107 11944 0 5 2 AE r R3F5 A4 r R3F5 O1BC 10344 2080 O45 10344 2080 O45 14184 2080 OF6 14184 2080 O133 10344 0 5 2 AE r R5DB A4 r R5DB O120 12584 288 O45 12584 288 O45 15224 288 O1CF 15224 288 O10A 12584 0 5 2 AE r R859 "/0(MiChip)/3(AddrMux)*1.[19][0]" A4 r R859 O139 5224 736 O45 5224 736 O45 5864 736 O109 5864 736 O130 5224 0 5 2 AE r R85A "PDTPout" A4 r R85A O1BC 9784 1888 O45 9784 1888 O45 13624 1888 O127 13624 1888 O12F 9784 0 5 2 AE r R85B "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21).[2]" A4 r R85B O184 10264 160 O45 10264 160 O45 10424 160 O10E 10424 0 O215 10264 160 5 2 AE r R4E4 A4 r R4E4 O263 19464 416 O45 19464 416 O45 21784 416 O10C 21784 0 O1D7 19464 416 5 2 AE r RA5 A4 r RA5 O157 6024 2720 O45 6024 2720 O45 7864 2720 O1D5 7864 0 OF4 6024 2720 5 2 AE r R5DD A4 r R5DD OFF 26744 672 O45 26744 672 O45 28744 672 O11D 28744 0 O112 26744 672 5 2 AE r R789 A4 r R789 O11F 9304 1120 O45 9304 1120 O45 10664 1120 O11E 10664 1120 O105 9304 0 5 2 AE r R788 A4 r R788 O2F1 17144 2208 O45 17144 2208 O45 19864 2208 O11B 19864 0 O159 17144 2208 5 2 AE r R4E9 A4 r R4E9 O321 11384 2208 O45 11384 2208 O45 16424 2208 O159 16424 2208 O11B 11384 0 5 2 AE r R31D A4 r R31D O184 25064 544 O45 25064 544 O45 25224 544 O102 25224 0 O116 25064 544 11 2 AE r R6C2 A4 r R6C2 O2C6 22104 2144 O45 22984 2144 O45 26984 2144 O45 22104 2144 O45 23384 2144 O45 27304 2144 OEB 27304 2144 O13E 22984 0 O13E 23384 0 OEB 26984 2144 O13E 22104 0 3 2 AE r R85C "/0(MiChip)/6(AddrCtl)*1.[6]" A4 r R85C OFB 23944 32 O21E 24024 32 OEE 23944 0 5 2 AE r R85D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2).[2]" A4 r R85D O184 27864 32 O45 27864 32 O45 28024 32 OEE 28024 0 O21E 27864 32 15 2 AE r R85E "/0(MiChip)/5(DataMux)/10(DataLatchMux)*1.[4]" A4 r R85E O33D A9 15072 32 A6 AA 0 8184 1056 O45 9944 1056 O45 21224 1056 O45 22584 1056 O45 8184 1056 O45 21304 1056 O45 10424 1056 O45 23224 1056 O13A 23224 1056 OF1 9944 0 O13A 10424 1056 OF1 21224 0 O13A 21304 1056 OF1 22584 0 OF1 8184 0 5 2 AE r R4F0 A4 r R4F0 O33E A9 15472 32 A6 AA 0 14184 2016 O45 14184 2016 O45 29624 2016 OF1 29624 2016 O13A 14184 0 5 2 AE r R791 A4 r R791 O10B 12424 1120 O45 12424 1120 O45 14104 1120 O11E 14104 1120 O105 12424 0 3 2 AE r R85F "/0(MiChip)/4(RefreshCtr)*1.[5]" A4 r R85F OFB 6264 32 OEE 6344 0 OEE 6264 0 5 2 AE r R792 A4 r R792 O27F 2584 288 O45 2584 288 O45 10504 288 O10A 10504 0 O10A 2584 0 5 2 AE r R860 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2).[1]" A4 r R860 O103 26504 608 O45 26504 608 O45 27064 608 O119 27064 0 O10D 26504 608 5 2 AE r R861 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2).[6]" A4 r R861 O284 10664 160 O45 10664 160 O45 19464 160 O10E 19464 0 O10E 10664 0 5 2 AE r R862 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21).[2]" A4 r R862 O22A 21544 2592 O45 21544 2592 O45 24504 2592 O10F 24504 0 O13D 21544 2592 5 2 AE r R3FE A4 r R3FE O328 13064 608 O45 13064 608 O45 16584 608 O10D 16584 608 O119 13064 0 5 2 AE r RC0 A4 r RC0 O303 5224 800 O45 5224 800 O45 16344 800 O22 16344 0 OF3 5224 800 5 2 AE r R863 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2).[6]" A4 r R863 O11C 28024 224 O45 28024 224 O45 29144 224 O107 29144 0 O223 28024 224 3 2 AE r R864 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[14]" A4 r R864 OFB 9144 32 OEE 9224 0 O21E 9144 32 5 2 AE r R865 "/0(MiChip)/6(AddrCtl)*1.[25]" A4 r R865 O14B 22904 3040 O45 22904 3040 O45 23864 3040 OEE 23864 3040 O21E 22904 0 3 2 AE r R866 "PDout34" A4 r R866 OFB 12264 1696 OFE 12344 1696 OEC 12264 0 7 2 AE r RC2 A4 r RC2 O2EA 8584 2720 O45 13144 2720 O45 8584 2720 O45 17784 2720 OF4 17784 2720 O1D5 13144 0 OF4 8584 2720 5 2 AE r R795 A4 r R795 O2B4 24584 416 O45 24584 416 O45 28664 416 O1D7 28664 416 O10C 24584 0 5 2 AE r R796 A4 r R796 O322 26664 2784 O45 26664 2784 O45 30424 2784 O1CF 30424 0 O10A 26664 2784 5 2 AE r R867 "/0(MiChip)/5(DataMux)/3(TstBuffer)*1.nInput[3]" A4 r R867 O10B 27224 2528 O45 27224 2528 O45 28904 2528 O116 28904 0 O102 27224 2528 10 2 AE r R5E5 A4 r R5E5 O33F A9 1216 32 A6 AA 0 14664 1888 O45 14664 1888 O45 15848 1888 O340 A9 32 224 A6 AB 0 15848 1696 O127 14664 1888 O341 A9 3168 32 A6 AA 0 15848 1696 O45 15848 1696 O45 18984 1696 OEC 18984 0 O340 15848 1696 5 2 AE r R798 A4 r R798 O111 19624 160 O45 19624 160 O45 20904 160 O215 20904 160 O10E 19624 0 5 2 AE r R262 A4 r R262 O15C 11464 2400 O45 11464 2400 O45 11704 2400 O11D 11704 2400 O112 11464 0 7 2 AE r R868 "/0(MiChip)/5(DataMux)*1.[39][0]" A4 r R868 O32D 3544 480 O45 4104 480 O45 3544 480 O45 8264 480 O13D 8264 0 O10F 4104 480 O13D 3544 0 5 2 AE r RCF A4 r RCF O2C4 12824 32 O45 12824 32 O45 20024 32 O21E 20024 32 OEE 12824 0 5 2 AE r R325 A4 r R325 O111 13784 2400 O45 13784 2400 O45 15064 2400 O112 15064 0 O11D 13784 2400 5 2 AE r R869 "/0(MiChip)/5(DataMux)/3(TstBuffer)*1.nInput[4]" A4 r R869 O342 A9 6672 32 A6 AA 0 15384 288 O45 15384 288 O45 22024 288 O10A 22024 0 O1CF 15384 288 5 2 AE r R86A "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2).[6]" A4 r R86A O343 A9 5952 32 A6 AA 0 20824 352 O45 20824 352 O45 26744 352 OF4 26744 0 OF4 20824 0 5 2 AE r R4FE A4 r R4FE O319 3464 416 O45 3464 416 O45 13784 416 O10C 13784 0 O10C 3464 0 5 2 AE r R406 A4 r R406 O143 10024 2208 O45 10024 2208 O45 11224 2208 O11B 11224 0 O159 10024 2208 5 2 AE r R86B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2).[6]" A4 r R86B OF2 24264 3040 O45 24264 3040 O45 24744 3040 O21E 24744 0 OEE 24264 3040 7 2 AE r RD5 A4 r RD5 O344 A9 26112 32 A6 AA 0 4504 2912 O45 29384 2912 O45 4504 2912 O45 30584 2912 O215 30584 0 O10E 29384 2912 O215 4504 0 7 2 AE r R5E7 A4 r R5E7 O1C1 10104 2976 O45 19224 2976 O45 10104 2976 O45 30824 2976 O206 30824 0 OFA 19224 2976 OFA 10104 2976 5 2 AE r R86C "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[5]" A4 r R86C O15C 14744 544 O45 14744 544 O45 14984 544 O102 14984 0 O102 14744 0 5 2 AE r R79B A4 r R79B O14B 5464 2848 O45 5464 2848 O45 6424 2848 O107 6424 2848 O223 5464 0 5 2 AE r R500 A4 r R500 O157 17944 864 O45 17944 864 O45 19784 864 O159 19784 0 O11B 17944 864 5 2 AE r R266 A4 r R266 O30A 21464 2848 O45 21464 2848 O45 23544 2848 O223 23544 0 O107 21464 2848 5 2 AE r R409 A4 r R409 O14B 10184 1312 O45 10184 1312 O45 11144 1312 O114 11144 0 O14D 10184 1312 5 2 AE r R501 A4 r R501 O11C 7624 736 O45 7624 736 O45 8744 736 O109 8744 736 O130 7624 0 11 2 AE r R6CB A4 r R6CB O2C6 22184 736 O45 23064 736 O45 27064 736 O45 22184 736 O45 23464 736 O45 27384 736 O109 27384 736 O130 23064 0 O130 23464 0 O109 27064 736 O130 22184 0 3 2 AE r R79D A4 r R79D OFB 21704 480 O10F 21784 480 O13D 21704 0 5 2 AE r R40C A4 r R40C O32C 20664 2208 O45 20664 2208 O45 27544 2208 O11B 27544 0 O159 20664 2208 5 2 AE r R79F A4 r R79F O161 4904 3040 O45 4904 3040 O45 6664 3040 O21E 6664 0 OEE 4904 3040 5 2 AE r R6CD A4 r R6CD O180 21944 2272 O45 21944 2272 O45 22344 2272 OF3 22344 0 O22 21944 2272 5 2 AE r RDB A4 r RDB O345 A9 8432 32 A6 AA 0 9224 736 O45 9224 736 O45 17624 736 O130 17624 0 O109 9224 736 5 2 AE r R6CE A4 r R6CE O14A 6184 160 O45 6184 160 O45 10184 160 O10E 10184 0 O215 6184 160 12 2 AE r R328 A4 r R328 O11F 9944 2784 O45 10808 2784 O45 9944 2784 O45 11304 2784 O10A 11304 2784 O346 A9 32 2784 A6 AB 0 10808 32 O10A 9944 2784 O347 A9 576 32 A6 AA 0 10264 32 O45 10264 32 O45 10808 32 O346 10808 32 OEE 10264 0 5 2 AE r R504 A4 r R504 O118 16504 2208 O45 16504 2208 O45 16824 2208 O11B 16824 0 O159 16504 2208 7 2 AE r R5EA A4 r R5EA O345 14984 2784 O45 19064 2784 O45 14984 2784 O45 23384 2784 O10A 23384 2784 O1CF 19064 0 O10A 14984 2784 5 2 AE r R86D "/0(MiChip)/5(DataMux)*1.[39][5]" A4 r R86D O2B0 14024 2272 O45 14024 2272 O45 21864 2272 O22 21864 2272 OF3 14024 0 11 2 AE r R6CF A4 r R6CF O31E 10984 928 O45 12504 928 O45 14824 928 O45 10984 928 O45 13384 928 O45 18664 928 O13E 18664 928 OEB 12504 0 O13E 13384 928 O13E 14824 928 O13E 10984 928 5 2 AE r R5EC A4 r R5EC O348 A9 8352 32 A6 AA 0 2424 224 O45 2424 224 O45 10744 224 O223 10744 224 O107 2424 0 5 2 AE r R86E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[9]" A4 r R86E O184 19224 416 O45 19224 416 O45 19384 416 O10C 19384 0 O10C 19224 0 5 2 AE r R1A3 A4 r R1A3 O2CA 4744 2976 O45 4744 2976 O45 8424 2976 O206 8424 0 O206 4744 0 7 2 AE r R86F "/0(MiChip)/5(DataMux)*1.[39][7]" A4 r R86F O263 21864 800 O45 23064 800 O45 21864 800 O45 24184 800 O22 24184 0 OF3 23064 800 O22 21864 0 3 2 AE r R7A2 A4 r R7A2 OFB 18504 1184 O127 18584 0 O12F 18504 1184 5 2 AE r R32A A4 r R32A O184 17064 1504 O45 17064 1504 O45 17224 1504 OF0 17224 1504 O100 17064 0 3 2 AE r R870 "/0(MiChip)/5(DataMux)/3(TstBuffer)*1.nInput[7]" A4 r R870 OFB 23224 32 OEE 23304 0 OEE 23224 0 5 2 AE r R50A A4 r R50A O349 A9 6192 32 A6 AA 0 24344 2848 O45 24344 2848 O45 30504 2848 O223 30504 0 O107 24344 2848 13 2 AE r RE0 A4 r RE0 O34A A9 14352 32 A6 AA 0 14664 1824 O45 19304 1824 O45 24104 1824 O45 14664 1824 O45 24424 1824 O45 20664 1824 O45 28984 1824 O121 28984 0 O121 19304 0 O121 20664 0 OFD 24104 1824 OFD 24424 1824 O121 14664 0 5 2 AE r R6D1 A4 r R6D1 O118 17464 1760 O45 17464 1760 O45 17784 1760 O14D 17784 0 O114 17464 1760 5 2 AE r R5F1 A4 r R5F1 O31B 18984 1760 O45 18984 1760 O45 24104 1760 O14D 24104 0 O114 18984 1760 7 2 AE r R1A5 A4 r R1A5 O33C 6984 3040 O45 22264 3040 O45 6984 3040 O45 22744 3040 O21E 22744 0 O21E 22264 0 O21E 6984 0 5 2 AE r R414 A4 r R414 O118 16984 1440 O45 16984 1440 O45 17304 1440 OF7 17304 1440 O128 16984 0 5 2 AE r R1A6 A4 r R1A6 O34B A9 17392 32 A6 AA 0 10104 96 O45 10104 96 O45 27464 96 O206 27464 96 OFA 10104 0 5 2 AE r R26A A4 r R26A O12E 18824 544 O45 18824 544 O45 19544 544 O102 19544 0 O116 18824 544 5 2 AE r R50E A4 r R50E O2D2 7784 928 O45 7784 928 O45 10584 928 O13E 10584 928 OEB 7784 0 5 2 AE r R5F4 A4 r R5F4 O349 13544 2144 O45 13544 2144 O45 19704 2144 O13E 19704 0 OEB 13544 2144 7 2 AE r R1A9 A4 r R1A9 O34C A9 10832 32 A6 AA 0 6904 1632 O45 16984 1632 O45 6904 1632 O45 17704 1632 O128 17704 1632 O128 16984 1632 OF7 6904 0 5 2 AE r R1AA A4 r R1AA O18E 18504 1120 O45 18504 1120 O45 19944 1120 O105 19944 0 O105 18504 0 5 2 AE r R1AB A4 r R1AB O34D A9 12512 32 A6 AA 0 17864 2720 O45 17864 2720 O45 30344 2720 O1D5 30344 0 OF4 17864 2720 5 2 AE r R871 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[2]" A4 r R871 O103 18024 1760 O45 18024 1760 O45 18584 1760 O114 18584 1760 O14D 18024 0 5 2 AE r R7A4 A4 r R7A4 O342 5944 608 O45 5944 608 O45 12584 608 O10D 12584 608 O119 5944 0 3 2 AE r R872 "/0(MiChip)*1.RefDone" A4 r R872 O135 20104 36 O136 20104 0 O300 20104 36 5 2 AE r R873 "/0(MiChip)/2(MemCtlA)*1.[23]" A4 r R873 O322 14504 1312 O45 14504 1312 O45 18264 1312 O114 18264 0 O114 14504 0 5 2 AE r R874 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[11]" A4 r R874 O34E A9 4432 32 A6 AA 0 4344 32 O45 4344 32 O45 8744 32 OEE 8744 0 OEE 4344 0 5 2 AE r R41A A4 r R41A O140 11784 32 O45 11784 32 O45 12664 32 OEE 12664 0 O21E 11784 32 5 2 AE r R1AE A4 r R1AE O349 21144 2080 O45 21144 2080 O45 27304 2080 O133 27304 0 OF6 21144 2080 5 2 AE r R875 "/0(MiChip)/4(RefreshCtr)*1.[1][3]" A4 r R875 O2A9 24664 2592 O45 24664 2592 O45 29144 2592 O13D 29144 2592 O10F 24664 0 5 2 AE r R1B1 A4 r R1B1 O2A3 17864 736 O45 17864 736 O45 18904 736 O109 18904 736 O130 17864 0 5 2 AE r R876 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[12]" A4 r R876 O34F A9 16832 32 A6 AA 0 3384 352 O45 3384 352 O45 20184 352 OF4 20184 0 OF4 3384 0 5 2 AE r R877 "/0(MiChip)/4(RefreshCtr)*1.[1][4]" A4 r R877 OF2 26184 288 O45 26184 288 O45 26664 288 O10A 26664 0 O1CF 26184 288 5 2 AE r R33C A4 r R33C O294 1624 160 O45 1624 160 O45 5784 160 O215 5784 160 O10E 1624 0 5 2 AE r R878 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21).[2]" A4 r R878 O12E 12984 2400 O45 12984 2400 O45 13704 2400 O11D 13704 2400 O112 12984 0 5 2 AE r R7A9 A4 r R7A9 O11F 11064 1824 O45 11064 1824 O45 12424 1824 OFD 12424 1824 O121 11064 0 5 2 AE r R41D A4 r R41D O321 14104 416 O45 14104 416 O45 19144 416 O1D7 19144 416 O10C 14104 0 5 2 AE r R513 A4 r R513 O143 14424 2848 O45 14424 2848 O45 15624 2848 O107 15624 2848 O223 14424 0 5 2 AE r R7AA A4 r R7AA O30A 15304 1760 O45 15304 1760 O45 17384 1760 O114 17384 1760 O14D 15304 0 9 2 AE r R879 "/0(MiChip)/6(AddrCtl)*1.RdRq" A4 r R879 O22F 20744 32 O45 20904 32 O45 20744 32 O45 23704 32 O45 25304 32 OEE 25304 0 OEE 20904 0 O21E 23704 32 O21E 20744 32 7 2 AE r R341 A4 r R341 O15B 5384 2784 O45 7224 2784 O45 5384 2784 O45 7864 2784 O10A 7864 2784 O10A 7224 2784 O1CF 5384 0 5 2 AE r R87A "/0(MiChip)/4(RefreshCtr)*1.[1][8]" A4 r R87A O103 27944 96 O45 27944 96 O45 28504 96 OFA 28504 0 O206 27944 96 5 2 AE r R515 A4 r R515 O2C1 11544 2784 O45 11544 2784 O45 14744 2784 O10A 14744 2784 O1CF 11544 0 5 2 AE r R41F A4 r R41F O321 14264 2080 O45 14264 2080 O45 19304 2080 OF6 19304 2080 O133 14264 0 5 2 AE r R6DB A4 r R6DB O12E 13224 2848 O45 13224 2848 O45 13944 2848 O223 13944 0 O107 13224 2848 5 2 AE r R7AD A4 r R7AD O180 26104 32 O45 26104 32 O45 26504 32 OEE 26504 0 O21E 26104 32 5 2 AE r R423 A4 r R423 O118 27224 2272 O45 27224 2272 O45 27544 2272 O22 27544 2272 OF3 27224 0 5 2 AE r R87B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/13(counterUpCtrl2).[4]" A4 r R87B O184 6264 2592 O45 6264 2592 O45 6424 2592 O10F 6424 0 O13D 6264 2592 13 2 AE r R87C "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv).nEnable" A4 r R87C O350 A9 13312 32 A6 AA 0 10024 672 O45 10504 672 O45 21384 672 O45 10024 672 O45 22664 672 O45 21304 672 O45 23304 672 O112 23304 672 O112 10504 672 O11D 21304 0 O112 21384 672 O11D 22664 0 O11D 10024 0 11 2 AE r REE A4 r REE O351 A9 23232 32 A6 AA 0 6024 2656 O45 7544 2656 O45 20184 2656 O45 6024 2656 O45 7784 2656 O45 29224 2656 O10C 29224 2656 O10C 7544 2656 O10C 7784 2656 O10C 20184 2656 O1D7 6024 0 15 2 AE r R1B4 A4 r R1B4 O352 A9 20672 32 A6 AA 0 1704 2528 O45 2584 2528 O45 4184 2528 O45 6504 2528 O45 1704 2528 O45 6104 2528 O45 3384 2528 O45 22344 2528 O102 22344 2528 O102 2584 2528 O102 3384 2528 O102 4184 2528 O102 6104 2528 O102 6504 2528 O116 1704 0 5 2 AE r R519 A4 r R519 O2C1 15464 544 O45 15464 544 O45 18664 544 O102 18664 0 O102 15464 0 5 2 AE r R7B2 A4 r R7B2 O140 26264 544 O45 26264 544 O45 27144 544 O102 27144 0 O116 26264 544 5 2 AE r R7B3 A4 r R7B3 O2D2 12344 1568 O45 12344 1568 O45 15144 1568 O100 15144 1568 OF0 12344 0 5 2 AE r R87D "/0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)*1.[5]" A4 r R87D O131 9864 2144 O45 9864 2144 O45 13304 2144 O13E 13304 0 OEB 9864 2144 5 2 AE r R87E "/0(MiChip)/1(ClockGen)/3(ffR)*1.[4]" A4 r R87E O12A 23784 288 O45 23784 288 O45 25704 288 O10A 25704 0 O10A 23784 0 11 2 AE r RB A4 r RB O282 15304 2464 O45 21704 2464 O45 26824 2464 O45 15304 2464 O45 23144 2464 O45 28824 2464 O10D 28824 0 O119 21704 2464 O10D 23144 0 O119 26824 2464 O119 15304 2464 5 2 AE r R87F "/0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)*1.[3]" A4 r R87F O18E 15944 1568 O45 15944 1568 O45 17384 1568 OF0 17384 0 O100 15944 1568 5 2 AE r R604 A4 r R604 O120 16904 608 O45 16904 608 O45 19544 608 O10D 19544 608 O119 16904 0 9 2 AE r R880 "/0(MiChip)*1.RefRq" A4 r R880 O2CB 16184 1888 O45 16424 1888 O45 16184 1888 O45 18344 1888 O45 18744 1888 O12F 18744 0 O12F 16424 0 O12F 18344 0 O12F 16184 0 5 2 AE r R881 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[9]" A4 r R881 O27F 7144 2464 O45 7144 2464 O45 15064 2464 O119 15064 2464 O10D 7144 0 7 2 AE r R882 "/0(MiChip)*1.[21]" A4 r R882 O2C7 15704 2848 O45 20824 2848 O45 15704 2848 O45 20984 2848 O223 20984 0 O107 20824 2848 O107 15704 2848 3 2 AE r R883 "PDin8" A4 r R883 O353 A9 2856 24 A6 AA 0 0 100 O45 2824 96 O354 A9 32 3004 A6 AB 0 2824 100 3 2 AE r R6E2 A4 r R6E2 OFB 5864 672 O112 5944 672 O11D 5864 0 5 2 AE r R7B8 A4 r R7B8 O14A 7624 2336 O45 7624 2336 O45 11624 2336 O109 11624 0 O130 7624 2336 11 2 AE r R6E5 A4 r R6E5 O31E 11064 1952 O45 11704 1952 O45 14904 1952 O45 11064 1952 O45 13464 1952 O45 18744 1952 O105 18744 1952 O11E 11704 0 O105 13464 1952 O105 14904 1952 O105 11064 1952 7 2 AE r R884 "/0(MiChip)/4(RefreshCtr)/1(ffRP)*1.[3]" A4 r R884 O22F 16504 800 O45 16664 800 O45 16504 800 O45 21064 800 OF3 21064 800 O22 16664 0 O22 16504 0 5 2 AE r R42B A4 r R42B O355 A9 19152 32 A6 AA 0 8504 480 O45 8504 480 O45 27624 480 O13D 27624 0 O10F 8504 480 5 2 AE r R885 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21).[2]" A4 r R885 O129 14344 1120 O45 14344 1120 O45 17704 1120 O105 17704 0 O105 14344 0 9 2 AE r R103 A4 r R103 O1D4 15544 2400 O45 25464 2400 O45 15544 2400 O45 27784 2400 O45 28424 2400 O11D 28424 2400 O11D 25464 2400 O112 27784 0 O112 15544 0 5 2 AE r R886 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[13]" A4 r R886 O12E 13624 1824 O45 13624 1824 O45 14344 1824 OFD 14344 1824 O121 13624 0 5 2 AE r R887 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)*1.nInput[1]" A4 r R887 O328 10344 2272 O45 10344 2272 O45 13864 2272 OF3 13864 0 O22 10344 2272 5 2 AE r R7BE A4 r R7BE O15C 25144 2528 O45 25144 2528 O45 25384 2528 O102 25384 2528 O116 25144 0 5 2 AE r R107 A4 r R107 O18E 28664 96 O45 28664 96 O45 30104 96 O206 30104 96 OFA 28664 0 5 2 AE r R6E7 A4 r R6E7 O180 5304 2720 O45 5304 2720 O45 5704 2720 OF4 5704 2720 O1D5 5304 0 5 2 AE r R888 "/0(MiChip)/4(RefreshCtr)/1(ffRP)*1.[4]" A4 r R888 O14B 15784 1440 O45 15784 1440 O45 16744 1440 O128 16744 0 O128 15784 0 5 2 AE r R889 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2).[1]" A4 r R889 O15C 12024 1760 O45 12024 1760 O45 12264 1760 O114 12264 1760 O14D 12024 0 5 2 AE r R88A "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)*1.nInput[3]" A4 r R88A O305 6584 672 O45 6584 672 O45 9864 672 O11D 9864 0 O11D 6584 0 5 2 AE r R7C0 A4 r R7C0 OFF 15464 1376 O45 15464 1376 O45 17464 1376 OFE 17464 0 OEC 15464 1376 5 2 AE r R60C A4 r R60C O180 7304 2592 O45 7304 2592 O45 7704 2592 O10F 7704 0 O13D 7304 2592 3 2 AE r R88B "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)*1.nInput[4]" A4 r R88B OFB 22424 32 OEE 22504 0 OEE 22424 0 5 2 AE r R524 A4 r R524 O18E 25144 2784 O45 25144 2784 O45 26584 2784 O1CF 26584 0 O10A 25144 2784 3 2 AE r R88C "/0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)*1.[3]" A4 r R88C OFB 2904 32 OEE 2984 0 OEE 2904 0 5 2 AE r R88D "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2).[2]" A4 r R88D O180 12104 2400 O45 12104 2400 O45 12504 2400 O11D 12504 2400 O112 12104 0 3 2 AE r R88E "PDin13" A4 r R88E O356 A9 4456 24 A6 AA 0 0 3044 O45 4424 3040 O136 4424 3044 3 2 AE r R88F "/0(MiChip)/1(ClockGen)*1.[10]" A4 r R88F O32F 29864 32 OEE 30024 0 OEE 29864 0 5 2 AE r R356 A4 r R356 O34D 8024 2592 O45 8024 2592 O45 20504 2592 O13D 20504 2592 O10F 8024 0 7 2 AE r R6EC A4 r R6EC O357 A9 13232 32 A6 AA 0 7944 992 O45 20424 992 O45 7944 992 O45 21144 992 OF6 21144 0 O133 20424 992 OF6 7944 0 5 2 AE r R890 "/0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)*1.[5]" A4 r R890 O180 9064 32 O45 9064 32 O45 9464 32 OEE 9464 0 OEE 9064 0 7 2 AE r R10A A4 r R10A O33C 11864 2336 O45 26344 2336 O45 11864 2336 O45 27624 2336 O130 27624 2336 O130 26344 2336 O109 11864 0 5 2 AE r R891 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)*1.nInput[7]" A4 r R891 O12E 21224 2144 O45 21224 2144 O45 21944 2144 O13E 21944 0 OEB 21224 2144 5 2 AE r R7C3 A4 r R7C3 O18C 23864 2784 O45 23864 2784 O45 24664 2784 O10A 24664 2784 O1CF 23864 0 5 2 AE r R10D A4 r R10D O30D 4984 544 O45 4984 544 O45 14584 544 O102 14584 0 O116 4984 544 5 2 AE r R7C6 A4 r R7C6 O12E 28584 32 O45 28584 32 O45 29304 32 O21E 29304 32 OEE 28584 0 3 2 AE r R892 "PDin24" A4 r R892 O358 A9 3656 24 A6 AA 0 0 36 O45 3624 32 O300 3624 36 5 2 AE r R112 A4 r R112 O209 9304 1184 O45 9304 1184 O45 17544 1184 O127 17544 0 O12F 9304 1184 3 2 AE r R1CC A4 r R1CC OFB 18024 3040 O21E 18104 0 OEE 18024 3040 5 2 AE r R1CE A4 r R1CE O19A 8264 2016 O45 8264 2016 O45 13704 2016 O13A 13704 0 OF1 8264 2016 7 2 AE r R52F A4 r R52F O2E9 3304 96 O45 4424 96 O45 3304 96 O45 9544 96 O206 9544 96 OFA 4424 0 O206 3304 96 5 2 AE r R6F0 A4 r R6F0 O197 15144 1504 O45 15144 1504 O45 16744 1504 OF0 16744 1504 O100 15144 0 7 2 AE r R1D1 A4 r R1D1 O34C 6824 864 O45 16904 864 O45 6824 864 O45 17624 864 O11B 17624 864 O11B 16904 864 O159 6824 0 3 2 AE r R893 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[2]" A4 r R893 OFB 27384 32 OEE 27464 0 OEE 27384 0 5 2 AE r R894 "/0(MiChip)/1(ClockGen)*1.[15]" A4 r R894 O179 21384 160 O45 21384 160 O45 30264 160 O10E 30264 0 O10E 21384 0 5 2 AE r R6F1 A4 r R6F1 O157 9464 2400 O45 9464 2400 O45 11304 2400 O112 11304 0 O11D 9464 2400 0 0 34720 0 1 AE r R895 "MIInnerChan11" O359 A2 0 0 32800 856 109 O35A A2 0 0 2560 832 2 O35B A2 0 0 2560 80 1 O35C A9 2560 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 2560 80 R2 1059061760 0 0 0 0 0 0 0 O35D A2 0 0 2560 80 1 O35C 0 0 0 2 A4 r RC AE r RC 0 0 2560 80 R2 1059061760 0 0 0 0 752 0 0 0 0 2560 832 R896 "MIInnerLeft11" 1031153506 0 1 0 0 0 0 0 O24 2560 0 0 2 AE r R897 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 3360 0 0 2 AE r R898 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 4160 0 0 2 AE r R899 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 4960 0 0 2 AE r R89A "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 5744 0 0 2 AE r R89B "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)*1.[4]-11" A1A a A1A O18 5824 0 0 2 AE r R89C "/0(MiChip)/3(AddrMux)*1.[19][0]-11" A1A a A1A O18 5904 0 0 2 AE r R89D "/0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)*1.[4]-11" A1A a A1A OCA 6000 0 0 2 AE r R89E "/0(MiChip)/5(DataMux)/13(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O86 6240 0 0 2 AE r R89F "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/13(counterUpCtrl2)/3(Inv)*1" A1A a A1A O18 6384 0 0 2 AE r R8A0 "/0(MiChip)/5(DataMux)*1.[39][2]-11" A1A a A1A O24 6480 0 0 2 AE r R8A1 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 7264 0 0 2 AE r R8A2 "/0(MiChip)/7(StatusReg)*1.[14][2]-11" A1A a A1A O16D 7360 0 0 2 AE r R8A3 "/0(MiChip)/1(ClockGen)/2(B)//0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer0" A1A a A1A O16D 7600 0 0 2 AE r R8A4 "/0(MiChip)/1(ClockGen)/2(B)//0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer1" A1A a A1A O86 7840 0 0 2 AE r R8A5 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv7" A1A a A1A OCE 8000 0 0 2 AE r R8A6 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver7" A1A a A1A OCE 8320 0 0 2 AE r R8A7 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver1" A1A a A1A ODD 8640 0 0 2 AE r R8A8 "/0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 9120 0 0 2 AE r R8A9 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver14" A1A a A1A ODD 9440 0 0 2 AE r R8AA "/0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OA4 9920 0 0 2 AE r R8AB "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 10320 0 0 2 AE r R8AC "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver1" A1A a A1A O18 10624 0 0 2 AE r R8AD "/0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)*1.[7]-11" A1A a A1A O86 10720 0 0 2 AE r R8AE "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv7" A1A a A1A OCE 10880 0 0 2 AE r R8AF "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver7" A1A a A1A ODD 11200 0 0 2 AE r R8B0 "/0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 11664 0 0 2 AE r R8B1 "PDout35-11" A1A a A1A O18 11744 0 0 2 AE r R8B2 "/0(MiChip)/5(DataMux)*1.[15][1]-11" A1A a A1A OB6 11840 0 0 2 AE r R8B3 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 12304 0 0 2 AE r R8B4 "PDout34-11" A1A a A1A O18 12384 0 0 2 AE r R8B5 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[5]-11" A1A a A1A O18 12464 0 0 2 AE r R8B6 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2).[2]-11" A1A a A1A O18 12544 0 0 2 AE r R8B7 "PDTPin-11" A1A a A1A O18 12624 0 0 2 AE r R8B8 "PDin35-11" A1A a A1A ODD 12720 0 0 2 AE r R8B9 "/0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 13184 0 0 2 AE r R8BA "/0(MiChip)/2(MemCtlA)*1.Accept-11" A1A a A1A OCE 13280 0 0 2 AE r R8BB "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver0" A1A a A1A O18 13584 0 0 2 AE r R8BC "PDTPout-11" A1A a A1A O18 13664 0 0 2 AE r R8BD "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21).[2]-11" A1A a A1A O18 13744 0 0 2 AE r R8BE "/0(MiChip)/2(MemCtlA)*1.WrHCy-11" A1A a A1A O168 13840 0 0 2 AE r R8BF "/0(MiChip)/2(MemCtlA)/46(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 14144 0 0 2 AE r R8C0 "PDin36-11" A1A a A1A ODD 14240 0 0 2 AE r R8C1 "/0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 14720 0 0 2 AE r R8C2 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver6" A1A a A1A O18 15024 0 0 2 AE r R8C3 "/0(MiChip)/5(DataMux)/12(ParGen)*1.[9]-11" A1A a A1A O18 15104 0 0 2 AE r R8C4 "/0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)*1.[3]-11" A1A a A1A O18 15184 0 0 2 AE r R8C5 "PDin37-11" A1A a A1A O86 15280 0 0 2 AE r R8C6 "/0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv4" A1A a A1A O86 15440 0 0 2 AE r R8C7 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O168 15600 0 0 2 AE r R8C8 "/0(MiChip)/2(MemCtlA)/31(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A ODD 15920 0 0 2 AE r R8C9 "/0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 16384 0 0 2 AE r R8CA "/0(MiChip)*1.[4]-11" A1A a A1A O18 16464 0 0 2 AE r R8CB "PDout37-11" A1A a A1A O86 16560 0 0 2 AE r R8CC "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv2" A1A a A1A O18 16704 0 0 2 AE r R8CD "PDin32-11" A1A a A1A OCE 16800 0 0 2 AE r R8CE "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver2" A1A a A1A O18 17104 0 0 2 AE r R8CF "/0(MiChip)/2(MemCtlA)*1.Done-11" A1A a A1A O18 17184 0 0 2 AE r R8D0 "PDout38-11" A1A a A1A O18 17264 0 0 2 AE r R8D1 "PDout39-11" A1A a A1A O18 17344 0 0 2 AE r R8D2 "/0(MiChip)/2(MemCtlA)*1.[64]-11" A1A a A1A O18 17424 0 0 2 AE r R8D3 "PDout29-11" A1A a A1A OCE 17520 0 0 2 AE r R8D4 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver9" A1A a A1A O18 17824 0 0 2 AE r R8D5 "/0(MiChip)/2(MemCtlA)*1.C1-11" A1A a A1A O18 17904 0 0 2 AE r R8D6 "PDout36-11" A1A a A1A O18 17984 0 0 2 AE r R8D7 "RPadEnb-11" A1A a A1A ODD 18080 0 0 2 AE r R8D8 "/0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 18560 0 0 2 AE r R8D9 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver2" A1A a A1A O18 18864 0 0 2 AE r R8DA "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).Two-11" A1A a A1A O18 18944 0 0 2 AE r R8DB "Dout10-11" A1A a A1A OA4 19040 0 0 2 AE r R8DC "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/1(A22o2i)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 19424 0 0 2 AE r R8DD "PDin38-11" A1A a A1A O16D 19520 0 0 2 AE r R8DE "/0(MiChip)/2(MemCtlA)/16(B)//0(MiChip)/2(MemCtlA)/13(B)//0(MiChip)/1(ClockGen)/2(B)//0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer1" A1A a A1A O16D 19760 0 0 2 AE r R8DF "/0(MiChip)/2(MemCtlA)/16(B)//0(MiChip)/2(MemCtlA)/13(B)//0(MiChip)/1(ClockGen)/2(B)//0(MiChip)/1(ClockGen)/1(B)//0(MiChip)/1(ClockGen)/0(B)/Buffer0" A1A a A1A O18 19984 0 0 2 AE r R8E0 "Din6-11" A1A a A1A O171 20080 0 0 2 AE r R8E1 "/0(MiChip)/4(RefreshCtr)/2(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O168 20400 0 0 2 AE r R8E2 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/0(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A OCA 20720 0 0 2 AE r R8E3 "/0(MiChip)/6(AddrCtl)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O86 20960 0 0 2 AE r R8E4 "/0(MiChip)/4(RefreshCtr)/1(ffRP)/2(Inv)*1" A1A a A1A O18 21104 0 0 2 AE r R8E5 "/0(MiChip)/5(DataMux)*1.[15][2]-11" A1A a A1A OCE 21200 0 0 2 AE r R8E6 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver7" A1A a A1A O86 21520 0 0 2 AE r R8E7 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 21680 0 0 2 AE r R8E8 "/0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv5" A1A a A1A ODD 21840 0 0 2 AE r R8E9 "/0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 22320 0 0 2 AE r R8EA "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 23120 0 0 2 AE r R8EB "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver6" A1A a A1A O168 23440 0 0 2 AE r R8EC "/0(MiChip)/6(AddrCtl)/2(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O168 23760 0 0 2 AE r R8ED "/0(MiChip)/6(AddrCtl)/8(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A OCA 24080 0 0 2 AE r R8EE "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 24304 0 0 2 AE r R8EF "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11).Two-11" A1A a A1A OCA 24400 0 0 2 AE r R8F0 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)/3(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O86 24640 0 0 2 AE r R8F1 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/2/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/3/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/4/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/5/6//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/0/2/0(Inv)*1*1*1*1*1*1" A1A a A1A O168 24800 0 0 2 AE r R8F2 "/0(MiChip)/6(AddrCtl)/13(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O18 25104 0 0 2 AE r R8F3 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12).[10][1]-11" A1A a A1A O86 25200 0 0 2 AE r R8F4 "/0(MiChip)/6(AddrCtl)/9(Inv)*1" A1A a A1A O18 25344 0 0 2 AE r R8F5 "/0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)*1.[7]-11" A1A a A1A O24 25440 0 0 2 AE r R8F6 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1*1*1*1*1*1" A1A a A1A OA4 26240 0 0 2 AE r R8F7 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1*1*1*1*1*1" A1A a A1A O18 26624 0 0 2 AE r R8F8 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[15]-11" A1A a A1A O18 26704 0 0 2 AE r R8F9 "/0(MiChip)/3(AddrMux)*1.[19][1]-11" A1A a A1A O35E AD -16 0 128 856 O35F A2 -16 0 128 856 11 O1A 128 328 2 1 A10 r R23 O1C 32 768 0 1 A12 i 58463 O1B 32 48 0 1 A12 i 58461 O22 40 0 0 1 A10 r R23 O1D 16 792 0 1 A10 r R23 O1E 16 8 0 1 A10 r R23 O1F 40 8 0 1 A10 r R23 O20 40 792 0 1 A10 r R23 O1A7 40 80 0 0 O21 16 0 0 4 A10 r R23 A4 r RB A12 i 58461 A16 lor 1 RB O21 16 752 0 4 A10 r R23 A4 r RC A12 i 58463 A16 lor 1 RC 16 0 96 832 R8FA "C2GD00A.mask" 1048576000 0 1 2 A28 r R8FB "Gnd Vdd Gnd" A17 i 74736 1 A18 a A19 26784 0 0 2 AE r R8FC "gnd" A1A a A1A OCE 26880 0 0 2 AE r R8FD "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver0" A1A a A1A OCE 27200 0 0 2 AE r R8FE "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver3" A1A a A1A OA4 27520 0 0 2 AE r R8FF "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/1(A22o2i)*1*1*1*1" A1A a A1A OB6 27920 0 0 2 AE r R900 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/2(Xnor2)*1*1*1*1" A1A a A1A O24 28400 0 0 2 AE r R901 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1*1*1*1*1*1*1" A1A a A1A O86 29200 0 0 2 AE r R902 "/0(MiChip)/2(MemCtlA)/44(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/43(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 29360 0 0 2 AE r R903 "/0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1" A1A a A1A O360 A2 0 0 2640 832 2 O361 A2 0 0 2640 80 1 O362 A9 2640 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 2640 80 R2 1059061760 0 0 0 0 0 0 0 O363 A2 0 0 2640 80 1 O362 0 0 0 2 A4 r RC AE r RC 0 0 2640 80 R2 1059061760 0 0 0 0 752 0 0 0 0 2640 832 R904 "MIInnerRight11" 1031153506 0 1 0 30160 0 0 0 0 0 32800 832 R905 "MIInnerIntRow11" 1030701209 0 0 0 0 37824 0 1 AE r R906 "Row11" O364 A29 0 0 32800 2912 152 0 0 32800 2912 5 2 AE r R6C0 A4 r R6C0 O131 12664 1248 O45 12664 1248 O45 16104 1248 OF7 16104 1248 OFD 12664 0 5 2 AE r RA1 A4 r RA1 O365 A9 19712 32 A6 AA 0 6744 2272 O45 6744 2272 O45 26424 2272 OF3 26424 0 O119 6744 2272 5 2 AE r R3F5 A4 r R3F5 OFF 14184 288 O45 14184 288 O45 16184 288 O10F 16184 288 O10A 14184 0 5 2 AE r R907 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[2]" A4 r R907 O184 16664 1696 O45 16664 1696 O45 16824 1696 OEC 16824 0 OEC 16664 0 5 2 AE r R5DB A4 r R5DB O111 15224 1120 O45 15224 1120 O45 16504 1120 O14D 16504 1120 O105 15224 0 5 2 AE r R859 A4 r R859 O2A3 5864 160 O45 5864 160 O45 6904 160 O1D5 6904 160 O10E 5864 0 5 2 AE r R85A A4 r R85A O129 13624 608 O45 13624 608 O45 16984 608 OF3 16984 608 O119 13624 0 5 2 AE r RA5 A4 r RA5 O32D 6024 2336 O45 6024 2336 O45 10744 2336 O102 10744 2336 O109 6024 0 5 2 AE r R4E4 A4 r R4E4 O120 16824 1760 O45 16824 1760 O45 19464 1760 O14D 19464 0 O105 16824 1760 5 2 AE r R908 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5).One" A4 r R908 O2B4 17384 2848 O45 17384 2848 O45 21464 2848 OEE 21464 2848 OEE 17384 2848 3 2 AE r R909 "PDin39" A4 r R909 OFB 6744 32 O223 6824 32 OEE 6744 0 5 2 AE r R788 A4 r R788 O322 13384 864 O45 13384 864 O45 17144 864 O159 17144 0 O13A 13384 864 5 2 AE r R789 A4 r R789 O11F 9304 1952 O45 9304 1952 O45 10664 1952 O11E 10664 0 OEB 9304 1952 5 2 AE r R5DD A4 r R5DD OF5 26744 2784 O45 26744 2784 O45 28264 2784 OFA 28264 2784 O1CF 26744 0 9 2 AE r R90A "/0(MiChip)/2(MemCtlA)*1.WrCy" A4 r R90A O2C6 10664 2016 O45 13464 2016 O45 10664 2016 O45 13864 2016 O45 15864 2016 O13A 15864 0 O159 13464 2016 O13A 13864 0 O159 10664 2016 7 2 AE r R90B "/0(MiChip)/6(AddrCtl)*1.[21]" A4 r R90B O157 23464 672 O45 24904 672 O45 23464 672 O45 25304 672 O11D 25304 0 O11D 24904 0 O11D 23464 0 5 2 AE r R90C "PDout30" A4 r R90C O111 17544 2016 O45 17544 2016 O45 18824 2016 O159 18824 2016 O159 17544 2016 5 2 AE r R4E9 A4 r R4E9 O2D2 16424 1248 O45 16424 1248 O45 19224 1248 OF7 19224 1248 OFD 16424 0 3 2 AE r R90D "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[7]" A4 r R90D OFB 7944 32 OEE 8024 0 OEE 7944 0 5 2 AE r R90E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2).[6]" A4 r R90E O320 11944 1888 O45 11944 1888 O45 24584 1888 O12F 24584 0 O12F 11944 0 5 2 AE r R90F "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[6]" A4 r R90F O349 21784 2720 O45 21784 2720 O45 27944 2720 O10E 27944 2720 O10E 21784 2720 5 2 AE r R910 "PDout31" A4 r R910 O294 17464 2080 O45 17464 2080 O45 21624 2080 O133 21624 0 O22 17464 2080 5 2 AE r R911 "/0(MiChip)/5(DataMux)/3(TstBuffer)*1.nInput[0]" A4 r R911 O184 26744 2848 O45 26744 2848 O45 26904 2848 O223 26904 0 OEE 26744 2848 7 2 AE r R6C2 A4 r R6C2 O2C1 23784 2464 O45 26424 2464 O45 23784 2464 O45 26984 2464 O10D 26984 0 O10C 26424 2464 O10C 23784 2464 5 2 AE r R912 "/0(MiChip)/6(AddrCtl)/15(EqConstant)*1.[4]" A4 r R912 O197 15704 2464 O45 15704 2464 O45 17304 2464 O10C 17304 2464 O10C 15704 2464 5 2 AE r R913 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2).[1]" A4 r R913 O103 27784 224 O45 27784 224 O45 28344 224 O107 28344 0 O107 27784 0 5 2 AE r R914 "PDout32" A4 r R914 O18C 14744 1696 O45 14744 1696 O45 15544 1696 OEC 15544 0 O127 14744 1696 5 2 AE r R915 "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[5]" A4 r R915 O2EB 8984 480 O45 8984 480 O45 15784 480 O112 15784 480 O112 8984 480 9 2 AE r R85E A4 r R85E O2F4 9624 672 O45 14424 672 O45 9624 672 O45 21304 672 O45 22664 672 O11B 22664 672 O11B 14424 672 O11D 21304 0 O11B 9624 672 5 2 AE r R4F0 A4 r R4F0 O366 A9 23632 32 A6 AA 0 6024 2400 O45 6024 2400 O45 29624 2400 O112 29624 0 O13D 6024 2400 5 2 AE r R916 "/0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)*1.[3]" A4 r R916 O11C 11624 992 O45 11624 992 O45 12744 992 OF6 12744 0 OF6 11624 0 5 2 AE r R917 "PDout33" A4 r R917 O140 13784 2336 O45 13784 2336 O45 14664 2336 O102 14664 2336 O102 13784 2336 3 2 AE r R918 "/0(MiChip)/5(DataMux)/3(TstBuffer)*1.nInput[2]" A4 r R918 OFB 23624 2848 OEE 23704 2848 OEE 23624 2848 7 2 AE r R3FE A4 r R3FE O15A 16584 1952 O45 19384 1952 O45 16584 1952 O45 19464 1952 OEB 19464 1952 OEB 19384 1952 O11E 16584 0 5 2 AE r R919 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2).[2]" A4 r R919 O140 25704 224 O45 25704 224 O45 26584 224 O107 26584 0 O107 25704 0 5 2 AE r R91A "/0(MiChip)/7(StatusReg)/8(TstBuffer)*1.nInput[9]" A4 r R91A OF5 17544 864 O45 17544 864 O45 19064 864 O13A 19064 864 O159 17544 0 5 2 AE r R865 A4 r R865 O157 22024 928 O45 22024 928 O45 23864 928 OEB 23864 0 O11E 22024 928 5 2 AE r R866 A4 r R866 O103 12344 32 O45 12344 32 O45 12904 32 O223 12904 32 OEE 12344 0 5 2 AE r R796 A4 r R796 O14B 26664 224 O45 26664 224 O45 27624 224 O1D7 27624 224 O107 26664 0 5 2 AE r R91B "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[2]" A4 r R91B O139 24504 1824 O45 24504 1824 O45 25144 1824 OF1 25144 1824 O121 24504 0 5 2 AE r R91C "/0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)*1.[3]" A4 r R91C O139 13224 2080 O45 13224 2080 O45 13864 2080 O22 13864 2080 O22 13224 2080 5 2 AE r R91D "/0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)*1.[5]" A4 r R91D O322 9064 864 O45 9064 864 O45 12824 864 O159 12824 0 O159 9064 0 5 2 AE r R262 A4 r R262 O11C 11704 1952 O45 11704 1952 O45 12824 1952 OEB 12824 1952 O11E 11704 0 5 2 AE r R91E "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)*1.ncarry[3]" A4 r R91E O103 24184 928 O45 24184 928 O45 24744 928 OEB 24744 0 OEB 24184 0 5 2 AE r R868 A4 r R868 O2C7 4104 2784 O45 4104 2784 O45 9384 2784 OFA 9384 2784 O1CF 4104 0 5 2 AE r R325 A4 r R325 O2C1 10584 224 O45 10584 224 O45 13784 224 O107 13784 0 O1D7 10584 224 5 2 AE r RCF A4 r RCF O28B 20024 224 O45 20024 224 O45 25624 224 O1D7 25624 224 O107 20024 0 5 2 AE r R406 A4 r R406 O2C6 4824 96 O45 4824 96 O45 10024 96 OFA 10024 0 O1CF 4824 96 5 2 AE r R5E7 A4 r R5E7 O10B 19224 1056 O45 19224 1056 O45 20904 1056 O121 20904 1056 OF1 19224 0 5 2 AE r R79B A4 r R79B OF5 6424 224 O45 6424 224 O45 7944 224 O1D7 7944 224 O107 6424 0 5 2 AE r R500 A4 r R500 O2F1 15224 1376 O45 15224 1376 O45 17944 1376 OFE 17944 0 O100 15224 1376 5 2 AE r R266 A4 r R266 O319 11144 2720 O45 11144 2720 O45 21464 2720 O1D5 21464 0 O1D5 11144 0 5 2 AE r R409 A4 r R409 O2C7 4904 2720 O45 4904 2720 O45 10184 2720 O1D5 10184 0 O10E 4904 2720 7 2 AE r R6CB A4 r R6CB O2C1 23864 1952 O45 26504 1952 O45 23864 1952 O45 27064 1952 O11E 27064 0 OEB 26504 1952 OEB 23864 1952 5 2 AE r R91F "A12" A4 r R91F O367 A9 16616 24 A6 AA 0 0 2852 O45 15624 2848 O45 16584 2848 O136 16584 2852 O136 15624 2852 7 2 AE r R40C A4 r R40C O2CF 8104 1184 O45 8424 1184 O45 8104 1184 O45 20664 1184 O127 20664 0 O127 8424 0 O127 8104 0 5 2 AE r R79F A4 r R79F O322 4904 2656 O45 4904 2656 O45 8664 2656 O1D7 8664 0 O1D7 4904 0 9 2 AE r RDB A4 r RDB O368 A9 21392 32 A6 AA 0 7144 160 O45 9224 160 O45 7144 160 O45 27704 160 O45 28504 160 O1D5 28504 160 O10E 9224 0 O1D5 27704 160 O1D5 7144 160 5 2 AE r R920 "/0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)*1.[5]" A4 r R920 O11C 13944 2080 O45 13944 2080 O45 15064 2080 O22 15064 2080 O22 13944 2080 7 2 AE r R5EA A4 r R5EA O1BD 23384 416 O45 26584 416 O45 23384 416 O45 28184 416 O10D 28184 416 O10D 26584 416 O10C 23384 0 5 2 AE r R504 A4 r R504 O11F 15144 1056 O45 15144 1056 O45 16504 1056 OF1 16504 0 O121 15144 1056 7 2 AE r R86D A4 r R86D O369 A9 17632 32 A6 AA 0 4744 1568 O45 21864 1568 O45 4744 1568 O45 22344 1568 O114 22344 1568 OF0 21864 0 O114 4744 1568 3 2 AE r R921 "/0(MiChip)/5(DataMux)/3(TstBuffer)*1.nInput[6]" A4 r R921 OFB 26264 2848 OEE 26344 2848 OEE 26264 2848 7 2 AE r R6CF A4 r R6CF O1D3 12584 1632 O45 18664 1632 O45 12584 1632 O45 21864 1632 OFD 21864 1632 OF7 18664 0 OFD 12584 1632 5 2 AE r R5EC A4 r R5EC OF2 10744 288 O45 10744 288 O45 11224 288 O10A 11224 0 O10A 10744 0 5 2 AE r R922 "CE'" A4 r R922 O103 16664 2848 O45 16664 2848 O45 17224 2848 OEE 17224 2848 OEE 16664 2848 9 2 AE r R923 "/0(MiChip)/5(DataMux)*1.[39][6]" A4 r R923 O36A A9 8512 32 A6 AA 0 19064 608 O45 22984 608 O45 19064 608 O45 23384 608 O45 27544 608 OF3 27544 608 OF3 22984 608 OF3 23384 608 O119 19064 0 5 2 AE r R86F A4 r R86F O184 22904 2464 O45 22904 2464 O45 23064 2464 O10D 23064 0 O10C 22904 2464 5 2 AE r R32A A4 r R32A O140 16344 2080 O45 16344 2080 O45 17224 2080 O133 17224 0 O22 16344 2080 5 2 AE r R924 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[0]" A4 r R924 O12A 11384 288 O45 11384 288 O45 13304 288 O10A 13304 0 O10F 11384 288 3 2 AE r R50A A4 r R50A O135 24344 2852 O36B A9 32 2876 A6 AB 0 24344 0 O136 24344 2852 5 2 AE r R925 "/0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)*1.[3]" A4 r R925 O143 23304 2080 O45 23304 2080 O45 24504 2080 O22 24504 2080 O22 23304 2080 5 2 AE r R926 "/0(MiChip)/2(MemCtlA)*1.[11]" A4 r R926 O11C 10104 2080 O45 10104 2080 O45 11224 2080 O22 11224 2080 O22 10104 2080 5 2 AE r R6D1 A4 r R6D1 O143 16264 2016 O45 16264 2016 O45 17464 2016 O13A 17464 0 O159 16264 2016 9 2 AE r R5F1 A4 r R5F1 O36C A9 10112 32 A6 AA 0 12744 1824 O45 16024 1824 O45 12744 1824 O45 18984 1824 O45 22824 1824 OF1 22824 1824 OF1 16024 1824 O121 18984 0 OF1 12744 1824 5 2 AE r R414 A4 r R414 O184 17144 1056 O45 17144 1056 O45 17304 1056 OF1 17304 0 O121 17144 1056 5 2 AE r R927 "/0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)*1.[5]" A4 r R927 O263 22264 2144 O45 22264 2144 O45 24584 2144 O130 24584 2144 O13E 22264 0 9 2 AE r R26A A4 r R26A O36D A9 9392 32 A6 AA 0 14584 32 O45 17064 32 O45 14584 32 O45 18824 32 O45 23944 32 O223 23944 32 OEE 17064 0 OEE 18824 0 O223 14584 32 5 2 AE r R50E A4 r R50E O36E A9 18112 32 A6 AA 0 10584 96 O45 10584 96 O45 28664 96 O1CF 28664 96 OFA 10584 0 5 2 AE r R928 "/0(MiChip)/2(MemCtlA)*1.[60]" A4 r R928 O184 10904 2720 O45 10904 2720 O45 11064 2720 O10E 11064 2720 O10E 10904 2720 9 2 AE r R5F4 A4 r R5F4 O36F A9 19872 32 A6 AA 0 7304 2208 O45 9784 2208 O45 7304 2208 O45 13544 2208 O45 27144 2208 O11B 27144 0 O11D 9784 2208 O11B 13544 0 O11D 7304 2208 7 2 AE r R1A9 A4 r R1A9 O2FA 15944 480 O45 17704 480 O45 15944 480 O45 28104 480 O112 28104 480 O13D 17704 0 O112 15944 480 5 2 AE r R1AB A4 r R1AB O324 7384 928 O45 7384 928 O45 17864 928 OEB 17864 0 O11E 7384 928 5 2 AE r R929 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11).One" A4 r R929 O120 21624 2848 O45 21624 2848 O45 24264 2848 OEE 24264 2848 OEE 21624 2848 5 2 AE r R7A4 A4 r R7A4 O1BC 12584 1440 O45 12584 1440 O45 16424 1440 O128 16424 1440 O128 12584 0 5 2 AE r R92A "/0(MiChip)/5(DataMux)/0(ParGen)*1.[10]" A4 r R92A O161 16344 288 O45 16344 288 O45 18104 288 O10A 18104 0 O10A 16344 0 5 2 AE r R92B "/0(MiChip)/2(MemCtlA)*1.[42]" A4 r R92B O120 10984 2336 O45 10984 2336 O45 13624 2336 O102 13624 2336 O102 10984 2336 7 2 AE r R41A A4 r R41A O22A 8824 2656 O45 9064 2656 O45 8824 2656 O45 11784 2656 O1D7 11784 0 O107 9064 2656 O107 8824 2656 5 2 AE r R92C "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21).[2]" A4 r R92C O139 18744 1376 O45 18744 1376 O45 19384 1376 OFE 19384 0 O100 18744 1376 5 2 AE r R92D "/0(MiChip)/4(RefreshCtr)*1.[1][2]" A4 r R92D O118 11864 2784 O45 11864 2784 O45 12184 2784 OFA 12184 2784 O1CF 11864 0 5 2 AE r R1AE A4 r R1AE O15B 18664 1696 O45 18664 1696 O45 21144 1696 OEC 21144 0 O127 18664 1696 5 2 AE r R1B1 A4 r R1B1 O120 18904 928 O45 18904 928 O45 21544 928 O11E 21544 928 OEB 18904 0 5 2 AE r R33C A4 r R33C O30A 5784 416 O45 5784 416 O45 7864 416 O10D 7864 416 O10C 5784 0 3 2 AE r R878 A4 r R878 O135 13704 2852 O36B 13704 0 O136 13704 2852 5 2 AE r R92E "/0(MiChip)/4(RefreshCtr)*1.Output[2]" A4 r R92E O2B3 12104 2656 O45 12104 2656 O45 24104 2656 O107 24104 2656 O107 12104 2656 3 2 AE r R7A9 A4 r R7A9 OFB 12424 2720 O10E 12504 2720 O1D5 12424 0 3 2 AE r R92F "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[0]" A4 r R92F OFB 6984 2848 OEE 7064 2848 OEE 6984 2848 5 2 AE r R7AA A4 r R7AA O2D4 17384 2464 O45 17384 2464 O45 20424 2464 O10C 20424 2464 O10D 17384 0 5 2 AE r R930 "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)*1.[7]" A4 r R930 O1D4 7704 2144 O45 7704 2144 O45 20584 2144 O130 20584 2144 O130 7704 2144 7 2 AE r R931 "DPadEnb" A4 r R931 O2A3 18904 992 O45 19704 992 O45 18904 992 O45 19944 992 OF6 19944 0 OF6 19704 0 O12F 18904 992 7 2 AE r R932 "/0(MiChip)/4(RefreshCtr)*1.Output[3]" A4 r R932 O321 24024 32 O45 24984 32 O45 24024 32 O45 29064 32 OEE 29064 0 O223 24984 32 O223 24024 32 5 2 AE r R933 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/13(counterUpCtrl2).[3]" A4 r R933 O15C 6344 352 O45 6344 352 O45 6584 352 O116 6584 352 OF4 6344 0 3 2 AE r R934 "/0(MiChip)/3(AddrMux)/1(TstBuffer)*1.nInput[1]" A4 r R934 OFB 28344 2848 OEE 28424 2848 OEE 28344 2848 5 2 AE r R6DB A4 r R6DB O129 9864 608 O45 9864 608 O45 13224 608 O119 13224 0 OF3 9864 608 5 2 AE r R935 "/0(MiChip)/2(MemCtlA)*1.[46]" A4 r R935 O157 5624 2464 O45 5624 2464 O45 7464 2464 O10C 7464 2464 O10C 5624 2464 5 2 AE r R87B A4 r R87B O104 6264 32 O45 6264 32 O45 12264 32 O223 12264 32 OEE 6264 0 3 2 AE r R936 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)*1.nInput[7]" A4 r R936 OFB 10824 32 OEE 10904 0 OEE 10824 0 5 2 AE r R937 "/0(MiChip)/5(DataMux)/0(ParGen)*1.[15]" A4 r R937 O2EF 14264 224 O45 14264 224 O45 18184 224 O107 18184 0 O1D7 14264 224 9 2 AE r R87C A4 r R87C O2F4 9704 416 O45 14504 416 O45 9704 416 O45 21384 416 O45 22744 416 O10D 22744 416 O10D 14504 416 O10C 21384 0 O10D 9704 416 7 2 AE r R938 "/0(MiChip)/2(MemCtlA)*1.[18]" A4 r R938 O131 10504 800 O45 13304 800 O45 10504 800 O45 13944 800 O22 13944 0 O133 13304 800 O133 10504 800 9 2 AE r REE A4 r REE O370 A9 16032 32 A6 AA 0 9224 736 O45 20184 736 O45 9224 736 O45 20504 736 O45 25224 736 O13E 25224 736 O130 20184 0 O13E 20504 736 O13E 9224 736 11 2 AE r R1B4 A4 r R1B4 O371 A9 22832 32 A6 AA 0 4024 1504 O45 8104 1504 O45 22344 1504 O45 4024 1504 O45 17944 1504 O45 26824 1504 OFE 26824 1504 OFE 8104 1504 OFE 17944 1504 O100 22344 0 OFE 4024 1504 5 2 AE r R939 "/0(MiChip)/7(StatusReg)*1.[17]" A4 r R939 O118 19304 1248 O45 19304 1248 O45 19624 1248 OF7 19624 1248 OF7 19304 1248 7 2 AE r R93A "/0(MiChip)/6(AddrCtl)*1.ctlCmp" A4 r R93A O2A3 23784 864 O45 24424 864 O45 23784 864 O45 24824 864 O159 24824 0 O13A 24424 864 O159 23784 0 5 2 AE r R7B3 A4 r R7B3 O2F1 15144 992 O45 15144 992 O45 17864 992 O12F 17864 992 OF6 15144 0 9 2 AE r RB A4 r RB O305 23544 1184 O45 26184 1184 O45 23544 1184 O45 26664 1184 O45 26824 1184 O127 26824 0 OEC 26184 1184 OEC 26664 1184 OEC 23544 1184 5 2 AE r R604 A4 r R604 O15C 19544 224 O45 19544 224 O45 19784 224 O107 19784 0 O107 19544 0 5 2 AE r R881 A4 r R881 O2D1 15064 800 O45 15064 800 O45 24904 800 O133 24904 800 O22 15064 0 5 2 AE r R882 A4 r R882 O18E 20824 2464 O45 20824 2464 O45 22264 2464 O10C 22264 2464 O10D 20824 0 5 2 AE r R6E2 A4 r R6E2 O12E 5224 32 O45 5224 32 O45 5944 32 OEE 5944 0 O223 5224 32 5 2 AE r R7B8 A4 r R7B8 O15C 7384 480 O45 7384 480 O45 7624 480 O13D 7624 0 O13D 7384 0 3 2 AE r R93B "PIRQ" A4 r R93B O372 A9 13256 24 A6 AA 0 19544 292 O45 19544 288 O373 A9 32 2620 A6 AB 0 19544 292 5 2 AE r R93C "/0(MiChip)/5(DataMux)/12(ParGen)*1.[12]" A4 r R93C O11C 13144 32 O45 13144 32 O45 14264 32 OEE 14264 0 OEE 13144 0 7 2 AE r R6E5 A4 r R6E5 O1D3 12664 1312 O45 18744 1312 O45 12664 1312 O45 21944 1312 OF0 21944 1312 O114 18744 0 OF0 12664 1312 5 2 AE r R42B A4 r R42B O118 8184 416 O45 8184 416 O45 8504 416 O10C 8504 0 O10C 8184 0 5 2 AE r R93D "/0(MiChip)/2(MemCtlA)/32(fsm2)*1.[2]" A4 r R93D O184 7624 2464 O45 7624 2464 O45 7784 2464 O10C 7784 2464 O10C 7624 2464 3 2 AE r R93E "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)*1.nInput[0]" A4 r R93E OFB 9464 2848 OEE 9544 2848 OEE 9464 2848 9 2 AE r R103 A4 r R103 O2E1 4984 2592 O45 11464 2592 O45 4984 2592 O45 19704 2592 O45 25464 2592 O10F 25464 0 O10A 11464 2592 O10A 19704 2592 O10A 4984 2592 5 2 AE r R93F "/0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)*1.[5]" A4 r R93F OF2 15544 1760 O45 15544 1760 O45 16024 1760 O14D 16024 0 O105 15544 1760 3 2 AE r R7BE A4 r R7BE OFB 25304 2464 O10D 25384 0 O10C 25304 2464 5 2 AE r R940 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)*1.nInput[2]" A4 r R940 O2FE 8024 2464 O45 8024 2464 O45 14344 2464 O10C 14344 2464 O10C 8024 2464 7 2 AE r R60C A4 r R60C O2C3 6504 288 O45 7304 288 O45 6504 288 O45 8904 288 O10F 8904 288 O10A 7304 0 O10F 6504 288 7 2 AE r R941 "/0(MiChip)/7(StatusReg)*1.[14][3]" A4 r R941 O2CB 19144 864 O45 21384 864 O45 19144 864 O45 21704 864 O13A 21704 864 O13A 21384 864 O13A 19144 864 7 2 AE r R942 "/0(MiChip)/6(AddrCtl)*1.memCmp" A4 r R942 O2EB 16744 1120 O45 22104 1120 O45 16744 1120 O45 23544 1120 O105 23544 0 O14D 22104 1120 O14D 16744 1120 5 2 AE r R524 A4 r R524 O14B 24184 992 O45 24184 992 O45 25144 992 OF6 25144 0 O12F 24184 992 5 2 AE r R943 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)*1.nInput[5]" A4 r R943 O184 22424 2464 O45 22424 2464 O45 22584 2464 O10C 22584 2464 O10C 22424 2464 5 2 AE r R88D A4 r R88D O18C 11704 2080 O45 11704 2080 O45 12504 2080 O133 12504 0 O22 11704 2080 5 2 AE r R6EC A4 r R6EC OF2 19944 1952 O45 19944 1952 O45 20424 1952 O11E 20424 0 OEB 19944 1952 5 2 AE r R944 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)*1.nInput[6]" A4 r R944 O118 23144 2464 O45 23144 2464 O45 23464 2464 O10C 23464 2464 O10D 23144 0 5 2 AE r R10A A4 r R10A O374 A9 13952 32 A6 AA 0 12424 2784 O45 12424 2784 O45 26344 2784 O1CF 26344 0 OFA 12424 2784 5 2 AE r R7C3 A4 r R7C3 O180 24664 2848 O45 24664 2848 O45 25064 2848 OEE 25064 2848 O223 24664 0 5 2 AE r R945 "/0(MiChip)/7(StatusReg)*1.[14][6]" A4 r R945 O2C0 18984 2016 O45 18984 2016 O45 26104 2016 O159 26104 2016 O159 18984 2016 9 2 AE r R10D A4 r R10D O375 A9 20432 32 A6 AA 0 4984 2528 O45 5784 2528 O45 4984 2528 O45 20664 2528 O45 25384 2528 OF4 25384 2528 OF4 5784 2528 OF4 20664 2528 O116 4984 0 9 2 AE r R112 A4 r R112 O368 7224 352 O45 9304 352 O45 7224 352 O45 27784 352 O45 28584 352 O116 28584 352 OF4 9304 0 O116 27784 352 O116 7224 352 5 2 AE r R1CC A4 r R1CC O14B 17064 608 O45 17064 608 O45 18024 608 O119 18024 0 OF3 17064 608 5 2 AE r R946 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)*1.nInput[1]" A4 r R946 O18C 8344 224 O45 8344 224 O45 9144 224 O1D7 9144 224 O107 8344 0 5 2 AE r R947 "/0(MiChip)/4(RefreshCtr)*1.[13]" A4 r R947 O139 20344 992 O45 20344 992 O45 20984 992 OF6 20984 0 OF6 20344 0 3 2 AE r R948 "PDin31" A4 r R948 OFB 22504 32 OEE 22584 0 O223 22504 32 5 2 AE r R1CE A4 r R1CE O376 A9 19632 32 A6 AA 0 8264 544 O45 8264 544 O45 27864 544 O109 27864 544 O102 8264 0 5 2 AE r R6F0 A4 r R6F0 O184 16744 1056 O45 16744 1056 O45 16904 1056 O121 16904 1056 OF1 16744 0 7 2 AE r R1D1 A4 r R1D1 O2FA 15864 2336 O45 17624 2336 O45 15864 2336 O45 28024 2336 O102 28024 2336 O109 17624 0 O102 15864 2336 5 2 AE r R52F A4 r R52F O161 9544 2784 O45 9544 2784 O45 11304 2784 OFA 11304 2784 O1CF 9544 0 0 0 38656 0 1 AE r R949 "MIInnerChan12" O377 A2 0 0 32800 864 83 O378 A2 0 0 4000 832 2 O379 A2 0 0 4000 80 1 O37A A9 4000 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 4000 80 R2 1059061760 0 0 0 0 0 0 0 O37B A2 0 0 4000 80 1 O37A 0 0 0 2 A4 r RC AE r RC 0 0 4000 80 R2 1059061760 0 0 0 0 752 0 0 0 0 4000 832 R94A "MIInnerLeft12" 1031153506 0 1 0 0 0 0 0 O24 4000 0 0 2 AE r R94B "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 4800 0 0 2 AE r R94C "/0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/0(decoder12)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/0(decoder12)/0(Inv)*1*1*1" A1A a A1A O24 4960 0 0 2 AE r R94D "/0(MiChip)/2(MemCtlA)/40(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/38(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/1(FF)*1*1*1*1*1*1*1*1*1" A1A a A1A O24 5760 0 0 2 AE r R94E "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O16D 6560 0 0 2 AE r R94F "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/13(counterUpCtrl2)/0(B)/Buffer0" A1A a A1A O18 6784 0 0 2 AE r R950 "PDin39-12" A1A a A1A O86 6880 0 0 2 AE r R951 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv0" A1A a A1A OCE 7040 0 0 2 AE r R952 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver0" A1A a A1A O171 7360 0 0 2 AE r R953 "/0(MiChip)/2(MemCtlA)/32(fsm2)/1(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A OAF 7680 0 0 2 AE r R954 "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O86 7920 0 0 2 AE r R955 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv2" A1A a A1A O24 8080 0 0 2 AE r R956 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 8880 0 0 2 AE r R957 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv5" A1A a A1A O86 9040 0 0 2 AE r R958 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv1" A1A a A1A O86 9200 0 0 2 AE r R959 "/0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1*1*1*1" A1A a A1A O86 9360 0 0 2 AE r R95A "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv0" A1A a A1A OCE 9520 0 0 2 AE r R95B "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver0" A1A a A1A O24 9840 0 0 2 AE r R95C "/0(MiChip)/2(MemCtlA)/49(FF)*1" A1A a A1A O168 10640 0 0 2 AE r R95D "/0(MiChip)/2(MemCtlA)/52(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O171 10960 0 0 2 AE r R95E "/0(MiChip)/2(MemCtlA)/50(or2)/0(NormalizedOr2)/0(Or2)" A1A a A1A O86 11280 0 0 2 AE r R95F "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv0" A1A a A1A O24 11440 0 0 2 AE r R960 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/10(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/9(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/8(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/7(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/6(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/5(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/4(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/3(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/2(counterUp1B2)//0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/1(counterUp1B2)/0(FF)*1*1*1*1*1*1*1*1*1*1" A1A a A1A O16D 12240 0 0 2 AE r R961 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/13(counterUpCtrl2)/1(B)/Buffer0" A1A a A1A OCE 12480 0 0 2 AE r R962 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver5" A1A a A1A ODD 12800 0 0 2 AE r R963 "/0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O37C AD -32 0 432 856 O37D A1B -32 0 432 856 1 1 O37E AD -8 0 456 856 O37F A2 -8 0 456 856 159 OA8 24 752 0 4 A10 r R23 A4 r RC A12 i 59018 A16 lor 1 RC O94 296 352 2 1 A10 r R3C OA8 24 0 0 4 A10 r R23 A4 r RB A12 i 59016 A16 lor 1 RB OA9 456 328 2 1 A10 r R23 O8C 368 280 0 1 A12 i 59014 OA0 208 280 0 1 A12 i 59012 O9F 128 280 0 1 A12 i 59010 O9E 48 280 0 1 A12 i 59008 O1D 24 792 0 1 A10 r R23 O95 64 312 0 1 A10 r R3D O1E 24 8 0 1 A10 r R23 O1F 208 8 0 1 A10 r R23 O20 208 792 0 1 A10 r R23 O91 48 368 0 1 A10 r R3D OA1 56 312 0 1 A10 r R3D O32 68 312 0 1 A10 r R3D OA2 136 368 0 1 A10 r R3C O94 136 352 2 1 A10 r R3C O93 128 80 0 1 A10 r R3B O93 40 80 0 1 A10 r R3B O78 96 312 0 1 A10 r R3C O41 96 288 0 1 A10 r R3B O1D 104 792 0 1 A10 r R23 O95 144 312 0 1 A10 r R3D O1E 104 8 0 1 A10 r R23 O1F 128 8 0 1 A10 r R23 O20 128 792 0 1 A10 r R23 O91 128 368 0 1 A10 r R3D OA1 136 312 0 1 A10 r R3D O32 148 312 0 1 A10 r R3D OA2 216 368 0 1 A10 r R3C OA2 128 368 0 1 A10 r R3C O94 216 352 2 1 A10 r R3C O93 208 80 0 1 A10 r R3B O93 120 80 0 1 A10 r R3B O78 176 312 0 1 A10 r R3C O31 216 64 2 1 A10 r R3B O41 176 288 0 1 A10 r R3B O1D 184 792 0 1 A10 r R23 O95 224 312 0 1 A10 r R3D O1E 184 8 0 1 A10 r R23 O1F 48 8 0 1 A10 r R23 O20 48 792 0 1 A10 r R23 O91 208 368 0 1 A10 r R3D OA1 216 312 0 1 A10 r R3D O32 228 312 0 1 A10 r R3D OA2 296 368 0 1 A10 r R3C OA2 208 368 0 1 A10 r R3C O93 288 80 0 1 A10 r R3B O93 200 80 0 1 A10 r R3B O78 256 312 0 1 A10 r R3C O31 296 64 2 1 A10 r R3B O41 256 288 0 1 A10 r R3B O1D 264 792 0 1 A10 r R23 O95 304 312 0 1 A10 r R3D O1E 264 8 0 1 A10 r R23 O1F 288 8 0 1 A10 r R23 O20 288 792 0 1 A10 r R23 O91 288 368 0 1 A10 r R3D OA1 296 312 0 1 A10 r R3D O32 308 312 0 1 A10 r R3D OA2 288 368 0 1 A10 r R3C O94 376 352 2 1 A10 r R3C O93 368 80 0 1 A10 r R3B O93 280 80 0 1 A10 r R3B O78 336 312 0 1 A10 r R3C O41 336 288 0 1 A10 r R3B O1D 344 792 0 1 A10 r R23 O1E 344 8 0 1 A10 r R23 O1F 368 8 0 1 A10 r R23 O20 368 792 0 1 A10 r R23 O92 80 656 2 0 O3E 48 664 0 0 O92 80 608 2 0 O3E 48 616 0 0 O92 80 560 2 0 O3E 48 568 0 0 O92 80 512 2 0 O3E 48 520 0 0 O92 80 464 2 0 O3E 48 472 0 0 O92 160 704 2 0 O3E 128 712 0 0 O92 160 656 2 0 O3E 128 664 0 0 O92 160 608 2 0 O3E 128 616 0 0 O92 160 560 2 0 O3E 128 568 0 0 O92 240 656 2 0 O3E 208 664 0 0 O92 240 608 2 0 O3E 208 616 0 0 O92 240 560 2 0 O3E 208 568 0 0 O92 240 512 2 0 O3E 208 520 0 0 O92 240 464 2 0 O3E 208 472 0 0 O92 320 704 2 0 O3E 288 712 0 0 O92 320 656 2 0 O3E 288 664 0 0 O92 320 608 2 0 O3E 288 616 0 0 O92 320 560 2 0 O3E 288 568 0 0 O92 400 656 2 0 O3E 368 664 0 0 O92 400 608 2 0 O3E 368 616 0 0 O92 400 560 2 0 O3E 368 568 0 0 O92 400 512 2 0 O3E 368 520 0 0 O92 400 464 2 0 O3E 368 472 0 0 O2A0 56 464 0 0 O90 296 344 0 0 O16C 376 312 0 0 O91 48 128 0 0 O30 48 136 0 0 O91 48 176 0 0 O30 48 184 0 0 O91 48 224 0 0 O30 48 232 0 0 O91 288 80 0 0 O30 288 88 0 0 O91 288 128 0 0 O30 288 136 0 0 O91 288 176 0 0 O30 288 184 0 0 O91 368 128 0 0 O30 368 136 0 0 O91 368 176 0 0 O30 368 184 0 0 O91 368 224 0 0 O30 368 232 0 0 O2A0 56 248 0 0 O96 296 248 0 0 O96 376 248 0 0 O92 80 368 2 0 O45 48 376 0 0 O92 160 368 2 0 O45 128 376 0 0 O92 240 368 2 0 O45 208 376 0 0 O92 400 368 2 0 O45 368 376 0 0 O97 40 368 0 1 A10 r R3C O97 376 368 0 1 A10 r R3C O22 48 0 0 3 A10 r R23 A12 i 59008 A16 lor 1 R42 O31 136 64 2 1 A10 r R3B O22 128 0 0 3 A10 r R23 A12 i 59010 A16 lor 1 R43 O22 208 0 0 3 A10 r R23 A12 i 59012 A16 lor 1 R44 O31 376 64 2 1 A10 r R3B O22 368 0 0 3 A10 r R23 A12 i 59014 A16 lor 1 R3A O1B 248 16 0 1 A12 i 59016 O1C 240 800 0 1 A12 i 59018 24 0 424 832 R964 "C2AN03A.mask" 1048576000 0 1 2 A28 r R46 A17 i 74747 1 A18 a A19 0 1 A18 a A19 13280 0 0 2 AE r R965 "/0(MiChip)/2(MemCtlA)/53(and3)/0(NormalizedAnd3)/0(And3)" A1A a A1A O86 13680 0 0 2 AE r R966 "/0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/11(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 13840 0 0 2 AE r R967 "/0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 14320 0 0 2 AE r R968 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver2" A1A a A1A ODD 14640 0 0 2 AE r R969 "/0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A ODD 15120 0 0 2 AE r R96A "/0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/1(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 15600 0 0 2 AE r R96B "/0(MiChip)/6(AddrCtl)/15(EqConstant)/1(Inv)" A1A a A1A OCE 15760 0 0 2 AE r R96C "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver5" A1A a A1A O18 16064 0 0 2 AE r R96D "PDin35-12" A1A a A1A O18 16144 0 0 2 AE r R96E "PDin36-12" A1A a A1A O18 16224 0 0 2 AE r R96F "PDout29-12" A1A a A1A O18 16304 0 0 2 AE r R970 "PDout38-12" A1A a A1A O18 16384 0 0 2 AE r R971 "PDTPin-12" A1A a A1A O18 16464 0 0 2 AE r R972 "PDin37-12" A1A a A1A OCA 16560 0 0 2 AE r R973 "/0(MiChip)/6(AddrCtl)/12(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O18 16784 0 0 2 AE r R974 "PDin38-12" A1A a A1A O18 16864 0 0 2 AE r R975 "PDin32-12" A1A a A1A O18 16944 0 0 2 AE r R976 "PDTPout-12" A1A a A1A O18 17024 0 0 2 AE r R977 "RPadEnb-12" A1A a A1A O18 17104 0 0 2 AE r R978 "PDout39-12" A1A a A1A OCA 17200 0 0 2 AE r R979 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5)/1(NormalizedNor2)/0(Nor2)" A1A a A1A ODD 17440 0 0 2 AE r R97A "/0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O24 17920 0 0 2 AE r R97B "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 18720 0 0 2 AE r R97C "/0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/10(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/9(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/8(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/5(DataMux)/6(DataLatchMux)/1(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/9(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/8(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/7(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/6(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/5(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/4(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/3(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/2(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/1(NormalizedMuxD21)//0(MiChip)/3(AddrMux)/4(mux2)/0(Mux)/1(Mux)/0(NormalizedMuxD21)/0(Inv)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O18 18864 0 0 2 AE r R97D "DPadEnb-12" A1A a A1A O86 18960 0 0 2 AE r R97E "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv9" A1A a A1A O98 19120 0 0 2 AE r R97F "/0(MiChip)/7(StatusReg)/2(ffrs1)/1(nor3)/0(NormalizedNor3)/0(Nor3)" A1A a A1A OCA 19440 0 0 2 AE r R980 "/0(MiChip)/7(StatusReg)/2(ffrs1)/0(nor2)/0(NormalizedNor2)/0(Nor2)" A1A a A1A O24 19680 0 0 2 AE r R981 "/0(MiChip)/2(MemCtlA)/47(FF)*1" A1A a A1A O86 20480 0 0 2 AE r R982 "/0(MiChip)/2(MemCtlA)/32(fsm2)/0(ffR)//0(MiChip)/2(MemCtlA)/28(fsm1i)/0(ffR)//0(MiChip)/2(MemCtlA)/25(fsm1)/0(ffR)//0(MiChip)/2(MemCtlA)/21(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/17(fsm2i)/0(ffR)//0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1*1*1*1*1*1" A1A a A1A O24 20640 0 0 2 AE r R983 "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OAF 21440 0 0 2 AE r R984 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/1(Or5)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O86 21680 0 0 2 AE r R985 "/0(MiChip)/7(StatusReg)/8(TstBuffer)/0(InverterSequence)/Inv6" A1A a A1A O86 21840 0 0 2 AE r R986 "/0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/1(Inv)" A1A a A1A O168 22000 0 0 2 AE r R987 "/0(MiChip)/6(AddrCtl)/5(and2)/0(NormalizedAnd2)/0(And2)" A1A a A1A O86 22320 0 0 2 AE r R988 "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv5" A1A a A1A O18 22464 0 0 2 AE r R989 "PDin31-12" A1A a A1A OCE 22560 0 0 2 AE r R98A "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/1(TstBufferInv)/0(TristateSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver5" A1A a A1A ODD 22880 0 0 2 AE r R98B "/0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/2(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 23360 0 0 2 AE r R98C "/0(MiChip)/5(DataMux)/10(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/9(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/8(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/6(DataLatchMux)/2(TstBuffer)/0(InverterSequence)//0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv6" A1A a A1A O86 23520 0 0 2 AE r R98D "/0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv2" A1A a A1A OCE 23680 0 0 2 AE r R98E "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver2" A1A a A1A OAF 24000 0 0 2 AE r R98F "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/6/2(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A OCA 24240 0 0 2 AE r R990 "/0(MiChip)/6(AddrCtl)/15(EqConstant)/0(Nor11)/0(NormalizedNor2)/0(Nor2)" A1A a A1A ODD 24480 0 0 2 AE r R991 "/0(MiChip)/5(DataMux)/12(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/12(ParGen)/0(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/13(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/12(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/11(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/10(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/9(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/8(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/7(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/6(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/5(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/4(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/3(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/1(XOR4)//0(MiChip)/5(DataMux)/0(ParGen)/0(XOR4)/0(Xor2)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OAF 24960 0 0 2 AE r R992 "/0(MiChip)/4(RefreshCtr)/3(FastCounterUp12)/0(CLP12)/1/6/1(nand2)/0(NormalizedNand2)/0(Nand2)" A1A a A1A O86 25200 0 0 2 AE r R993 "/0(MiChip)/2(MemCtlA)/14(fsm1)/0(ffR)//0(MiChip)/1(ClockGen)/3(ffR)/0(Inv)*1*1" A1A a A1A O24 25360 0 0 2 AE r R994 "/0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple9//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple8//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple7//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple6//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple5//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple4//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple3//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple2//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple1//0(MiChip)/7(StatusReg)/9(RegisterSimple)/reg1BSimple0//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple39//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple38//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple37//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple36//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple35//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple34//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple33//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple32//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple31//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A O86 26160 0 0 2 AE r R995 "/0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv6" A1A a A1A OCE 26320 0 0 2 AE r R996 "/0(MiChip)/5(DataMux)/3(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver6" A1A a A1A O86 26640 0 0 2 AE r R997 "/0(MiChip)/5(DataMux)/3(TstBuffer)/0(InverterSequence)/Inv0" A1A a A1A O24 26800 0 0 2 AE r R998 "/0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple30//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple29//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple28//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple27//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple26//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple25//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple24//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple23//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple22//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple21//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple20//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple19//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple18//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple17//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple16//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple15//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple14//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple13//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple12//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple11//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple10//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple9//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple8//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple7//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple6//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple5//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple4//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple3//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple2//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple1//0(MiChip)/5(DataMux)/4(RegisterSimple)/reg1BSimple0//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple15//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple14//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple13//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple12//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple11//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple10//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple9//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple8//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple7//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple6//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple5//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple4//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple3//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple2//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple1//0(MiChip)/4(RefreshCtr)/5(RegisterSimple)/reg1BSimple0//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple15//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple14//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple13//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple12//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple11//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple10//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple9//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple8//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple7//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple6//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple5//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple4//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple3//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple2//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple1//0(MiChip)/3(AddrMux)/6(RegisterSimple)/reg1BSimple0/0(FF)*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1*1" A1A a A1A OCE 27600 0 0 2 AE r R999 "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver15" A1A a A1A OCE 27920 0 0 2 AE r R99A "/0(MiChip)/7(StatusReg)/8(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver6" A1A a A1A O86 28240 0 0 2 AE r R99B "/0(MiChip)/3(AddrMux)/1(TstBuffer)/0(InverterSequence)/Inv1" A1A a A1A OCE 28400 0 0 2 AE r R99C "/0(MiChip)/3(AddrMux)/1(TstBuffer)/1(TstBufferInv)/0(TristateSequence)/TstDriver1" A1A a A1A O380 A2 0 0 4080 832 2 O381 A2 0 0 4080 80 1 O382 A9 4080 80 A6 AA 0 0 0 0 2 A4 r RB AE r RB 0 0 4080 80 R2 1059061760 0 0 0 0 0 0 0 O383 A2 0 0 4080 80 1 O382 0 0 0 2 A4 r RC AE r RC 0 0 4080 80 R2 1059061760 0 0 0 0 752 0 0 0 0 4080 832 R99D "MIInnerRight12" 1031153506 0 1 0 28720 0 0 0 0 0 32800 832 R99E "MIInnerIntRow12" 1030556027 0 0 0 0 41568 0 1 AE r R99F "Row12" 0 0 32800 42400 R9A0 "MIInner" 983200529 0 0 0 1 A18 a A19 14368 9568 0 0 O384 A2 0 0 4368 4368 1 O385 AD 0 0 4368 4368 O386 A2 0 0 4368 4368 25 OA 4368 0 2 0 O8 3152 0 0 2 A12 i 83521 A16 lor 1 R9 O387 A9 880 1312 A6 AB 0 1312 672 2 2 A12 i 133 A16 lor 1 RA O388 A9 1552 880 A6 AA 0 1552 0 2 0 O388 0 672 0 0 O389 A9 288 640 A6 AB 0 640 352 2 2 A12 i 134 A16 lor 1 RC OA 0 3152 0 0 O9 3800 3152 2 1 A12 i 132 O38A A11 RA R24 8 0 144 696 0 1 A12 i 133 O38B A9 248 320 A6 AB 0 320 72 2 2 A12 i 135 A16 lor 1 RB O38B 320 320 4 0 O38C A9 288 600 A6 AB 0 640 600 4 0 O38D A2 0 0 1536 512 8 O38E A2 0 0 384 256 24 O38F A2C C2LargeVia A6 64 64 A6 AB 0 256 0 0 0 O38F 256 64 0 0 O38F 320 64 0 0 O38F 320 0 0 0 O38F 320 128 0 0 O38F 320 192 0 0 O38F 256 192 0 0 O38F 256 128 0 0 O38F 0 128 0 0 O38F 0 192 0 0 O38F 64 192 0 0 O38F 64 128 0 0 O38F 128 128 0 0 O38F 128 192 0 0 O38F 192 192 0 0 O38F 192 128 0 0 O38F 192 0 0 0 O38F 192 64 0 0 O38F 128 64 0 0 O38F 128 0 0 0 O38F 64 0 0 0 O38F 64 64 0 0 O38F 0 64 0 0 O38F 0 0 0 0 0 0 384 256 R9A1 "viax" 1044905984 0 0 2 A17 i 83680 A2D DontFlatten a A2D 1152 0 0 0 O38E 1152 256 0 0 O38E 768 256 0 0 O38E 384 0 0 0 O38E 384 256 0 0 O38E 0 256 0 0 O38E 0 0 0 0 O38E 768 0 0 0 0 0 1536 512 R9A2 "viatop" 1036517376 0 0 2 A17 i 83679 A2D a A2D 4336 1568 2 0 O38D 3824 1568 2 0 O38D 3824 32 2 0 O38D 4336 32 2 0 O38D 32 3312 0 0 O390 A9 880 1552 A6 AB 0 672 0 0 0 O391 A11 RB R24 8 0 24 136 0 1 A12 i 135 O392 A11 RC R24 8 0 56 408 0 1 A12 i 134 O38D 1568 3824 0 0 O38D 1568 3312 0 0 O38D 16 960 0 0 O38D 32 3824 0 0 O393 A11 R9 R24 8 0 3528 3616 0 1 A12 i 83521 0 0 4368 4368 R9A3 "CornerPad.mask" 1040187392 0 0 1 A17 i 83683 1 A18 a A19 4368 4368 4 0 0 0 4368 4368 R2 1010535353 0 0 0 0 0 0 0 O394 A2 0 -4368 52800 0 33 O395 AD 0 0 1600 4368 O396 A2 0 0 1600 4368 998 O30 632 216 0 0 O397 A2 0 0 304 288 1 O398 A9 304 288 A6 AA 0 0 288 5 0 0 0 304 288 R9A4 "metPtr" 1043449628 0 0 2 A2D a A2D A17 i 83686 1104 1552 1 0 O399 A9 360 1056 A6 AF 0 1584 320 2 0 O39A A23 16 232 A6 A1D 0 632 352 0 0 O3E 696 552 0 0 O39B A9 16 24 A6 A1E 0 288 352 0 0 O39C A2 0 0 1024 1024 4 O39D A9 944 944 A6 A7 0 40 40 0 1 A2E SinixCMosBExtractProc a A2F ExtractNull O39E A2C A6 976 976 A6 AB 0 24 24 3 0 O39F A9 1024 1024 A6 AA 0 0 0 0 0 O3A0 A9 1024 1024 A6 AB 0 0 0 0 0 0 0 1024 1024 R9A5 "PadBlank" 1028128768 0 0 2 A17 i 83687 A2D a A2D 288 1840 3 0 O3A1 A9 32 72 A6 AA 0 1280 40 2 0 O397 496 1552 0 2 A12 i 258 A16 lor 1 R1 O3A2 A11 R1 R9A6 "Xerox/TiogaFonts/Helvetica7" 8 0 664 1664 0 1 A12 i 258 O3A3 A11 RA R9A6 8 0 568 712 0 1 A12 i 129 O3A4 A9 72 256 A6 AA 0 216 384 1 0 O3A5 A9 16 560 A6 A1E 0 1504 656 2 0 O3A1 1568 456 1 0 O3A6 A9 32 72 A6 A1E 0 1568 456 1 0 O32 1568 456 1 0 O32 1568 496 1 0 O3E 1336 392 1 0 O3E 1336 432 1 0 O3E 1336 472 1 0 O45 1344 120 1 0 O3A7 A30 C2DifShortCon A6 32 64 A6 A20 0 1416 152 7 0 O3A7 1416 248 7 0 O3A8 A9 32 232 A6 AA 0 1480 152 1 0 O3E 1336 512 1 0 O39A 1320 352 1 0 O30 1544 216 1 0 O30 1544 168 1 0 O3A9 A9 32 96 A6 AA 0 1544 120 1 0 O3A5 1504 112 1 0 O45 1400 608 1 0 O45 1480 608 1 0 O45 1336 608 1 0 O3AA A31 C2WellDifShortCon A6 32 64 A6 A1D 0 1440 584 1 0 O3AB A9 16 80 A6 A1E 0 1384 320 3 0 O3E 1336 552 1 0 O3E 1336 352 1 0 O3E 1440 416 1 0 O3E 1440 456 1 0 O3E 1440 496 1 0 O3E 1440 536 1 0 O3E 1544 552 1 0 O3AC A9 32 168 A6 AA 0 1440 416 1 0 O3AD A9 16 56 A6 A1E 0 1360 600 1 0 O30 1480 216 1 0 O30 1480 152 1 0 O3AE A9 16 136 A6 A1E 0 1504 136 1 0 O3AF A9 16 224 A6 A1E 0 1440 112 1 0 O3B0 A9 32 128 A6 A20 0 1544 120 1 0 O3E 1544 352 1 0 O3A8 1544 352 1 0 O3B1 A9 32 240 A6 AA 0 1304 352 3 0 O3B2 A1C A6 264 64 A6 A1D 0 1464 336 3 0 O3B3 A9 16 272 A6 A1E 0 1464 328 1 0 O3B2 1424 336 3 0 O3B2 1360 336 3 0 O3B2 1320 336 3 0 O3A8 1336 352 1 0 O30 1512 120 0 0 O3A7 1416 200 7 0 O3B4 A22 A6 160 64 A6 A20 0 1400 104 3 0 O3B0 1416 120 1 0 O3B5 A9 104 128 A6 AA 0 1416 120 1 0 O3B6 A9 32 128 A6 A14 0 1384 120 1 0 O45 1544 608 1 0 O3E 1544 416 1 0 O3B7 A23 16 64 A6 A1D 0 1544 384 1 0 O45 1344 168 1 0 O45 1344 216 1 0 O3A1 880 456 0 0 O3A6 880 456 0 0 O32 880 456 0 0 O32 880 496 0 0 O3E 1112 392 0 0 O3E 1112 432 0 0 O3E 1112 472 0 0 O45 1104 120 0 0 O3A7 1032 248 6 0 O3A8 968 152 0 0 O3E 1112 512 0 0 O39A 1128 352 0 0 O30 904 216 0 0 O30 904 168 0 0 O3A9 904 120 0 0 O3A5 944 112 0 0 O45 1048 608 0 0 O45 968 608 0 0 O45 1112 608 0 0 O3AA 1008 584 0 0 O3AB 1064 320 2 0 O3E 1112 552 0 0 O3E 1112 352 0 0 O3E 1008 416 0 0 O3E 1008 456 0 0 O3E 1008 496 0 0 O3E 1008 536 0 0 O3E 904 552 0 0 O3AC 1008 416 0 0 O3AD 1088 600 0 0 O30 968 216 0 0 O30 968 152 0 0 O3AE 944 136 0 0 O3AF 1008 112 0 0 O3B0 904 120 0 0 O3E 904 352 0 0 O3A8 904 352 0 0 O3B3 984 328 0 0 O3B2 1024 336 2 0 O3B2 1088 336 2 0 O3B2 1128 336 2 0 O3A8 1112 352 0 0 O30 936 120 1 0 O3B4 920 104 3 0 O3A7 1032 200 6 0 O3B4 1048 104 2 0 O3B0 1032 120 0 0 O3B5 1032 120 0 0 O3B6 1064 120 0 0 O45 904 608 0 0 O3E 904 416 0 0 O3B7 904 384 0 0 O45 1104 168 0 0 O45 1104 216 0 0 O45 80 72 0 0 O45 128 72 0 0 O3B8 A9 32 120 A6 AA 0 192 72 2 0 O45 464 32 0 0 O45 416 32 0 0 O3B1 536 32 2 0 O45 336 256 0 0 O45 336 208 0 0 O45 336 160 0 0 O30 504 224 0 0 O30 376 224 0 0 O30 296 256 0 0 O30 408 184 1 0 O30 408 144 1 0 O3A7 376 96 5 0 O3AB 496 264 2 0 O3B9 A22 A6 192 64 A6 A20 0 392 80 3 0 O3BA A9 16 152 A6 A20 0 520 96 0 0 O3A7 536 96 4 0 O30 440 96 0 0 O30 440 224 0 0 O30 440 184 0 0 O30 440 136 0 0 O30 504 104 0 0 O30 504 144 0 0 O30 504 184 0 0 O392 0 472 0 1 A12 i 121 O391 0 184 0 1 A12 i 213 O3BB A9 32 232 A6 A1E 0 1512 1312 1 0 O3BC A9 48 128 A6 A1E 0 1440 1320 2 0 O3BD A9 232 128 A6 AB 0 1440 1544 7 0 O3BE A22 A6 144 64 A6 A20 0 1376 1504 7 0 O3BC 1440 1544 7 0 O30 1392 1408 7 0 O30 1296 1376 0 0 O30 1424 1376 0 0 O30 1392 1488 7 0 O3BF A9 16 72 A6 A20 0 1392 1416 1 0 O30 1456 1456 2 0 O30 1328 1456 2 0 O30 1296 1416 0 0 O3C0 A9 16 112 A6 A20 0 1312 1488 4 0 O30 1424 1416 0 0 O3C0 1456 1488 4 0 O3C1 A9 32 176 A6 AA 0 1328 1312 1 0 O3C1 1456 1312 1 0 O30 1392 1448 7 0 O3BE 1440 1504 7 0 O3AC 1392 1376 1 0 O3C2 A9 32 128 A6 AA 0 1440 1344 7 0 O3C2 1440 1520 2 0 O3C3 A9 240 160 A6 AB 0 1600 1312 2 0 O3BC 672 1320 2 0 O3BD 672 1544 7 0 O3BE 608 1504 7 0 O3BC 672 1544 7 0 O30 624 1408 7 0 O30 528 1376 0 0 O30 656 1376 0 0 O30 624 1488 7 0 O3BF 624 1416 1 0 O30 688 1456 2 0 O30 560 1456 2 0 O30 528 1416 0 0 O3C0 544 1488 4 0 O30 656 1416 0 0 O3C0 688 1488 4 0 O3C1 560 1312 1 0 O3C1 688 1312 1 0 O30 624 1448 7 0 O3BE 672 1504 7 0 O3AC 624 1376 1 0 O3C2 672 1344 7 0 O3C2 672 1520 2 0 O3BC 800 1320 2 0 O3BD 800 1544 7 0 O3BE 736 1504 7 0 O3BC 800 1544 7 0 O30 752 1408 7 0 O30 656 1376 0 0 O30 784 1376 0 0 O30 752 1488 7 0 O3BF 752 1416 1 0 O30 816 1456 2 0 O30 688 1456 2 0 O30 656 1416 0 0 O3C0 672 1488 4 0 O30 784 1416 0 0 O3C0 816 1488 4 0 O3C1 688 1312 1 0 O3C1 816 1312 1 0 O30 752 1448 7 0 O3BE 800 1504 7 0 O3AC 752 1376 1 0 O3C2 800 1344 7 0 O3C2 800 1520 2 0 O3BC 416 1320 2 0 O3BD 416 1544 7 0 O3BE 352 1504 7 0 O3BC 416 1544 7 0 O30 368 1408 7 0 O30 272 1376 0 0 O30 400 1376 0 0 O30 368 1488 7 0 O3BF 368 1416 1 0 O30 432 1456 2 0 O30 304 1456 2 0 O30 272 1416 0 0 O3C0 288 1488 4 0 O30 400 1416 0 0 O3C0 432 1488 4 0 O3C1 304 1312 1 0 O3C1 432 1312 1 0 O30 368 1448 7 0 O3BE 416 1504 7 0 O3AC 368 1376 1 0 O3C2 416 1344 7 0 O3C2 416 1520 2 0 O3C4 A9 152 240 A6 AA 0 0 1312 0 0 O3C5 A9 240 288 A6 AB 0 288 1312 2 0 O3C6 A9 48 72 A6 A1E 0 1440 1320 3 0 O32 192 1344 0 0 O3C7 A9 32 144 A6 AA 0 1600 1312 2 0 O3C8 A9 32 64 A6 A1E 0 192 1312 0 0 O3C6 1440 1496 3 0 O32 1544 1520 0 0 O3C9 A9 32 240 A6 A1E 0 1544 1312 0 0 O3A9 288 1520 2 0 O3CA A9 32 208 A6 AA 0 192 1344 0 0 O3BC 544 1320 2 0 O3BD 544 1544 7 0 O3BE 480 1504 7 0 O3BC 544 1544 7 0 O30 496 1408 7 0 O30 400 1376 0 0 O30 528 1376 0 0 O30 496 1488 7 0 O3BF 496 1416 1 0 O30 560 1456 2 0 O30 432 1456 2 0 O30 400 1416 0 0 O3C0 416 1488 4 0 O30 528 1416 0 0 O3C0 560 1488 4 0 O3C1 432 1312 1 0 O3C1 560 1312 1 0 O30 496 1448 7 0 O3BE 544 1504 7 0 O3AC 496 1376 1 0 O3C2 544 1344 7 0 O3C2 544 1520 2 0 O3BC 928 1320 2 0 O3BD 928 1544 7 0 O3BE 864 1504 7 0 O3BC 928 1544 7 0 O30 880 1408 7 0 O30 784 1376 0 0 O30 912 1376 0 0 O30 880 1488 7 0 O3BF 880 1416 1 0 O30 944 1456 2 0 O30 816 1456 2 0 O30 784 1416 0 0 O3C0 800 1488 4 0 O30 912 1416 0 0 O3C0 944 1488 4 0 O3C1 816 1312 1 0 O3C1 944 1312 1 0 O30 880 1448 7 0 O3BE 928 1504 7 0 O3AC 880 1376 1 0 O3C2 928 1344 7 0 O3C2 928 1520 2 0 O3BC 1056 1320 2 0 O3BD 1056 1544 7 0 O3BE 992 1504 7 0 O3BC 1056 1544 7 0 O30 1008 1408 7 0 O30 912 1376 0 0 O30 1040 1376 0 0 O30 1008 1488 7 0 O3BF 1008 1416 1 0 O30 1072 1456 2 0 O30 944 1456 2 0 O30 912 1416 0 0 O3C0 928 1488 4 0 O30 1040 1416 0 0 O3C0 1072 1488 4 0 O3C1 944 1312 1 0 O3C1 1072 1312 1 0 O30 1008 1448 7 0 O3BE 1056 1504 7 0 O3AC 1008 1376 1 0 O3C2 1056 1344 7 0 O3C2 1056 1520 2 0 O3BC 1184 1320 2 0 O3BD 1184 1544 7 0 O3BE 1120 1504 7 0 O3BC 1184 1544 7 0 O30 1136 1408 7 0 O30 1040 1376 0 0 O30 1168 1376 0 0 O30 1136 1488 7 0 O3BF 1136 1416 1 0 O30 1200 1456 2 0 O30 1072 1456 2 0 O30 1040 1416 0 0 O3C0 1056 1488 4 0 O30 1168 1416 0 0 O3C0 1200 1488 4 0 O3C1 1072 1312 1 0 O3C1 1200 1312 1 0 O30 1136 1448 7 0 O3BE 1184 1504 7 0 O3AC 1136 1376 1 0 O3C2 1184 1344 7 0 O3C2 1184 1520 2 0 O3BC 1312 1320 2 0 O3BD 1312 1544 7 0 O3BE 1248 1504 7 0 O3BC 1312 1544 7 0 O30 1264 1408 7 0 O30 1168 1376 0 0 O30 1296 1376 0 0 O30 1264 1488 7 0 O3BF 1264 1416 1 0 O30 1328 1456 2 0 O30 1200 1456 2 0 O30 1168 1416 0 0 O3C0 1184 1488 4 0 O30 1296 1416 0 0 O3C0 1328 1488 4 0 O3C1 1200 1312 1 0 O3C1 1328 1312 1 0 O30 1264 1448 7 0 O3BE 1312 1504 7 0 O3AC 1264 1376 1 0 O3C2 1312 1344 7 0 O3C2 1312 1520 2 0 O30 1248 3456 0 0 O3BE 1328 3400 2 0 O3CB A9 312 128 A6 AB 0 1392 3416 2 0 O3CC A9 32 136 A6 AA 0 1280 3552 4 0 O3CD A9 16 104 A6 A20 0 1264 3416 1 0 O45 1376 3608 0 0 O30 1376 3456 0 0 O3CD 1408 3416 1 0 O3BE 1392 3400 2 0 O30 1376 3496 0 0 O3AC 1344 3528 4 0 O30 1344 3456 2 0 O30 1344 3416 2 0 O3C2 1392 3336 2 0 O45 1312 3368 5 0 O3CE A9 32 128 A6 A1E 0 1392 3376 2 0 O1F 1344 3280 2 0 O30 1280 3448 7 0 O30 1408 3448 7 0 O20 1344 3184 2 0 O45 1376 3336 0 0 O30 1312 3496 0 0 O20 1344 3664 2 0 O3CF A9 32 160 A6 A13 0 1408 3184 2 0 O3D0 A9 32 160 A6 AA 0 1408 3184 2 0 O3D1 A9 32 160 A6 A14 0 1408 3280 2 0 O3D0 1408 3280 2 0 O1F 1408 3280 2 0 O45 1312 3608 0 0 O3D1 1408 3568 2 0 O3CF 1408 3664 2 0 O3D0 1408 3664 2 0 O1F 1376 3568 0 0 O1F 1312 3568 0 0 O3CC 1408 3552 4 0 O3D2 A9 88 160 A6 AA 0 1408 3552 2 0 O20 1408 3664 2 0 O30 1248 3496 0 0 O20 1408 3184 2 0 O3D3 A9 128 216 A6 AB 0 1264 3368 5 0 O3D4 A9 88 160 A6 AF 0 1408 3152 2 0 O3D4 1408 3640 2 0 O30 1120 3456 0 0 O3BE 1200 3400 2 0 O3CB 1264 3416 2 0 O3CC 1152 3552 4 0 O3CD 1136 3416 1 0 O45 1248 3608 0 0 O30 1248 3456 0 0 O3CD 1280 3416 1 0 O3BE 1264 3400 2 0 O30 1248 3496 0 0 O3AC 1216 3528 4 0 O30 1216 3456 2 0 O30 1216 3416 2 0 O3C2 1264 3336 2 0 O45 1184 3368 5 0 O3CE 1264 3376 2 0 O1F 1216 3280 2 0 O30 1152 3448 7 0 O30 1280 3448 7 0 O20 1216 3184 2 0 O45 1248 3336 0 0 O30 1184 3496 0 0 O20 1216 3664 2 0 O3CF 1280 3184 2 0 O3D0 1280 3184 2 0 O3D1 1280 3280 2 0 O3D0 1280 3280 2 0 O1F 1280 3280 2 0 O45 1184 3608 0 0 O3D1 1280 3568 2 0 O3CF 1280 3664 2 0 O3D0 1280 3664 2 0 O1F 1248 3568 0 0 O1F 1184 3568 0 0 O3CC 1280 3552 4 0 O3D2 1280 3552 2 0 O20 1280 3664 2 0 O30 1120 3496 0 0 O20 1280 3184 2 0 O3D3 1136 3368 5 0 O3D4 1280 3152 2 0 O3D4 1280 3640 2 0 O30 992 3456 0 0 O3BE 1072 3400 2 0 O3CB 1136 3416 2 0 O3CC 1024 3552 4 0 O3CD 1008 3416 1 0 O45 1120 3608 0 0 O30 1120 3456 0 0 O3CD 1152 3416 1 0 O3BE 1136 3400 2 0 O30 1120 3496 0 0 O3AC 1088 3528 4 0 O30 1088 3456 2 0 O30 1088 3416 2 0 O3C2 1136 3336 2 0 O45 1056 3368 5 0 O3CE 1136 3376 2 0 O1F 1088 3280 2 0 O30 1024 3448 7 0 O30 1152 3448 7 0 O20 1088 3184 2 0 O45 1120 3336 0 0 O30 1056 3496 0 0 O20 1088 3664 2 0 O3CF 1152 3184 2 0 O3D0 1152 3184 2 0 O3D1 1152 3280 2 0 O3D0 1152 3280 2 0 O1F 1152 3280 2 0 O45 1056 3608 0 0 O3D1 1152 3568 2 0 O3CF 1152 3664 2 0 O3D0 1152 3664 2 0 O1F 1120 3568 0 0 O1F 1056 3568 0 0 O3CC 1152 3552 4 0 O3D2 1152 3552 2 0 O20 1152 3664 2 0 O30 992 3496 0 0 O20 1152 3184 2 0 O3D3 1008 3368 5 0 O3D4 1152 3152 2 0 O3D4 1152 3640 2 0 O30 608 3456 0 0 O3BE 688 3400 2 0 O3CB 752 3416 2 0 O3CC 640 3552 4 0 O3CD 624 3416 1 0 O45 736 3608 0 0 O30 736 3456 0 0 O3CD 768 3416 1 0 O3BE 752 3400 2 0 O30 736 3496 0 0 O3AC 704 3528 4 0 O30 704 3456 2 0 O30 704 3416 2 0 O3C2 752 3336 2 0 O45 672 3368 5 0 O3CE 752 3376 2 0 O1F 704 3280 2 0 O30 640 3448 7 0 O30 768 3448 7 0 O20 704 3184 2 0 O45 736 3336 0 0 O30 672 3496 0 0 O20 704 3664 2 0 O3CF 768 3184 2 0 O3D0 768 3184 2 0 O3D1 768 3280 2 0 O3D0 768 3280 2 0 O1F 768 3280 2 0 O45 672 3608 0 0 O3D1 768 3568 2 0 O3CF 768 3664 2 0 O3D0 768 3664 2 0 O1F 736 3568 0 0 O1F 672 3568 0 0 O3CC 768 3552 4 0 O3D2 768 3552 2 0 O20 768 3664 2 0 O30 608 3496 0 0 O20 768 3184 2 0 O3D3 624 3368 5 0 O3D4 768 3152 2 0 O3D4 768 3640 2 0 O30 864 3456 0 0 O3BE 944 3400 2 0 O3CB 1008 3416 2 0 O3CC 896 3552 4 0 O3CD 880 3416 1 0 O45 992 3608 0 0 O30 992 3456 0 0 O3CD 1024 3416 1 0 O3BE 1008 3400 2 0 O30 992 3496 0 0 O3AC 960 3528 4 0 O30 960 3456 2 0 O30 960 3416 2 0 O3C2 1008 3336 2 0 O45 928 3368 5 0 O3CE 1008 3376 2 0 O1F 960 3280 2 0 O30 896 3448 7 0 O30 1024 3448 7 0 O20 960 3184 2 0 O45 992 3336 0 0 O30 928 3496 0 0 O20 960 3664 2 0 O3CF 1024 3184 2 0 O3D0 1024 3184 2 0 O3D1 1024 3280 2 0 O3D0 1024 3280 2 0 O1F 1024 3280 2 0 O45 928 3608 0 0 O3D1 1024 3568 2 0 O3CF 1024 3664 2 0 O3D0 1024 3664 2 0 O1F 992 3568 0 0 O1F 928 3568 0 0 O3CC 1024 3552 4 0 O3D2 1024 3552 2 0 O20 1024 3664 2 0 O30 864 3496 0 0 O20 1024 3184 2 0 O3D3 880 3368 5 0 O3D4 1024 3152 2 0 O3D4 1024 3640 2 0 O30 736 3456 0 0 O3BE 816 3400 2 0 O3CB 880 3416 2 0 O3CC 768 3552 4 0 O3CD 752 3416 1 0 O45 864 3608 0 0 O30 864 3456 0 0 O3CD 896 3416 1 0 O3BE 880 3400 2 0 O30 864 3496 0 0 O3AC 832 3528 4 0 O30 832 3456 2 0 O30 832 3416 2 0 O3C2 880 3336 2 0 O45 800 3368 5 0 O3CE 880 3376 2 0 O1F 832 3280 2 0 O30 768 3448 7 0 O30 896 3448 7 0 O20 832 3184 2 0 O45 864 3336 0 0 O30 800 3496 0 0 O20 832 3664 2 0 O3CF 896 3184 2 0 O3D0 896 3184 2 0 O3D1 896 3280 2 0 O3D0 896 3280 2 0 O1F 896 3280 2 0 O45 800 3608 0 0 O3D1 896 3568 2 0 O3CF 896 3664 2 0 O3D0 896 3664 2 0 O1F 864 3568 0 0 O1F 800 3568 0 0 O3CC 896 3552 4 0 O3D2 896 3552 2 0 O20 896 3664 2 0 O30 736 3496 0 0 O20 896 3184 2 0 O3D3 752 3368 5 0 O3D4 896 3152 2 0 O3D4 896 3640 2 0 O30 480 3456 0 0 O3BE 560 3400 2 0 O3CB 624 3416 2 0 O3CC 512 3552 4 0 O3CD 496 3416 1 0 O45 608 3608 0 0 O30 608 3456 0 0 O3CD 640 3416 1 0 O3BE 624 3400 2 0 O30 608 3496 0 0 O3AC 576 3528 4 0 O30 576 3456 2 0 O30 576 3416 2 0 O3C2 624 3336 2 0 O45 544 3368 5 0 O3CE 624 3376 2 0 O1F 576 3280 2 0 O30 512 3448 7 0 O30 640 3448 7 0 O20 576 3184 2 0 O45 608 3336 0 0 O30 544 3496 0 0 O20 576 3664 2 0 O3CF 640 3184 2 0 O3D0 640 3184 2 0 O3D1 640 3280 2 0 O3D0 640 3280 2 0 O1F 640 3280 2 0 O45 544 3608 0 0 O3D1 640 3568 2 0 O3CF 640 3664 2 0 O3D0 640 3664 2 0 O1F 608 3568 0 0 O1F 544 3568 0 0 O3CC 640 3552 4 0 O3D2 640 3552 2 0 O20 640 3664 2 0 O30 480 3496 0 0 O20 640 3184 2 0 O3D3 496 3368 5 0 O3D4 640 3152 2 0 O3D4 640 3640 2 0 O3D5 A9 312 208 A6 AB 0 1600 3416 2 0 O20 1536 3312 5 0 O20 1536 3448 5 0 O20 1440 3696 5 0 O1F 1440 3448 5 0 O3D6 A9 32 88 A6 A14 0 1440 3368 5 0 O3D7 A9 32 304 A6 AA 0 1440 3584 5 0 O1F 1440 3312 5 0 O1F 1440 3368 5 0 O1F 1440 3600 5 0 O20 1536 3696 5 0 O3D8 A9 32 168 A6 A14 0 1440 3584 5 0 O3D9 A9 32 120 A6 A1E 0 1496 3376 2 0 O3DA A9 32 40 A6 A13 0 1568 3216 7 0 O1F 1440 3488 5 0 O1F 1440 3528 5 0 O3DB A9 32 256 A6 A1E 0 1480 3152 0 0 O20 1520 3216 5 0 O20 1440 3216 5 0 O3DC A9 32 472 A6 A13 0 1536 3688 5 0 O3DD A9 32 504 A6 AA 0 1536 3688 5 0 O20 1536 3600 5 0 O20 1536 3528 5 0 O20 1536 3488 5 0 O20 1536 3368 5 0 O3D0 1536 3696 7 0 O3CF 1536 3696 7 0 O3A9 1472 3600 7 0 O3DE A9 32 96 A6 A14 0 1472 3600 7 0 O3DE 1472 3312 7 0 O3A9 1472 3312 7 0 O3DF A9 32 192 A6 AA 0 1568 3216 7 0 O3E0 A9 32 96 A6 A13 0 1472 3216 7 0 O3E1 A9 88 576 A6 AF 0 1512 3728 5 0 O3E2 A9 88 208 A6 AF 0 1600 3240 7 0 O3E3 A9 88 176 A6 AF 0 1568 3728 7 0 O30 352 3456 0 0 O3BE 432 3400 2 0 O3CB 496 3416 2 0 O3CC 384 3552 4 0 O3CD 368 3416 1 0 O45 480 3608 0 0 O30 480 3456 0 0 O3CD 512 3416 1 0 O3BE 496 3400 2 0 O30 480 3496 0 0 O3AC 448 3528 4 0 O30 448 3456 2 0 O30 448 3416 2 0 O3C2 496 3336 2 0 O45 416 3368 5 0 O3CE 496 3376 2 0 O1F 448 3280 2 0 O30 384 3448 7 0 O30 512 3448 7 0 O20 448 3184 2 0 O45 480 3336 0 0 O30 416 3496 0 0 O20 448 3664 2 0 O3CF 512 3184 2 0 O3D0 512 3184 2 0 O3D1 512 3280 2 0 O3D0 512 3280 2 0 O1F 512 3280 2 0 O45 416 3608 0 0 O3D1 512 3568 2 0 O3CF 512 3664 2 0 O3D0 512 3664 2 0 O1F 480 3568 0 0 O1F 416 3568 0 0 O3CC 512 3552 4 0 O3D2 512 3552 2 0 O20 512 3664 2 0 O30 352 3496 0 0 O20 512 3184 2 0 O3D3 368 3368 5 0 O3D4 512 3152 2 0 O3D4 512 3640 2 0 O3A1 352 3568 0 0 O3E4 A9 32 80 A6 A14 0 288 3600 6 0 O3E5 A9 32 80 A6 AA 0 288 3600 6 0 O1F 384 3600 4 0 O3E6 A9 56 112 A6 AB 0 96 3248 0 0 O3E7 A2C A6 56 56 A6 AB 0 96 3304 0 0 O45 352 3608 0 0 O20 384 3696 4 0 O20 384 3216 4 0 O1F 384 3312 4 0 O20 64 3488 4 0 O20 216 3488 4 0 O20 216 3544 4 0 O1F 320 3488 4 0 O1F 320 3528 4 0 O1F 320 3600 4 0 O3E7 96 3248 0 0 O3E 96 3600 0 0 O1F 320 3448 4 0 O20 216 3216 4 0 O20 216 3368 4 0 O20 216 3448 4 0 O20 216 3696 4 0 O20 216 3600 4 0 O20 64 3312 4 0 O20 64 3600 4 0 O20 64 3528 4 0 O20 64 3696 4 0 O20 64 3368 4 0 O20 64 3216 4 0 O1F 320 3368 4 0 O3E 96 3520 0 0 O3E8 A9 32 472 A6 AA 0 216 3688 4 0 O3E9 A9 32 480 A6 A13 0 216 3696 4 0 O20 216 3312 4 0 O3EA A9 32 336 A6 AA 0 32 3216 6 0 O3EB A9 32 168 A6 A13 0 32 3216 6 0 O20 136 3216 4 0 O20 136 3696 4 0 O3EC A9 32 536 A6 AA 0 64 3688 4 0 O3ED A9 32 504 A6 A13 0 64 3688 4 0 O20 64 3448 4 0 O3EE A9 32 304 A6 A14 0 320 3584 4 0 O3D7 320 3584 4 0 O3E4 288 3312 6 0 O3E5 288 3312 6 0 O1F 320 3312 4 0 O3EB 200 3216 6 0 O20 320 3216 4 0 O3EA 32 3696 6 0 O3EF A9 32 336 A6 A13 0 32 3696 6 0 O20 320 3696 4 0 O3E 120 3480 0 0 O3F0 A9 136 296 A6 AB 0 384 3232 2 0 O3F1 A23 56 384 A6 A1D 0 96 3248 0 0 O3F2 A9 56 384 A6 AA 0 96 3248 0 0 O3E 120 3560 0 0 O3E 120 3400 0 0 O3E 96 3440 0 0 O3F3 A9 88 128 A6 AF 0 240 3240 6 0 O3F4 A9 312 384 A6 AB 0 384 3416 2 0 O3F3 240 3728 6 0 O3F5 A9 240 576 A6 AF 0 240 3728 4 0 O3E 376 464 0 0 O3E 248 424 0 0 O3F6 A2 0 0 304 288 1 O3F7 A9 304 288 A6 AB 0 0 0 0 0 0 0 304 288 R9A7 "met2Ptr" 1043449628 0 0 2 A2D a A2D A17 i 83688 496 2864 0 0 O3F8 A11 R9A8 "fromChip" R9A6 2 0 1232 12 0 1 A12 i 171 O3E 312 528 0 0 O3E 312 488 0 0 O3E 312 448 0 0 O3F9 A9 32 184 A6 AA 0 312 456 0 0 O3E 248 464 0 0 O30 296 216 0 0 O30 296 136 0 0 O3FA A23 16 144 A6 A1D 0 536 432 1 0 O3FB A9 32 40 A6 AB 0 1248 0 0 0 O45 1248 8 0 0 O3FB 232 0 0 0 O45 232 8 0 0 O3FC A9 32 40 A6 AA 0 1248 0 0 2 A12 i 171 A16 lor 1 R9A8 O30 232 168 0 0 O30 232 216 0 0 O30 232 256 0 0 O30 232 128 0 0 O3E 408 424 1 0 O3E 536 440 1 0 O3E 536 488 1 0 O3E 472 480 1 0 O3E 408 504 1 0 O3AA 472 576 1 0 O45 552 608 1 0 O45 408 608 1 0 O45 280 608 1 0 O3AA 344 576 1 0 O3FD A23 16 192 A6 A1D 0 200 384 1 0 O3E 536 536 1 0 O3E 472 528 1 0 O3E 408 544 1 0 O3E 280 544 1 0 O3E 216 504 1 0 O3FE A9 16 40 A6 A1E 0 368 336 1 0 O3FF A11 R1 R9A6 2 0 192 676 0 1 A12 i 254 O400 A9 16 64 A6 A1E 0 1216 40 0 0 O32 912 280 0 0 O3FE 1424 304 2 0 O401 A9 16 192 A6 A1E 0 1424 288 2 0 O32 1024 288 0 0 O3C8 1480 3088 0 0 O402 A9 32 96 A6 A1E 0 1576 3088 2 0 O32 1208 40 0 0 O403 A11 RA R24 4 0 60 2304 2 1 A12 i 98 O32 1544 3088 0 0 O404 A11 R9A9 "Pull" R24 4 0 1572 2024 2 1 A12 i 99 O405 A11 R1 R24 4 0 220 1184 2 1 A12 i 101 O3B8 1176 288 2 0 O406 A11 R9 R9A6 8 0 600 4256 0 1 A12 i 128 O3B3 880 456 0 1 A12 i 160 O407 A9 16 216 A6 A1E 0 1560 456 0 1 A12 i 192 O404 1572 1152 2 1 A12 i 100 O408 A11 R9AA "Push" R24 4 0 1508 1152 2 1 A12 i 111 O409 A9 32 1568 A6 AA 0 1544 1552 0 2 A12 i 99 A16 lor 1 R9A9 O40A A9 32 1600 A6 AA 0 32 1552 0 2 A12 i 98 A16 lor 1 RA O45 72 608 0 0 O45 24 608 0 0 O3AA 216 576 1 0 O3E 408 384 1 0 O3A7 328 128 4 0 O3E 184 464 0 0 O3E 184 424 0 0 O3E 184 384 0 0 O3F9 248 384 0 0 O3E 248 504 0 0 O3E 248 384 0 0 O3F9 376 384 0 0 O3E 472 440 1 0 O3D0 440 440 0 0 O40B A9 16 592 A6 A1E 0 496 80 1 0 O40C A1C A6 176 64 A6 A1D 0 456 416 3 0 O40D A9 240 96 A6 AB 0 1272 80 2 1 A12 i 217 O1 328 1880 0 2 A4 r R1 A5 A6 A7 O3F6 1104 2864 1 0 O40E A9 32 600 A6 A1E 0 1480 712 0 2 A12 i 111 A16 lor 1 R9AA O40F A9 32 640 A6 A1E 0 1544 672 0 2 A12 i 100 A16 lor 1 R9A9 O40F 192 672 0 2 A12 i 101 A16 lor 1 R1 O410 A9 16 304 A6 A1E 0 192 656 3 2 A12 i 254 A16 lor 1 R1 O4 1600 672 2 1 A12 i 103 O3 1600 672 2 2 A12 i 129 A16 lor 1 RA O411 A9 16 632 A6 A1E 0 1512 712 2 0 O412 A2 0 0 1152 512 6 O38E 768 256 0 0 O38E 768 0 0 0 O38E 384 0 0 0 O38E 384 256 0 0 O38E 0 256 0 0 O38E 0 0 0 0 0 0 1152 512 R9AB "viamid" 1036517376 0 0 2 A17 i 83685 A2D a A2D 296 776 0 0 O3 1600 3728 2 0 O4 1600 3728 2 2 A12 i 128 A16 lor 1 R9 O38D 32 3824 0 0 O3B1 536 336 1 0 O3B9 184 112 3 0 O3B9 456 80 3 0 O30 296 176 0 0 O413 A9 16 160 A6 A20 0 312 128 0 0 O30 408 104 1 0 O413 392 96 1 0 O414 A9 32 224 A6 AA 0 504 32 0 0 O413 184 128 1 0 O30 200 136 1 0 O3A7 168 128 5 0 O30 200 176 1 0 O30 200 216 1 0 O30 168 256 0 0 O414 168 64 0 0 O45 336 112 0 0 O3B9 248 112 3 0 O415 A9 32 352 A6 AA 0 264 0 1 2 A12 i 119 A16 lor 1 R9AC "toChip" O416 A9 32 104 A6 AA 0 280 320 1 1 A12 i 255 O45 336 64 0 0 O417 A9 16 256 A6 A1E 0 224 336 0 0 O418 A9 16 248 A6 A1E 0 432 344 1 0 O419 A9 112 248 A6 AA 0 296 40 0 0 O3E 632 456 0 0 O45 696 608 0 0 O3E 632 416 0 0 O3E 632 496 0 0 O3E 632 536 0 0 O45 760 608 0 0 O45 824 608 0 0 O30 728 104 1 0 O3E 696 352 0 0 O3E 696 408 0 0 O3E 696 456 0 0 O3E 696 504 0 0 O414 632 416 0 0 O3B2 984 336 2 0 O3B1 1144 352 2 0 O41A A9 16 128 A6 A20 0 1256 120 0 0 O414 1208 152 1 0 O3E 1176 352 0 0 O30 1240 168 0 0 O30 1240 120 0 0 O30 1240 216 0 0 O45 1176 608 0 0 O3E 1240 512 0 0 O3E 1240 432 0 0 O3E 1240 392 0 0 O3E 1176 392 0 0 O3E 1176 432 0 0 O3E 1176 512 0 0 O3E 1176 552 0 0 O41B A23 16 208 A6 A1D 0 1256 376 0 0 O3CA 1240 376 0 0 O41C A9 32 200 A6 AA 0 1176 376 0 0 O41D A23 16 200 A6 A1D 0 1176 376 0 0 O3AA 1240 584 0 0 O30 1176 152 0 0 O30 1176 216 0 0 O3E 1176 472 0 0 O3E 1240 472 0 0 O41A 1176 120 0 0 O3D0 1304 96 2 0 O3A9 1240 120 0 0 O3E 1240 352 0 0 O3B2 1256 336 2 0 O41E A9 16 496 A6 A1E 0 1216 104 0 0 O3B4 1256 104 2 0 O3B4 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O3C1 560 1312 1 0 O3C1 688 1312 1 0 O30 624 1448 7 0 O3BE 672 1504 7 0 O3AC 624 1376 1 0 O3C2 672 1344 7 0 O3C2 672 1520 2 0 O3BC 800 1320 2 0 O3BD 800 1544 7 0 O3BE 736 1504 7 0 O3BC 800 1544 7 0 O30 752 1408 7 0 O30 656 1376 0 0 O30 784 1376 0 0 O30 752 1488 7 0 O3BF 752 1416 1 0 O30 816 1456 2 0 O30 688 1456 2 0 O30 656 1416 0 0 O3C0 672 1488 4 0 O30 784 1416 0 0 O3C0 816 1488 4 0 O3C1 688 1312 1 0 O3C1 816 1312 1 0 O30 752 1448 7 0 O3BE 800 1504 7 0 O3AC 752 1376 1 0 O3C2 800 1344 7 0 O3C2 800 1520 2 0 O3BC 416 1320 2 0 O3BD 416 1544 7 0 O3BE 352 1504 7 0 O3BC 416 1544 7 0 O30 368 1408 7 0 O30 272 1376 0 0 O30 400 1376 0 0 O30 368 1488 7 0 O3BF 368 1416 1 0 O30 432 1456 2 0 O30 304 1456 2 0 O30 272 1416 0 0 O3C0 288 1488 4 0 O30 400 1416 0 0 O3C0 432 1488 4 0 O3C1 304 1312 1 0 O3C1 432 1312 1 0 O30 368 1448 7 0 O3BE 416 1504 7 0 O3AC 368 1376 1 0 O3C2 416 1344 7 0 O3C2 416 1520 2 0 O3C4 0 1312 0 0 O3C5 288 1312 2 0 O3C6 1440 1320 3 0 O32 192 1344 0 0 O3C7 1600 1312 2 0 O3C8 192 1312 0 0 O3C6 1440 1496 3 0 O32 1544 1520 0 0 O3C9 1544 1312 0 0 O3A9 288 1520 2 0 O3CA 192 1344 0 0 O3BC 544 1320 2 0 O3BD 544 1544 7 0 O3BE 480 1504 7 0 O3BC 544 1544 7 0 O30 496 1408 7 0 O30 400 1376 0 0 O30 528 1376 0 0 O30 496 1488 7 0 O3BF 496 1416 1 0 O30 560 1456 2 0 O30 432 1456 2 0 O30 400 1416 0 0 O3C0 416 1488 4 0 O30 528 1416 0 0 O3C0 560 1488 4 0 O3C1 432 1312 1 0 O3C1 560 1312 1 0 O30 496 1448 7 0 O3BE 544 1504 7 0 O3AC 496 1376 1 0 O3C2 544 1344 7 0 O3C2 544 1520 2 0 O3BC 928 1320 2 0 O3BD 928 1544 7 0 O3BE 864 1504 7 0 O3BC 928 1544 7 0 O30 880 1408 7 0 O30 784 1376 0 0 O30 912 1376 0 0 O30 880 1488 7 0 O3BF 880 1416 1 0 O30 944 1456 2 0 O30 816 1456 2 0 O30 784 1416 0 0 O3C0 800 1488 4 0 O30 912 1416 0 0 O3C0 944 1488 4 0 O3C1 816 1312 1 0 O3C1 944 1312 1 0 O30 880 1448 7 0 O3BE 928 1504 7 0 O3AC 880 1376 1 0 O3C2 928 1344 7 0 O3C2 928 1520 2 0 O3BC 1056 1320 2 0 O3BD 1056 1544 7 0 O3BE 992 1504 7 0 O3BC 1056 1544 7 0 O30 1008 1408 7 0 O30 912 1376 0 0 O30 1040 1376 0 0 O30 1008 1488 7 0 O3BF 1008 1416 1 0 O30 1072 1456 2 0 O30 944 1456 2 0 O30 912 1416 0 0 O3C0 928 1488 4 0 O30 1040 1416 0 0 O3C0 1072 1488 4 0 O3C1 944 1312 1 0 O3C1 1072 1312 1 0 O30 1008 1448 7 0 O3BE 1056 1504 7 0 O3AC 1008 1376 1 0 O3C2 1056 1344 7 0 O3C2 1056 1520 2 0 O3BC 1184 1320 2 0 O3BD 1184 1544 7 0 O3BE 1120 1504 7 0 O3BC 1184 1544 7 0 O30 1136 1408 7 0 O30 1040 1376 0 0 O30 1168 1376 0 0 O30 1136 1488 7 0 O3BF 1136 1416 1 0 O30 1200 1456 2 0 O30 1072 1456 2 0 O30 1040 1416 0 0 O3C0 1056 1488 4 0 O30 1168 1416 0 0 O3C0 1200 1488 4 0 O3C1 1072 1312 1 0 O3C1 1200 1312 1 0 O30 1136 1448 7 0 O3BE 1184 1504 7 0 O3AC 1136 1376 1 0 O3C2 1184 1344 7 0 O3C2 1184 1520 2 0 O3BC 1312 1320 2 0 O3BD 1312 1544 7 0 O3BE 1248 1504 7 0 O3BC 1312 1544 7 0 O30 1264 1408 7 0 O30 1168 1376 0 0 O30 1296 1376 0 0 O30 1264 1488 7 0 O3BF 1264 1416 1 0 O30 1328 1456 2 0 O30 1200 1456 2 0 O30 1168 1416 0 0 O3C0 1184 1488 4 0 O30 1296 1416 0 0 O3C0 1328 1488 4 0 O3C1 1200 1312 1 0 O3C1 1328 1312 1 0 O30 1264 1448 7 0 O3BE 1312 1504 7 0 O3AC 1264 1376 1 0 O3C2 1312 1344 7 0 O3C2 1312 1520 2 0 O30 1248 3456 0 0 O3BE 1328 3400 2 0 O3CB 1392 3416 2 0 O3CC 1280 3552 4 0 O3CD 1264 3416 1 0 O45 1376 3608 0 0 O30 1376 3456 0 0 O3CD 1408 3416 1 0 O3BE 1392 3400 2 0 O30 1376 3496 0 0 O3AC 1344 3528 4 0 O30 1344 3456 2 0 O30 1344 3416 2 0 O3C2 1392 3336 2 0 O45 1312 3368 5 0 O3CE 1392 3376 2 0 O1F 1344 3280 2 0 O30 1280 3448 7 0 O30 1408 3448 7 0 O20 1344 3184 2 0 O45 1376 3336 0 0 O30 1312 3496 0 0 O20 1344 3664 2 0 O3CF 1408 3184 2 0 O3D0 1408 3184 2 0 O3D1 1408 3280 2 0 O3D0 1408 3280 2 0 O1F 1408 3280 2 0 O45 1312 3608 0 0 O3D1 1408 3568 2 0 O3CF 1408 3664 2 0 O3D0 1408 3664 2 0 O1F 1376 3568 0 0 O1F 1312 3568 0 0 O3CC 1408 3552 4 0 O3D2 1408 3552 2 0 O20 1408 3664 2 0 O30 1248 3496 0 0 O20 1408 3184 2 0 O3D3 1264 3368 5 0 O3D4 1408 3152 2 0 O3D4 1408 3640 2 0 O30 1120 3456 0 0 O3BE 1200 3400 2 0 O3CB 1264 3416 2 0 O3CC 1152 3552 4 0 O3CD 1136 3416 1 0 O45 1248 3608 0 0 O30 1248 3456 0 0 O3CD 1280 3416 1 0 O3BE 1264 3400 2 0 O30 1248 3496 0 0 O3AC 1216 3528 4 0 O30 1216 3456 2 0 O30 1216 3416 2 0 O3C2 1264 3336 2 0 O45 1184 3368 5 0 O3CE 1264 3376 2 0 O1F 1216 3280 2 0 O30 1152 3448 7 0 O30 1280 3448 7 0 O20 1216 3184 2 0 O45 1248 3336 0 0 O30 1184 3496 0 0 O20 1216 3664 2 0 O3CF 1280 3184 2 0 O3D0 1280 3184 2 0 O3D1 1280 3280 2 0 O3D0 1280 3280 2 0 O1F 1280 3280 2 0 O45 1184 3608 0 0 O3D1 1280 3568 2 0 O3CF 1280 3664 2 0 O3D0 1280 3664 2 0 O1F 1248 3568 0 0 O1F 1184 3568 0 0 O3CC 1280 3552 4 0 O3D2 1280 3552 2 0 O20 1280 3664 2 0 O30 1120 3496 0 0 O20 1280 3184 2 0 O3D3 1136 3368 5 0 O3D4 1280 3152 2 0 O3D4 1280 3640 2 0 O30 992 3456 0 0 O3BE 1072 3400 2 0 O3CB 1136 3416 2 0 O3CC 1024 3552 4 0 O3CD 1008 3416 1 0 O45 1120 3608 0 0 O30 1120 3456 0 0 O3CD 1152 3416 1 0 O3BE 1136 3400 2 0 O30 1120 3496 0 0 O3AC 1088 3528 4 0 O30 1088 3456 2 0 O30 1088 3416 2 0 O3C2 1136 3336 2 0 O45 1056 3368 5 0 O3CE 1136 3376 2 0 O1F 1088 3280 2 0 O30 1024 3448 7 0 O30 1152 3448 7 0 O20 1088 3184 2 0 O45 1120 3336 0 0 O30 1056 3496 0 0 O20 1088 3664 2 0 O3CF 1152 3184 2 0 O3D0 1152 3184 2 0 O3D1 1152 3280 2 0 O3D0 1152 3280 2 0 O1F 1152 3280 2 0 O45 1056 3608 0 0 O3D1 1152 3568 2 0 O3CF 1152 3664 2 0 O3D0 1152 3664 2 0 O1F 1120 3568 0 0 O1F 1056 3568 0 0 O3CC 1152 3552 4 0 O3D2 1152 3552 2 0 O20 1152 3664 2 0 O30 992 3496 0 0 O20 1152 3184 2 0 O3D3 1008 3368 5 0 O3D4 1152 3152 2 0 O3D4 1152 3640 2 0 O30 608 3456 0 0 O3BE 688 3400 2 0 O3CB 752 3416 2 0 O3CC 640 3552 4 0 O3CD 624 3416 1 0 O45 736 3608 0 0 O30 736 3456 0 0 O3CD 768 3416 1 0 O3BE 752 3400 2 0 O30 736 3496 0 0 O3AC 704 3528 4 0 O30 704 3456 2 0 O30 704 3416 2 0 O3C2 752 3336 2 0 O45 672 3368 5 0 O3CE 752 3376 2 0 O1F 704 3280 2 0 O30 640 3448 7 0 O30 768 3448 7 0 O20 704 3184 2 0 O45 736 3336 0 0 O30 672 3496 0 0 O20 704 3664 2 0 O3CF 768 3184 2 0 O3D0 768 3184 2 0 O3D1 768 3280 2 0 O3D0 768 3280 2 0 O1F 768 3280 2 0 O45 672 3608 0 0 O3D1 768 3568 2 0 O3CF 768 3664 2 0 O3D0 768 3664 2 0 O1F 736 3568 0 0 O1F 672 3568 0 0 O3CC 768 3552 4 0 O3D2 768 3552 2 0 O20 768 3664 2 0 O30 608 3496 0 0 O20 768 3184 2 0 O3D3 624 3368 5 0 O3D4 768 3152 2 0 O3D4 768 3640 2 0 O30 864 3456 0 0 O3BE 944 3400 2 0 O3CB 1008 3416 2 0 O3CC 896 3552 4 0 O3CD 880 3416 1 0 O45 992 3608 0 0 O30 992 3456 0 0 O3CD 1024 3416 1 0 O3BE 1008 3400 2 0 O30 992 3496 0 0 O3AC 960 3528 4 0 O30 960 3456 2 0 O30 960 3416 2 0 O3C2 1008 3336 2 0 O45 928 3368 5 0 O3CE 1008 3376 2 0 O1F 960 3280 2 0 O30 896 3448 7 0 O30 1024 3448 7 0 O20 960 3184 2 0 O45 992 3336 0 0 O30 928 3496 0 0 O20 960 3664 2 0 O3CF 1024 3184 2 0 O3D0 1024 3184 2 0 O3D1 1024 3280 2 0 O3D0 1024 3280 2 0 O1F 1024 3280 2 0 O45 928 3608 0 0 O3D1 1024 3568 2 0 O3CF 1024 3664 2 0 O3D0 1024 3664 2 0 O1F 992 3568 0 0 O1F 928 3568 0 0 O3CC 1024 3552 4 0 O3D2 1024 3552 2 0 O20 1024 3664 2 0 O30 864 3496 0 0 O20 1024 3184 2 0 O3D3 880 3368 5 0 O3D4 1024 3152 2 0 O3D4 1024 3640 2 0 O30 736 3456 0 0 O3BE 816 3400 2 0 O3CB 880 3416 2 0 O3CC 768 3552 4 0 O3CD 752 3416 1 0 O45 864 3608 0 0 O30 864 3456 0 0 O3CD 896 3416 1 0 O3BE 880 3400 2 0 O30 864 3496 0 0 O3AC 832 3528 4 0 O30 832 3456 2 0 O30 832 3416 2 0 O3C2 880 3336 2 0 O45 800 3368 5 0 O3CE 880 3376 2 0 O1F 832 3280 2 0 O30 768 3448 7 0 O30 896 3448 7 0 O20 832 3184 2 0 O45 864 3336 0 0 O30 800 3496 0 0 O20 832 3664 2 0 O3CF 896 3184 2 0 O3D0 896 3184 2 0 O3D1 896 3280 2 0 O3D0 896 3280 2 0 O1F 896 3280 2 0 O45 800 3608 0 0 O3D1 896 3568 2 0 O3CF 896 3664 2 0 O3D0 896 3664 2 0 O1F 864 3568 0 0 O1F 800 3568 0 0 O3CC 896 3552 4 0 O3D2 896 3552 2 0 O20 896 3664 2 0 O30 736 3496 0 0 O20 896 3184 2 0 O3D3 752 3368 5 0 O3D4 896 3152 2 0 O3D4 896 3640 2 0 O30 480 3456 0 0 O3BE 560 3400 2 0 O3CB 624 3416 2 0 O3CC 512 3552 4 0 O3CD 496 3416 1 0 O45 608 3608 0 0 O30 608 3456 0 0 O3CD 640 3416 1 0 O3BE 624 3400 2 0 O30 608 3496 0 0 O3AC 576 3528 4 0 O30 576 3456 2 0 O30 576 3416 2 0 O3C2 624 3336 2 0 O45 544 3368 5 0 O3CE 624 3376 2 0 O1F 576 3280 2 0 O30 512 3448 7 0 O30 640 3448 7 0 O20 576 3184 2 0 O45 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1512 3728 5 0 O3E2 1600 3240 7 0 O3E3 1568 3728 7 0 O30 352 3456 0 0 O3BE 432 3400 2 0 O3CB 496 3416 2 0 O3CC 384 3552 4 0 O3CD 368 3416 1 0 O45 480 3608 0 0 O30 480 3456 0 0 O3CD 512 3416 1 0 O3BE 496 3400 2 0 O30 480 3496 0 0 O3AC 448 3528 4 0 O30 448 3456 2 0 O30 448 3416 2 0 O3C2 496 3336 2 0 O45 416 3368 5 0 O3CE 496 3376 2 0 O1F 448 3280 2 0 O30 384 3448 7 0 O30 512 3448 7 0 O20 448 3184 2 0 O45 480 3336 0 0 O30 416 3496 0 0 O20 448 3664 2 0 O3CF 512 3184 2 0 O3D0 512 3184 2 0 O3D1 512 3280 2 0 O3D0 512 3280 2 0 O1F 512 3280 2 0 O45 416 3608 0 0 O3D1 512 3568 2 0 O3CF 512 3664 2 0 O3D0 512 3664 2 0 O1F 480 3568 0 0 O1F 416 3568 0 0 O3CC 512 3552 4 0 O3D2 512 3552 2 0 O20 512 3664 2 0 O30 352 3496 0 0 O20 512 3184 2 0 O3D3 368 3368 5 0 O3D4 512 3152 2 0 O3D4 512 3640 2 0 O3A1 352 3568 0 0 O3E4 288 3600 6 0 O3E5 288 3600 6 0 O1F 384 3600 4 0 O3E6 96 3248 0 0 O3E7 96 3304 0 0 O45 352 3608 0 0 O20 384 3696 4 0 O20 384 3216 4 0 O1F 384 3312 4 0 O20 64 3488 4 0 O20 216 3488 4 0 O20 216 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368 3 0 O3D0 248 384 3 0 O426 264 368 3 0 O426 328 368 3 0 O426 392 368 3 0 O427 536 344 2 0 O428 712 360 0 0 O429 1544 608 2 0 O45 568 608 0 0 O3AA 664 584 1 0 O3B2 648 336 3 0 O42A 1600 352 2 2 A12 i 121 A16 lor 1 RC O30 632 120 0 0 O3A7 1032 152 6 0 O3FB 664 0 0 0 O32 664 48 0 0 O45 664 8 0 0 O3E5 664 0 0 2 A12 i 158 A16 lor 1 R9AD O42B 656 4 0 1 A12 i 158 O42C 880 288 2 0 O3A9 664 120 1 0 O45 592 176 0 0 O45 592 120 0 0 O42D 632 216 4 0 O42E 672 72 0 0 O30 632 168 0 0 O3C0 648 104 1 0 O42F 696 104 0 0 O430 728 104 1 0 O431 648 88 3 0 O30 696 200 0 0 O30 728 152 1 0 O432 1600 72 2 2 A12 i 213 A16 lor 1 RB O471 A9 32 280 A6 AA 0 264 72 1 1 A12 i 119 0 0 1600 4368 R2 1010535353 0 1 1 A17 i 83694 1 A18 a A19 9600 0 4 0 O433 11200 0 4 0 O46F 12800 0 4 0 O472 AD 0 0 1600 4368 O473 A2 0 0 1600 4368 57 O474 A9 40 320 A6 AB 0 1568 0 2 0 O45 1248 8 0 0 O45 1296 8 0 0 O45 1344 8 0 0 O45 1392 8 0 0 O45 1440 8 0 0 O45 1488 8 0 0 O45 1536 8 0 0 O45 1136 8 0 0 O45 1088 8 0 0 O45 1040 8 0 0 O45 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0 O3A7 1472 152 7 0 O480 1504 120 0 0 O3B4 1456 104 3 0 O32 1576 488 1 0 O32 1576 416 1 0 O32 1576 352 1 0 O32 1576 544 1 0 O3E 1536 344 1 0 O45 1536 608 1 0 O3E 1536 384 1 0 O3E 1536 424 1 0 O3E 1536 544 1 0 O41D 1536 368 1 0 O3AA 1472 576 1 0 O30 1536 120 1 0 O3E 1536 464 1 0 O41A 1536 120 1 0 O3E 1536 504 1 0 O30 1536 168 1 0 O30 1536 216 1 0 O3A7 1472 248 7 0 O3A7 1472 200 7 0 O481 A9 40 128 A6 A14 0 1400 120 0 0 O3CA 1472 376 1 0 O3AA 1472 432 7 0 O3FB 1480 0 0 0 O45 1480 8 0 0 O32 1320 288 0 0 O402 1576 3088 2 0 O403 60 2304 2 1 A12 i 98 O32 1544 3088 0 0 O404 1572 2024 2 1 A12 i 99 O482 A9 32 152 A6 AA 0 1504 288 2 0 O32 1480 48 0 0 O404 1572 1152 2 1 A12 i 100 O408 1500 1152 2 1 A12 i 111 O40A 32 1552 0 2 A12 i 98 A16 lor 1 RA O483 A9 32 48 A6 AA 0 1480 0 0 2 A12 i 171 A16 lor 1 R9A8 O3F8 1464 4 0 1 A12 i 171 O481 1400 120 1 0 O409 1544 1552 0 2 A12 i 99 A16 lor 1 R9A9 O3C8 1480 3088 0 0 O41B 1344 376 0 0 O38E 32 384 0 0 O479 32 96 0 0 O484 A9 56 464 A6 AA 0 1456 40 2 0 O391 1128 48 0 1 A12 i 120 O485 A9 352 368 A6 AF 0 1224 304 0 0 O39C 288 1840 0 0 O3F7 496 2864 0 0 O3A3 648 704 0 1 A12 i 129 O398 496 1552 0 2 A12 i 256 A16 lor 1 R1 O3A2 712 1664 0 1 A12 i 256 O3BB 1512 1312 1 0 O3BC 1440 1320 2 0 O3BD 1440 1544 7 0 O3BE 1376 1504 7 0 O3BC 1440 1544 7 0 O30 1392 1408 7 0 O30 1296 1376 0 0 O30 1424 1376 0 0 O30 1392 1488 7 0 O3BF 1392 1416 1 0 O30 1456 1456 2 0 O30 1328 1456 2 0 O30 1296 1416 0 0 O3C0 1312 1488 4 0 O30 1424 1416 0 0 O3C0 1456 1488 4 0 O3C1 1328 1312 1 0 O3C1 1456 1312 1 0 O30 1392 1448 7 0 O3BE 1440 1504 7 0 O3AC 1392 1376 1 0 O3C2 1440 1344 7 0 O3C2 1440 1520 2 0 O3C3 1600 1312 2 0 O3BC 672 1320 2 0 O3BD 672 1544 7 0 O3BE 608 1504 7 0 O3BC 672 1544 7 0 O30 624 1408 7 0 O30 528 1376 0 0 O30 656 1376 0 0 O30 624 1488 7 0 O3BF 624 1416 1 0 O30 688 1456 2 0 O30 560 1456 2 0 O30 528 1416 0 0 O3C0 544 1488 4 0 O30 656 1416 0 0 O3C0 688 1488 4 0 O3C1 560 1312 1 0 O3C1 688 1312 1 0 O30 624 1448 7 0 O3BE 672 1504 7 0 O3AC 624 1376 1 0 O3C2 672 1344 7 0 O3C2 672 1520 2 0 O3BC 800 1320 2 0 O3BD 800 1544 7 0 O3BE 736 1504 7 0 O3BC 800 1544 7 0 O30 752 1408 7 0 O30 656 1376 0 0 O30 784 1376 0 0 O30 752 1488 7 0 O3BF 752 1416 1 0 O30 816 1456 2 0 O30 688 1456 2 0 O30 656 1416 0 0 O3C0 672 1488 4 0 O30 784 1416 0 0 O3C0 816 1488 4 0 O3C1 688 1312 1 0 O3C1 816 1312 1 0 O30 752 1448 7 0 O3BE 800 1504 7 0 O3AC 752 1376 1 0 O3C2 800 1344 7 0 O3C2 800 1520 2 0 O3BC 416 1320 2 0 O3BD 416 1544 7 0 O3BE 352 1504 7 0 O3BC 416 1544 7 0 O30 368 1408 7 0 O30 272 1376 0 0 O30 400 1376 0 0 O30 368 1488 7 0 O3BF 368 1416 1 0 O30 432 1456 2 0 O30 304 1456 2 0 O30 272 1416 0 0 O3C0 288 1488 4 0 O30 400 1416 0 0 O3C0 432 1488 4 0 O3C1 304 1312 1 0 O3C1 432 1312 1 0 O30 368 1448 7 0 O3BE 416 1504 7 0 O3AC 368 1376 1 0 O3C2 416 1344 7 0 O3C2 416 1520 2 0 O3C4 0 1312 0 0 O3C5 288 1312 2 0 O3C6 1440 1320 3 0 O32 192 1344 0 0 O3C7 1600 1312 2 0 O3C8 192 1312 0 0 O3C6 1440 1496 3 0 O32 1544 1520 0 0 O3C9 1544 1312 0 0 O3A9 288 1520 2 0 O3CA 192 1344 0 0 O3BC 544 1320 2 0 O3BD 544 1544 7 0 O3BE 480 1504 7 0 O3BC 544 1544 7 0 O30 496 1408 7 0 O30 400 1376 0 0 O30 528 1376 0 0 O30 496 1488 7 0 O3BF 496 1416 1 0 O30 560 1456 2 0 O30 432 1456 2 0 O30 400 1416 0 0 O3C0 416 1488 4 0 O30 528 1416 0 0 O3C0 560 1488 4 0 O3C1 432 1312 1 0 O3C1 560 1312 1 0 O30 496 1448 7 0 O3BE 544 1504 7 0 O3AC 496 1376 1 0 O3C2 544 1344 7 0 O3C2 544 1520 2 0 O3BC 928 1320 2 0 O3BD 928 1544 7 0 O3BE 864 1504 7 0 O3BC 928 1544 7 0 O30 880 1408 7 0 O30 784 1376 0 0 O30 912 1376 0 0 O30 880 1488 7 0 O3BF 880 1416 1 0 O30 944 1456 2 0 O30 816 1456 2 0 O30 784 1416 0 0 O3C0 800 1488 4 0 O30 912 1416 0 0 O3C0 944 1488 4 0 O3C1 816 1312 1 0 O3C1 944 1312 1 0 O30 880 1448 7 0 O3BE 928 1504 7 0 O3AC 880 1376 1 0 O3C2 928 1344 7 0 O3C2 928 1520 2 0 O3BC 1056 1320 2 0 O3BD 1056 1544 7 0 O3BE 992 1504 7 0 O3BC 1056 1544 7 0 O30 1008 1408 7 0 O30 912 1376 0 0 O30 1040 1376 0 0 O30 1008 1488 7 0 O3BF 1008 1416 1 0 O30 1072 1456 2 0 O30 944 1456 2 0 O30 912 1416 0 0 O3C0 928 1488 4 0 O30 1040 1416 0 0 O3C0 1072 1488 4 0 O3C1 944 1312 1 0 O3C1 1072 1312 1 0 O30 1008 1448 7 0 O3BE 1056 1504 7 0 O3AC 1008 1376 1 0 O3C2 1056 1344 7 0 O3C2 1056 1520 2 0 O3BC 1184 1320 2 0 O3BD 1184 1544 7 0 O3BE 1120 1504 7 0 O3BC 1184 1544 7 0 O30 1136 1408 7 0 O30 1040 1376 0 0 O30 1168 1376 0 0 O30 1136 1488 7 0 O3BF 1136 1416 1 0 O30 1200 1456 2 0 O30 1072 1456 2 0 O30 1040 1416 0 0 O3C0 1056 1488 4 0 O30 1168 1416 0 0 O3C0 1200 1488 4 0 O3C1 1072 1312 1 0 O3C1 1200 1312 1 0 O30 1136 1448 7 0 O3BE 1184 1504 7 0 O3AC 1136 1376 1 0 O3C2 1184 1344 7 0 O3C2 1184 1520 2 0 O3BC 1312 1320 2 0 O3BD 1312 1544 7 0 O3BE 1248 1504 7 0 O3BC 1312 1544 7 0 O30 1264 1408 7 0 O30 1168 1376 0 0 O30 1296 1376 0 0 O30 1264 1488 7 0 O3BF 1264 1416 1 0 O30 1328 1456 2 0 O30 1200 1456 2 0 O30 1168 1416 0 0 O3C0 1184 1488 4 0 O30 1296 1416 0 0 O3C0 1328 1488 4 0 O3C1 1200 1312 1 0 O3C1 1328 1312 1 0 O30 1264 1448 7 0 O3BE 1312 1504 7 0 O3AC 1264 1376 1 0 O3C2 1312 1344 7 0 O3C2 1312 1520 2 0 O486 A9 32 960 A6 A1E 0 1544 352 0 2 A12 i 100 A16 lor 1 R9A9 O487 A9 32 624 A6 A1E 0 1480 688 0 2 A12 i 111 A16 lor 1 R9AA O30 1248 3456 0 0 O3BE 1328 3400 2 0 O3CB 1392 3416 2 0 O3CC 1280 3552 4 0 O3CD 1264 3416 1 0 O45 1376 3608 0 0 O30 1376 3456 0 0 O3CD 1408 3416 1 0 O3BE 1392 3400 2 0 O30 1376 3496 0 0 O3AC 1344 3528 4 0 O30 1344 3456 2 0 O30 1344 3416 2 0 O3C2 1392 3336 2 0 O45 1312 3368 5 0 O3CE 1392 3376 2 0 O1F 1344 3280 2 0 O30 1280 3448 7 0 O30 1408 3448 7 0 O20 1344 3184 2 0 O45 1376 3336 0 0 O30 1312 3496 0 0 O20 1344 3664 2 0 O3CF 1408 3184 2 0 O3D0 1408 3184 2 0 O3D1 1408 3280 2 0 O3D0 1408 3280 2 0 O1F 1408 3280 2 0 O45 1312 3608 0 0 O3D1 1408 3568 2 0 O3CF 1408 3664 2 0 O3D0 1408 3664 2 0 O1F 1376 3568 0 0 O1F 1312 3568 0 0 O3CC 1408 3552 4 0 O3D2 1408 3552 2 0 O20 1408 3664 2 0 O30 1248 3496 0 0 O20 1408 3184 2 0 O3D3 1264 3368 5 0 O3D4 1408 3152 2 0 O3D4 1408 3640 2 0 O30 1120 3456 0 0 O3BE 1200 3400 2 0 O3CB 1264 3416 2 0 O3CC 1152 3552 4 0 O3CD 1136 3416 1 0 O45 1248 3608 0 0 O30 1248 3456 0 0 O3CD 1280 3416 1 0 O3BE 1264 3400 2 0 O30 1248 3496 0 0 O3AC 1216 3528 4 0 O30 1216 3456 2 0 O30 1216 3416 2 0 O3C2 1264 3336 2 0 O45 1184 3368 5 0 O3CE 1264 3376 2 0 O1F 1216 3280 2 0 O30 1152 3448 7 0 O30 1280 3448 7 0 O20 1216 3184 2 0 O45 1248 3336 0 0 O30 1184 3496 0 0 O20 1216 3664 2 0 O3CF 1280 3184 2 0 O3D0 1280 3184 2 0 O3D1 1280 3280 2 0 O3D0 1280 3280 2 0 O1F 1280 3280 2 0 O45 1184 3608 0 0 O3D1 1280 3568 2 0 O3CF 1280 3664 2 0 O3D0 1280 3664 2 0 O1F 1248 3568 0 0 O1F 1184 3568 0 0 O3CC 1280 3552 4 0 O3D2 1280 3552 2 0 O20 1280 3664 2 0 O30 1120 3496 0 0 O20 1280 3184 2 0 O3D3 1136 3368 5 0 O3D4 1280 3152 2 0 O3D4 1280 3640 2 0 O30 992 3456 0 0 O3BE 1072 3400 2 0 O3CB 1136 3416 2 0 O3CC 1024 3552 4 0 O3CD 1008 3416 1 0 O45 1120 3608 0 0 O30 1120 3456 0 0 O3CD 1152 3416 1 0 O3BE 1136 3400 2 0 O30 1120 3496 0 0 O3AC 1088 3528 4 0 O30 1088 3456 2 0 O30 1088 3416 2 0 O3C2 1136 3336 2 0 O45 1056 3368 5 0 O3CE 1136 3376 2 0 O1F 1088 3280 2 0 O30 1024 3448 7 0 O30 1152 3448 7 0 O20 1088 3184 2 0 O45 1120 3336 0 0 O30 1056 3496 0 0 O20 1088 3664 2 0 O3CF 1152 3184 2 0 O3D0 1152 3184 2 0 O3D1 1152 3280 2 0 O3D0 1152 3280 2 0 O1F 1152 3280 2 0 O45 1056 3608 0 0 O3D1 1152 3568 2 0 O3CF 1152 3664 2 0 O3D0 1152 3664 2 0 O1F 1120 3568 0 0 O1F 1056 3568 0 0 O3CC 1152 3552 4 0 O3D2 1152 3552 2 0 O20 1152 3664 2 0 O30 992 3496 0 0 O20 1152 3184 2 0 O3D3 1008 3368 5 0 O3D4 1152 3152 2 0 O3D4 1152 3640 2 0 O30 608 3456 0 0 O3BE 688 3400 2 0 O3CB 752 3416 2 0 O3CC 640 3552 4 0 O3CD 624 3416 1 0 O45 736 3608 0 0 O30 736 3456 0 0 O3CD 768 3416 1 0 O3BE 752 3400 2 0 O30 736 3496 0 0 O3AC 704 3528 4 0 O30 704 3456 2 0 O30 704 3416 2 0 O3C2 752 3336 2 0 O45 672 3368 5 0 O3CE 752 3376 2 0 O1F 704 3280 2 0 O30 640 3448 7 0 O30 768 3448 7 0 O20 704 3184 2 0 O45 736 3336 0 0 O30 672 3496 0 0 O20 704 3664 2 0 O3CF 768 3184 2 0 O3D0 768 3184 2 0 O3D1 768 3280 2 0 O3D0 768 3280 2 0 O1F 768 3280 2 0 O45 672 3608 0 0 O3D1 768 3568 2 0 O3CF 768 3664 2 0 O3D0 768 3664 2 0 O1F 736 3568 0 0 O1F 672 3568 0 0 O3CC 768 3552 4 0 O3D2 768 3552 2 0 O20 768 3664 2 0 O30 608 3496 0 0 O20 768 3184 2 0 O3D3 624 3368 5 0 O3D4 768 3152 2 0 O3D4 768 3640 2 0 O30 864 3456 0 0 O3BE 944 3400 2 0 O3CB 1008 3416 2 0 O3CC 896 3552 4 0 O3CD 880 3416 1 0 O45 992 3608 0 0 O30 992 3456 0 0 O3CD 1024 3416 1 0 O3BE 1008 3400 2 0 O30 992 3496 0 0 O3AC 960 3528 4 0 O30 960 3456 2 0 O30 960 3416 2 0 O3C2 1008 3336 2 0 O45 928 3368 5 0 O3CE 1008 3376 2 0 O1F 960 3280 2 0 O30 896 3448 7 0 O30 1024 3448 7 0 O20 960 3184 2 0 O45 992 3336 0 0 O30 928 3496 0 0 O20 960 3664 2 0 O3CF 1024 3184 2 0 O3D0 1024 3184 2 0 O3D1 1024 3280 2 0 O3D0 1024 3280 2 0 O1F 1024 3280 2 0 O45 928 3608 0 0 O3D1 1024 3568 2 0 O3CF 1024 3664 2 0 O3D0 1024 3664 2 0 O1F 992 3568 0 0 O1F 928 3568 0 0 O3CC 1024 3552 4 0 O3D2 1024 3552 2 0 O20 1024 3664 2 0 O30 864 3496 0 0 O20 1024 3184 2 0 O3D3 880 3368 5 0 O3D4 1024 3152 2 0 O3D4 1024 3640 2 0 O30 736 3456 0 0 O3BE 816 3400 2 0 O3CB 880 3416 2 0 O3CC 768 3552 4 0 O3CD 752 3416 1 0 O45 864 3608 0 0 O30 864 3456 0 0 O3CD 896 3416 1 0 O3BE 880 3400 2 0 O30 864 3496 0 0 O3AC 832 3528 4 0 O30 832 3456 2 0 O30 832 3416 2 0 O3C2 880 3336 2 0 O45 800 3368 5 0 O3CE 880 3376 2 0 O1F 832 3280 2 0 O30 768 3448 7 0 O30 896 3448 7 0 O20 832 3184 2 0 O45 864 3336 0 0 O30 800 3496 0 0 O20 832 3664 2 0 O3CF 896 3184 2 0 O3D0 896 3184 2 0 O3D1 896 3280 2 0 O3D0 896 3280 2 0 O1F 896 3280 2 0 O45 800 3608 0 0 O3D1 896 3568 2 0 O3CF 896 3664 2 0 O3D0 896 3664 2 0 O1F 864 3568 0 0 O1F 800 3568 0 0 O3CC 896 3552 4 0 O3D2 896 3552 2 0 O20 896 3664 2 0 O30 736 3496 0 0 O20 896 3184 2 0 O3D3 752 3368 5 0 O3D4 896 3152 2 0 O3D4 896 3640 2 0 O30 480 3456 0 0 O3BE 560 3400 2 0 O3CB 624 3416 2 0 O3CC 512 3552 4 0 O3CD 496 3416 1 0 O45 608 3608 0 0 O30 608 3456 0 0 O3CD 640 3416 1 0 O3BE 624 3400 2 0 O30 608 3496 0 0 O3AC 576 3528 4 0 O30 576 3456 2 0 O30 576 3416 2 0 O3C2 624 3336 2 0 O45 544 3368 5 0 O3CE 624 3376 2 0 O1F 576 3280 2 0 O30 512 3448 7 0 O30 640 3448 7 0 O20 576 3184 2 0 O45 608 3336 0 0 O30 544 3496 0 0 O20 576 3664 2 0 O3CF 640 3184 2 0 O3D0 640 3184 2 0 O3D1 640 3280 2 0 O3D0 640 3280 2 0 O1F 640 3280 2 0 O45 544 3608 0 0 O3D1 640 3568 2 0 O3CF 640 3664 2 0 O3D0 640 3664 2 0 O1F 608 3568 0 0 O1F 544 3568 0 0 O3CC 640 3552 4 0 O3D2 640 3552 2 0 O20 640 3664 2 0 O30 480 3496 0 0 O20 640 3184 2 0 O3D3 496 3368 5 0 O3D4 640 3152 2 0 O3D4 640 3640 2 0 O3D5 1600 3416 2 0 O20 1536 3312 5 0 O20 1536 3448 5 0 O20 1440 3696 5 0 O1F 1440 3448 5 0 O3D6 1440 3368 5 0 O3D7 1440 3584 5 0 O1F 1440 3312 5 0 O1F 1440 3368 5 0 O1F 1440 3600 5 0 O20 1536 3696 5 0 O3D8 1440 3584 5 0 O3D9 1496 3376 2 0 O3DA 1568 3216 7 0 O1F 1440 3488 5 0 O1F 1440 3528 5 0 O3DB 1480 3152 0 0 O20 1520 3216 5 0 O20 1440 3216 5 0 O3DC 1536 3688 5 0 O3DD 1536 3688 5 0 O20 1536 3600 5 0 O20 1536 3528 5 0 O20 1536 3488 5 0 O20 1536 3368 5 0 O3D0 1536 3696 7 0 O3CF 1536 3696 7 0 O3A9 1472 3600 7 0 O3DE 1472 3600 7 0 O3DE 1472 3312 7 0 O3A9 1472 3312 7 0 O3DF 1568 3216 7 0 O3E0 1472 3216 7 0 O3E1 1512 3728 5 0 O3E2 1600 3240 7 0 O3E3 1568 3728 7 0 O30 352 3456 0 0 O3BE 432 3400 2 0 O3CB 496 3416 2 0 O3CC 384 3552 4 0 O3CD 368 3416 1 0 O45 480 3608 0 0 O30 480 3456 0 0 O3CD 512 3416 1 0 O3BE 496 3400 2 0 O30 480 3496 0 0 O3AC 448 3528 4 0 O30 448 3456 2 0 O30 448 3416 2 0 O3C2 496 3336 2 0 O45 416 3368 5 0 O3CE 496 3376 2 0 O1F 448 3280 2 0 O30 384 3448 7 0 O30 512 3448 7 0 O20 448 3184 2 0 O45 480 3336 0 0 O30 416 3496 0 0 O20 448 3664 2 0 O3CF 512 3184 2 0 O3D0 512 3184 2 0 O3D1 512 3280 2 0 O3D0 512 3280 2 0 O1F 512 3280 2 0 O45 416 3608 0 0 O3D1 512 3568 2 0 O3CF 512 3664 2 0 O3D0 512 3664 2 0 O1F 480 3568 0 0 O1F 416 3568 0 0 O3CC 512 3552 4 0 O3D2 512 3552 2 0 O20 512 3664 2 0 O30 352 3496 0 0 O20 512 3184 2 0 O3D3 368 3368 5 0 O3D4 512 3152 2 0 O3D4 512 3640 2 0 O3A1 352 3568 0 0 O3E4 288 3600 6 0 O3E5 288 3600 6 0 O1F 384 3600 4 0 O3E6 96 3248 0 0 O3E7 96 3304 0 0 O45 352 3608 0 0 O20 384 3696 4 0 O20 384 3216 4 0 O1F 384 3312 4 0 O20 64 3488 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A6 AA 0 -5672 33432 O4EA A9 2000 24 A6 AA 0 304 19268 5 2 AE r R40A A4 r R40A O4EB A9 32 15788 A6 AB 0 1968 18692 O45 1968 18688 O45 1968 34448 O4CE -5672 34448 O4A5 1968 18692 5 2 AE r R613 A4 r R613 O4EC A9 32 13012 A6 AB 0 496 23652 O45 496 23648 O45 496 36632 O4ED A9 6200 32 A6 AA 0 -5672 36632 O4EE A9 1808 24 A6 AA 0 496 23652 36 2 AE r RB A4 r RB O4BA 2160 6912 O4BB -5672 6912 O4BC 2160 6912 O4BA 2160 9888 O4BB -5672 9888 O4BC 2160 9888 O4BA 2160 13568 O4BB -5672 13568 O4BC 2160 13568 O4BA 2160 17824 O4BB -5672 17824 O4BC 2160 17824 O4BA 2160 22720 O4BB -5672 22720 O4BC 2160 22720 O4BA 2160 26528 O4BB -5672 26528 O4BC 2160 26528 O4BA 2160 30528 O4BB -5672 30528 O4BC 2160 30528 O4BA 2160 33888 O4BB -5672 33888 O4BC 2160 33888 O4BA 2160 37824 O4BB -5672 37824 O4BC 2160 37824 O4BA 2160 41568 O4BB -5672 41568 O4BC 2160 41568 O4BA 2160 3488 O4BB -5672 3488 O4BC 2160 3488 O4BA 2160 0 O4BB -5672 0 O4BC 2160 0 3 2 AE r R339 A4 r R339 O4EF A9 32 10844 A6 AB 0 1904 0 O45 1904 10816 O4CB 1904 10820 5 2 AE r R52B A4 r R52B O4F0 A9 32 19124 A6 AB 0 688 19140 O45 688 19136 O45 688 38232 O4F1 A9 6392 32 A6 AA 0 -5672 38232 O4F2 A9 1616 24 A6 AA 0 688 19140 3 2 AE r R503 A4 r R503 O4F3 A9 32 19996 A6 AB 0 1136 22404 O45 1136 22400 O4C5 1136 22404 5 2 AE r R509 A4 r R509 O4F4 A9 32 17196 A6 AB 0 752 22084 O45 752 22080 O45 752 39248 O4F5 A9 6456 32 A6 AA 0 -5672 39248 O4F6 A9 1552 24 A6 AA 0 752 22084 5 2 AE r R41E A4 r R41E O4F7 A9 32 11620 A6 AB 0 1584 3032 O45 1584 3032 O45 1584 14624 O4C8 1584 14628 O4F8 A9 7288 32 A6 AA 0 -5672 3032 3 2 AE r R4EF A4 r R4EF O4F9 A9 32 22300 A6 AB 0 1520 0 O45 1520 22272 O4FA A9 784 24 A6 AA 0 1520 22276 5 2 AE r R4F4 A4 r R4F4 O4FB A9 32 18140 A6 AB 0 1008 896 O45 1008 896 O45 1008 19008 O4A9 1008 19012 O4FC A9 6712 32 A6 AA 0 -5672 896 5 2 AE r R3FC A4 r R3FC O4FD A9 32 11116 A6 AB 0 1968 4048 O45 1968 4048 O45 1968 15136 O4A5 1968 15140 O4CE -5672 4048 5 2 AE r R5E2 A4 r R5E2 O4FE A9 32 19116 A6 AB 0 624 5648 O45 624 5648 O45 624 24736 O4D7 624 24740 O4D8 -5672 5648 5 2 AE r R424 A4 r R424 O4FF A9 32 6756 A6 AB 0 752 7832 O45 752 7832 O45 752 14560 O4F6 752 14564 O4F5 -5672 7832 5 2 AE r R322 A4 r R322 O500 A9 32 5932 A6 AB 0 1776 8848 O45 1776 8848 O45 1776 14752 O4A0 1776 14756 O501 A9 7480 32 A6 AA 0 -5672 8848 5 2 AE r R3FD A4 r R3FD O502 A9 32 8460 A6 AB 0 1712 10448 O45 1712 10448 O45 1712 18880 O503 A9 592 24 A6 AA 0 1712 18884 O504 A9 7416 32 A6 AA 0 -5672 10448 5 2 AE r R400 A4 r R400 O505 A9 32 6732 A6 AB 0 2096 12048 O45 2096 12048 O45 2096 18752 O4A7 2096 18756 O506 A9 7800 32 A6 AA 0 -5672 12048 5 2 AE r R4F8 A4 r R4F8 O507 A9 32 8652 A6 AB 0 2032 13712 O45 2032 13712 O45 2032 22336 O4BE 2032 22340 O4BF -5672 13712 5 2 AE r R348 A4 r R348 O508 A9 32 308 A6 AB 0 2096 10756 O45 2096 10752 O45 2096 11032 O506 -5672 11032 O4A7 2096 10756 5 2 AE r R4FA A4 r R4FA O509 A9 32 7372 A6 AB 0 560 15248 O45 560 15248 O45 560 22592 O4B0 560 22596 O4AF -5672 15248 5 2 AE r R4FD A4 r R4FD O50A A9 32 876 A6 AB 0 1520 22532 O45 1520 22528 O45 1520 23376 O50B A9 7224 32 A6 AA 0 -5672 23376 O4FA 1520 22532 5 2 AE r R60B A4 r R60B O50C A9 32 10988 A6 AB 0 1200 14224 O45 1200 14224 O45 1200 25184 O4B2 1200 25188 O50D A9 6904 32 A6 AA 0 -5672 14224 5 2 AE r R4E3 A4 r R4E3 O50E A9 32 2380 A6 AB 0 1904 16848 O45 1904 16848 O45 1904 19200 O4CB 1904 19204 O4CA -5672 16848 3 2 AE r R315 A4 r R315 O50F A9 32 27196 A6 AB 0 1392 15204 O45 1392 15200 O510 A9 912 24 A6 AA 0 1392 15204 5 2 AE r R5DF A4 r R5DF O511 A9 32 2748 A6 AB 0 944 23716 O45 944 23712 O45 944 26432 O512 A9 6648 32 A6 AA 0 -5672 26432 O4AB 944 23716 3 2 AE r R4EC A4 r R4EC O513 A9 32 23452 A6 AB 0 1712 18948 O45 1712 18944 O503 1712 18948 5 2 AE r R289 A4 r R289 O514 A9 32 33620 A6 AB 0 816 7844 O45 816 7840 O45 816 41432 O515 A9 6520 32 A6 AA 0 -5672 41432 O516 A9 1488 24 A6 AA 0 816 7844 5 2 AE r R792 A4 r R792 O517 A9 32 4012 A6 AB 0 368 29648 O45 368 29648 O45 368 33632 O4E0 368 33636 O4DF -5672 29648 3 2 AE r R611 A4 r R611 O518 A9 32 18812 A6 AB 0 1520 23588 O45 1520 23584 O4FA 1520 23588 3 2 AE r R28B A4 r R28B O519 A9 32 34620 A6 AB 0 1648 7780 O45 1648 7776 O51A A9 656 24 A6 AA 0 1648 7780 3 2 AE r R4F7 A4 r R4F7 O51B A9 32 19932 A6 AB 0 2032 22468 O45 2032 22464 O4BE 2032 22468 0 12064 9568 0 0 O51C A29 -64 0 7912 42400 52 -64 0 7912 42400 5 2 AE r RD0 A4 r RD0 O51D A9 32 8188 A6 AB 0 240 5280 O45 240 5280 O45 240 13440 O4A5 -64 13444 O4CE 240 5280 36 2 AE r RC A4 r RC O4BA 48 752 O4BC -64 752 O4BB 48 752 O4BA 48 4240 O4BC -64 4240 O4BB 48 4240 O4BA 48 7664 O4BC -64 7664 O4BB 48 7664 O4BA 48 10640 O4BC -64 10640 O4BB 48 10640 O4BA 48 14320 O4BC -64 14320 O4BB 48 14320 O4BA 48 18576 O4BC -64 18576 O4BB 48 18576 O4BA 48 23472 O4BC -64 23472 O4BB 48 23472 O4BA 48 27280 O4BC -64 27280 O4BB 48 27280 O4BA 48 31280 O4BC -64 31280 O4BB 48 31280 O4BA 48 34640 O4BC -64 34640 O4BB 48 34640 O4BA 48 38576 O4BC -64 38576 O4BB 48 38576 O4BA 48 42320 O4BC -64 42320 O4BB 48 42320 5 2 AE r R5EA A4 r R5EA O51E A9 32 13100 A6 AB 0 1648 23652 O45 1648 23648 O45 1648 36720 O4AF 1648 36720 O4B0 -64 23652 3 2 AE r RC2 A4 r RC2 O51F A9 32 25148 A6 AB 0 48 17252 O45 48 17248 O4B8 -64 17252 3 2 AE r R3F9 A4 r R3F9 O520 A9 32 19868 A6 AB 0 624 22532 O45 624 22528 O4C8 -64 22532 3 2 AE r R1CE A4 r R1CE O521 A9 32 20060 A6 AB 0 1072 22340 O45 1072 22336 O4C5 -64 22340 3 2 AE r R435 A4 r R435 O4F9 624 0 O45 624 22272 O4C8 -64 22276 5 2 AE r R1A3 A4 r R1A3 O4A4 2608 18820 O45 2608 18816 O45 2608 26432 O522 A9 5304 32 A6 AA 0 2608 26432 O523 A9 2704 24 A6 AA 0 -64 18820 5 2 AE r R19A A4 r R19A O524 A9 32 16508 A6 AB 0 2032 14948 O45 2032 14944 O45 2032 31424 O4E5 2032 31424 O4E6 -64 14948 3 2 AE r R275 A4 r R275 O525 A9 32 27484 A6 AB 0 2480 0 O45 2480 27456 O526 A9 2576 24 A6 AA 0 -64 27460 5 2 AE r R858 A4 r R858 O527 A9 32 21308 A6 AB 0 1520 16480 O45 1520 16480 O45 1520 37760 O4F2 -64 37764 O4F1 1520 16480 5 2 AE r R266 A4 r R266 O528 A9 32 24844 A6 AB 0 1456 13508 O45 1456 13504 O45 1456 38320 O4F5 1456 38320 O4F6 -64 13508 3 2 AE r RBD A4 r RBD O529 A9 32 23196 A6 AB 0 240 19204 O45 240 19200 O4A5 -64 19204 3 2 AE r R316 A4 r R316 O51B 816 22468 O45 816 22464 O510 -64 22468 36 2 AE r RB A4 r RB O4BA 48 3488 O4BC -64 3488 O4BB 48 3488 O4BA 48 6912 O4BC -64 6912 O4BB 48 6912 O4BA 48 9888 O4BC -64 9888 O4BB 48 9888 O4BA 48 13568 O4BC -64 13568 O4BB 48 13568 O4BA 48 17824 O4BC -64 17824 O4BB 48 17824 O4BA 48 22720 O4BC -64 22720 O4BB 48 22720 O4BA 48 26528 O4BC -64 26528 O4BB 48 26528 O4BA 48 30528 O4BC -64 30528 O4BB 48 30528 O4BA 48 33888 O4BC -64 33888 O4BB 48 33888 O4BA 48 37824 O4BC -64 37824 O4BB 48 37824 O4BA 48 41568 O4BC -64 41568 O4BB 48 41568 O4BA 48 0 O4BC -64 0 O4BB 48 0 5 2 AE r R6D3 A4 r R6D3 O52A A9 32 8700 A6 AB 0 2352 19680 O45 2352 19680 O45 2352 28352 O52B A9 2448 24 A6 AA 0 -64 28356 O52C A9 5560 32 A6 AA 0 2352 19680 5 2 AE r REE A4 r REE O52D A9 32 19732 A6 AB 0 304 2888 O45 304 2888 O45 304 22592 O4CB -64 22596 O4CA 304 2888 3 2 AE r R196 A4 r R196 O4A8 1200 22148 O45 1200 22144 O4A9 -64 22148 5 2 AE r R502 A4 r R502 O52E A9 32 9412 A6 AB 0 2416 18756 O45 2416 18752 O45 2416 28136 O52F A9 5496 32 A6 AA 0 2416 28136 O530 A9 2512 24 A6 AA 0 -64 18756 5 2 AE r RC0 A4 r RC0 O531 A9 32 16996 A6 AB 0 1840 15972 O45 1840 15968 O45 1840 32936 O4DF 1840 32936 O4E0 -64 15972 3 2 AE r R198 A4 r R198 O4B3 1136 19716 O45 1136 19712 O4AD -64 19716 5 2 AE r R5F1 A4 r R5F1 O532 A9 32 8428 A6 AB 0 1776 25124 O45 1776 25120 O45 1776 33520 O4C2 1776 33520 O4C1 -64 25124 3 2 AE r R324 A4 r R324 O533 A9 32 23708 A6 AB 0 1008 18692 O45 1008 18688 O4B2 -64 18692 5 2 AE r R1A5 A4 r R1A5 O534 A9 32 13068 A6 AB 0 1968 18884 O45 1968 18880 O45 1968 31920 O4A2 1968 31920 O4A3 -64 18884 3 2 AE r R43C A4 r R43C O535 A9 32 27836 A6 AB 0 368 14564 O45 368 14560 O536 A9 464 24 A6 AA 0 -64 14564 3 2 AE r R261 A4 r R261 O537 A9 32 21148 A6 AB 0 880 21252 O45 880 21248 O4D0 -64 21252 5 2 AE r R794 A4 r R794 O538 A9 32 8156 A6 AB 0 1904 24480 O45 1904 24480 O45 1904 32608 O4EA -64 32612 O4E9 1904 24480 5 2 AE r R1A6 A4 r R1A6 O539 A9 32 6188 A6 AB 0 2096 24164 O45 2096 24160 O45 2096 30320 O4E3 2096 30320 O4E2 -64 24164 3 2 AE r RCA A4 r RCA O53A A9 32 20444 A6 AB 0 688 21956 O45 688 21952 O4FA -64 21956 5 2 AE r R26A A4 r R26A O53B A9 32 14060 A6 AB 0 2288 14692 O45 2288 14688 O45 2288 28720 O53C A9 5624 32 A6 AA 0 2288 28720 O53D A9 2384 24 A6 AA 0 -64 14692 5 2 AE r R6E6 A4 r R6E6 O53E A9 32 16356 A6 AB 0 2224 13304 O45 2224 13304 O45 2224 29632 O53F A9 2320 24 A6 AA 0 -64 29636 O540 A9 5688 32 A6 AA 0 2224 13304 3 2 AE r RCB A4 r RCB O541 A9 32 20188 A6 AB 0 496 22212 O45 496 22208 O503 -64 22212 5 2 AE r RCC A4 r RCC O542 A9 32 26300 A6 AB 0 1264 15204 O45 1264 15200 O45 1264 41472 O512 1264 41472 O4AB -64 15204 3 2 AE r R93B A4 r R93B O543 A9 32 38972 A6 AB 0 1392 0 O45 1392 38944 O516 -64 38948 5 2 AE r R50E A4 r R50E O544 A9 32 4748 A6 AB 0 2544 22404 O45 2544 22400 O45 2544 27120 O545 A9 5368 32 A6 AA 0 2544 27120 O546 A9 2640 24 A6 AA 0 -64 22404 3 2 AE r R18F A4 r R18F O547 A9 32 26556 A6 AB 0 432 15844 O45 432 15840 O4A0 -64 15844 3 2 AE r R403 A4 r R403 O548 A9 32 23260 A6 AB 0 752 19140 O45 752 19136 O4D5 -64 19140 3 2 AE r RCF A4 r RCF O549 A9 32 19740 A6 AB 0 304 22660 O45 304 22656 O4CB -64 22660 3 2 AE r R314 A4 r R314 O54A A9 32 23324 A6 AB 0 944 19076 O45 944 19072 O4B5 -64 19076 5 2 AE r R5F4 A4 r R5F4 O54B A9 32 556 A6 AB 0 2672 24996 O45 2672 24992 O45 2672 25520 O54C A9 5240 32 A6 AA 0 2672 25520 O54D A9 2768 24 A6 AA 0 -64 24996 3 2 AE r R260 A4 r R260 O54E A9 32 27772 A6 AB 0 560 14628 O45 560 14624 O51A -64 14628 5 2 AE r R616 A4 r R616 O54F A9 32 12124 A6 AB 0 1328 11680 O45 1328 11680 O45 1328 23776 O4DA -64 23780 O550 A9 6584 32 A6 AA 0 1328 11680 5 2 AE r R40D A4 r R40D O551 A9 32 14556 A6 AB 0 48 480 O45 48 480 O45 48 15008 O4B8 -64 15012 O4B9 48 480 3 2 AE r R19F A4 r R19F O552 A9 32 31580 A6 AB 0 112 10820 O45 112 10816 O4A7 -64 10820 5 2 AE r R404 A4 r R404 O553 A9 32 476 A6 AB 0 240 14436 O45 240 14432 O45 240 14880 O4CE 240 14880 O4A5 -64 14436 5 2 AE r R1A1 A4 r R1A1 O554 A9 32 14052 A6 AB 0 1328 25316 O45 1328 25312 O45 1328 39336 O550 1328 39336 O4DA -64 25316 5 2 AE r R19B A4 r R19B O555 A9 32 700 A6 AB 0 112 10080 O45 112 10080 O45 112 10752 O4A7 -64 10756 O506 112 10080 1 2 AE r R1CC A4 r R1CC O4C3 176 0 5 2 AE r R5E7 A4 r R5E7 O556 A9 32 14044 A6 AB 0 1584 23716 O45 1584 23712 O45 1584 37728 O4D8 1584 37728 O4D7 -64 23716 5 2 AE r R1A0 A4 r R1A0 O557 A9 32 14948 A6 AB 0 2160 14820 O45 2160 14816 O45 2160 29736 O4DC 2160 29736 O4DD -64 14820 5 2 AE r RCE A4 r RCE O558 A9 32 4924 A6 AB 0 368 8480 O45 368 8480 O45 368 13376 O536 -64 13380 O559 A9 7544 32 A6 AA 0 368 8480 5 2 AE r R4F0 A4 r R4F0 O55A A9 32 15556 A6 AB 0 1712 19012 O45 1712 19008 O45 1712 34536 O4ED 1712 34536 O4EE -64 19012 0 47232 9568 0 0 O55B A29 0 0 48752 3176 38 0 0 48752 3176 5 2 AE r R9B7 "PA2" A4 r R9B7 O55C A9 8408 32 A6 AA 0 34720 112 O45 34720 112 O45 43096 112 O55D A9 32 144 A6 AB 0 43096 0 O55E A9 32 3064 A6 AB 0 34720 112 5 2 AE r RD3 A4 r RD3 O55F A9 25296 32 A6 AA 0 22720 48 O45 22720 48 O45 47984 48 O560 A9 32 80 A6 AB 0 47984 0 O561 A9 32 3128 A6 AB 0 22720 48 5 2 AE r RE6 A4 r RE6 O562 A9 19216 32 A6 AA 0 736 3080 O45 736 3080 O45 19920 3080 O563 A9 32 96 A6 AB 0 19920 3080 O564 A9 32 3112 A6 AB 0 736 0 5 2 AE r RDD A4 r RDD O565 A9 4136 32 A6 AA 0 17496 2616 O45 17496 2616 O45 21600 2616 O566 A9 32 560 A6 AB 0 21600 2616 O567 A9 32 2648 A6 AB 0 17496 0 5 2 AE r RB0 A4 r RB0 O568 A9 15768 32 A6 AA 0 12960 112 O45 12960 112 O45 28696 112 O55D 28696 0 O55E 12960 112 5 2 AE r REF A4 r REF O569 A9 7776 32 A6 AA 0 12720 2744 O45 12720 2744 O45 20464 2744 O56A A9 32 2776 A6 AB 0 20464 0 O56B A9 32 432 A6 AB 0 12720 2744 5 2 AE r R9B8 "PA11" A4 r R9B8 O56C A9 2808 32 A6 AA 0 24320 368 O45 24320 368 O45 27096 368 O56D A9 32 400 A6 AB 0 27096 0 O56E A9 32 2808 A6 AB 0 24320 368 5 2 AE r REA A4 r REA O56F A9 3656 32 A6 AA 0 15896 432 O45 15896 432 O45 19520 432 O570 A9 32 2744 A6 AB 0 19520 432 O571 A9 32 464 A6 AB 0 15896 0 4 2 AE r R435 A4 r R435 O4F8 41464 1264 O45 41464 1264 O572 A9 24 32 A6 AA 0 48728 1264 O573 A9 32 1912 A6 AB 0 41464 1264 5 2 AE r RB6 A4 r RB6 O574 A9 21680 32 A6 AA 0 912 48 O45 912 48 O45 22560 48 O561 22560 48 O560 912 0 5 2 AE r RC5 A4 r RC5 O575 A9 12056 32 A6 AA 0 6296 240 O45 6296 240 O45 18320 240 O576 A9 32 2936 A6 AB 0 18320 240 O577 A9 32 272 A6 AB 0 6296 0 5 2 AE r R9B9 "MEMRDY" A4 r R9B9 O578 A9 21496 32 A6 AA 0 3656 176 O45 3656 176 O45 25120 176 O579 A9 32 3000 A6 AB 0 25120 176 O57A A9 32 208 A6 AB 0 3656 0 4 2 AE r R4EF A4 r R4EF O50B 0 2424 O45 7192 2424 O57B A9 32 752 A6 AB 0 7192 2424 O572 0 2424 5 2 AE r R9BA "RAS1'" A4 r R9BA O57C A9 10776 32 A6 AA 0 14296 2680 O45 14296 2680 O45 25040 2680 O57D A9 32 496 A6 AB 0 25040 2680 O57E A9 32 2712 A6 AB 0 14296 0 5 2 AE r R111 A4 r R111 O57F A9 11448 32 A6 AA 0 22080 2952 O45 22080 2952 O45 33496 2952 O580 A9 32 2984 A6 AB 0 33496 0 O581 A9 32 224 A6 AB 0 22080 2952 5 2 AE r RD2 A4 r RD2 O582 A9 19496 32 A6 AA 0 2056 2952 O45 2056 2952 O45 21520 2952 O581 21520 2952 O580 2056 0 5 2 AE r R104 A4 r R104 O583 A9 19928 32 A6 AA 0 20000 3080 O45 20000 3080 O45 39896 3080 O564 39896 0 O563 20000 3080 5 2 AE r R9BB "PA1" A4 r R9BB O584 A9 21048 32 A6 AA 0 23680 2808 O45 23680 2808 O45 44696 2808 O585 A9 32 2840 A6 AB 0 44696 0 O586 A9 32 368 A6 AB 0 23680 2808 5 2 AE r RF6 A4 r RF6 O587 A9 6096 32 A6 AA 0 12800 368 O45 12800 368 O45 18864 368 O56D 18864 0 O56E 12800 368 5 2 AE r R9BC "RAS2'" A4 r R9BC O588 A9 13976 32 A6 AA 0 12696 304 O45 12696 304 O45 26640 304 O589 A9 32 2872 A6 AB 0 26640 304 O58A A9 32 336 A6 AB 0 12696 0 4 2 AE r R275 A4 r R275 O58B A9 5432 32 A6 AA 0 43320 840 O45 43320 840 O572 48728 840 O58C A9 32 2336 A6 AB 0 43320 840 4 2 AE r R511 A4 r R511 O512 0 2888 O45 6616 2888 O58D A9 32 288 A6 AB 0 6616 2888 O572 0 2888 5 2 AE r REC A4 r REC O58E A9 13176 32 A6 AA 0 9496 2808 O45 9496 2808 O45 22640 2808 O586 22640 2808 O585 9496 0 6 2 AE r R931 A4 r R931 O559 0 1840 O45 824 1840 O45 7512 1840 O58F A9 32 1336 A6 AB 0 7512 1840 O590 A9 32 1872 A6 AB 0 824 0 O572 0 1840 5 2 AE r RA6 A4 r RA6 O591 A9 8168 32 A6 AA 0 22160 2888 O45 22160 2888 O45 30296 2888 O592 A9 32 2920 A6 AB 0 30296 0 O58D 22160 2888 5 2 AE r R9BD "PA6" A4 r R9BD O540 29440 3016 O45 29440 3016 O45 35096 3016 O593 A9 32 3048 A6 AB 0 35096 0 O594 A9 32 160 A6 AB 0 29440 3016 5 2 AE r R9BE "PA3" A4 r R9BE O595 A9 16168 32 A6 AA 0 25360 176 O45 25360 176 O45 41496 176 O57A 41496 0 O579 25360 176 5 2 AE r RC6 A4 r RC6 O596 A9 13256 32 A6 AA 0 8456 2888 O45 8456 2888 O45 21680 2888 O58D 21680 2888 O592 8456 0 5 2 AE r R9BF "PA0" A4 r R9BF O597 A9 22488 32 A6 AA 0 23840 2744 O45 23840 2744 O45 46296 2744 O56A 46296 0 O56B 23840 2744 5 2 AE r RE3 A4 r RE3 O598 A9 11824 32 A6 AA 0 1088 112 O45 1088 112 O45 12880 112 O55E 12880 112 O55D 1088 0 4 2 AE r R4E5 A4 r R4E5 O4D2 0 1056 O45 6936 1056 O599 A9 32 2120 A6 AB 0 6936 1056 O572 0 1056 4 2 AE r R339 A4 r R339 O4CA 0 1408 O45 7576 1408 O59A A9 32 1768 A6 AB 0 7576 1408 O572 0 1408 4 2 AE r R93B A4 r R93B O515 42232 744 O45 42232 744 O572 48728 744 O59B A9 32 2432 A6 AB 0 42232 744 5 2 AE r R9C0 "PDWPin" A4 r R9C0 O59C A9 26792 32 A6 AA 0 1000 3016 O45 1000 3016 O45 27760 3016 O594 27760 3016 O593 1000 0 5 2 AE r R1CC A4 r R1CC O59D A9 5896 32 A6 AA 0 41016 3080 O45 41016 3080 O45 46880 3080 O564 46880 0 O563 41016 3080 5 2 AE r R116 A4 r R116 O59E A9 9688 32 A6 AA 0 22240 240 O45 22240 240 O45 31896 240 O577 31896 0 O576 22240 240 4 2 AE r R91F A4 r R91F O550 0 744 O45 6552 744 O59B 6552 744 O572 0 744 5 2 AE r R9C1 "PA5" A4 r R9C1 O59F A9 12488 32 A6 AA 0 25840 2680 O45 25840 2680 O45 38296 2680 O57E 38296 0 O57D 25840 2680 0 6392 6392 0 0 O5A0 A29 0 0 48752 3176 64 0 0 48752 3176 5 2 AE r R438 A4 r R438 O5A1 A9 6568 32 A6 AA 0 912 392 O45 912 392 O45 7448 392 O5A2 A9 32 424 A6 AB 0 7448 0 O5A3 A9 32 2784 A6 AB 0 912 392 5 2 AE r R892 A4 r R892 O4AF 1408 848 O45 1408 848 O45 7640 848 O5A4 A9 32 880 A6 AB 0 7640 0 O5A5 A9 32 2328 A6 AB 0 1408 848 5 2 AE r R866 A4 r R866 O5A6 A9 7176 32 A6 AA 0 20880 1232 O45 20880 1232 O45 28024 1232 O5A7 A9 32 1944 A6 AB 0 28024 1232 O5A8 A9 32 1264 A6 AB 0 20880 0 5 2 AE r R85A A4 r R85A O5A9 A9 14296 32 A6 AA 0 24960 200 O45 24960 200 O45 39224 200 O5AA A9 32 2976 A6 AB 0 39224 200 O5AB A9 32 232 A6 AB 0 24960 0 5 2 AE r R52C A4 r R52C O5AC A9 4792 32 A6 AA 0 3008 912 O45 3008 912 O45 7768 912 O5AD A9 32 944 A6 AB 0 7768 0 O5AE A9 32 2264 A6 AB 0 3008 912 3 2 AE r R6EE A4 r R6EE O5AF A9 440 32 A6 AB 0 6208 64 O563 6616 0 O564 6208 64 5 2 AE r R4FF A4 r R4FF O5B0 A9 576 32 A6 AA 0 6680 1736 O45 6680 1736 O45 7224 1736 O5B1 A9 32 1440 A6 AB 0 7224 1736 O59A 6680 0 5 2 AE r R43B A4 r R43B O5B2 A9 1096 32 A6 AA 0 6744 1040 O45 6744 1040 O45 7808 1040 O5B3 A9 32 2136 A6 AB 0 7808 1040 O5B4 A9 32 1072 A6 AB 0 6744 0 5 2 AE r R314 A4 r R314 O5B5 A9 672 32 A6 AA 0 41784 848 O45 41784 848 O45 42424 848 O5A5 42424 848 O5A4 41784 0 5 2 AE r R500 A4 r R500 O5B6 A9 8056 32 A6 AA 0 23200 1168 O45 23200 1168 O45 31224 1168 O5B7 A9 32 2008 A6 AB 0 31224 1168 O5B8 A9 32 1200 A6 AB 0 23200 0 5 2 AE r R618 A4 r R618 O5B9 A9 2568 32 A6 AA 0 6872 328 O45 6872 328 O45 9408 328 O5BA A9 32 2848 A6 AB 0 9408 328 O5BB A9 32 360 A6 AB 0 6872 0 5 2 AE r R9C2 "PDin29" A4 r R9C2 O5BC A9 2000 32 A6 AA 0 12240 64 O45 12240 64 O45 14208 64 O564 14208 64 O563 12240 0 5 2 AE r R5EE A4 r R5EE O5BD A9 3520 32 A6 AA 0 6936 200 O45 6936 200 O45 10424 200 O5AA 10424 200 O5AB 6936 0 5 2 AE r R3F9 A4 r R3F9 O5BE A9 5792 32 A6 AA 0 41464 520 O45 41464 520 O45 47224 520 O5BF A9 32 2656 A6 AB 0 47224 520 O5C0 A9 32 552 A6 AB 0 41464 0 5 2 AE r R32A A4 r R32A O5C1 A9 10136 32 A6 AA 0 24320 632 O45 24320 632 O45 34424 632 O5C2 A9 32 2544 A6 AB 0 34424 632 O5C3 A9 32 664 A6 AB 0 24320 0 6 2 AE r R43C A4 r R43C O5C4 A9 8512 32 A6 AA 0 40240 1304 O45 40240 1304 O45 41208 1304 O572 48728 1304 O58F 41208 0 O590 40240 1304 5 2 AE r RBD A4 r RBD O5C5 A9 6936 32 A6 AA 0 41080 64 O45 41080 64 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0 0 O38F 256 320 0 0 O38F 0 384 0 0 O38F 64 384 0 0 O38F 128 384 0 0 O38F 192 384 0 0 O38F 256 384 0 0 O38F 0 448 0 0 O38F 64 448 0 0 O38F 128 448 0 0 O38F 192 448 0 0 O38F 256 448 0 0 O38F 0 512 0 0 O38F 64 512 0 0 O38F 128 512 0 0 O38F 192 512 0 0 O38F 256 512 0 0 O38F 0 576 0 0 O38F 64 576 0 0 O38F 128 576 0 0 O38F 192 576 0 0 O38F 256 576 0 0 O61A 0 0 0 0 O61B 0 0 0 0 0 0 320 640 R2 1033895936 0 0 1 A17 i 83710 43200 148 0 1 A4 r RC O618 43616 0 0 1 A4 r RC O624 A2 0 0 320 640 52 O38F 0 0 0 0 O38F 64 0 0 0 O38F 128 0 0 0 O38F 192 0 0 0 O38F 256 0 0 0 O38F 0 64 0 0 O38F 64 64 0 0 O38F 128 64 0 0 O38F 192 64 0 0 O38F 256 64 0 0 O38F 0 128 0 0 O38F 64 128 0 0 O38F 128 128 0 0 O38F 192 128 0 0 O38F 256 128 0 0 O38F 0 192 0 0 O38F 64 192 0 0 O38F 128 192 0 0 O38F 192 192 0 0 O38F 256 192 0 0 O38F 0 256 0 0 O38F 64 256 0 0 O38F 128 256 0 0 O38F 192 256 0 0 O38F 256 256 0 0 O38F 0 320 0 0 O38F 64 320 0 0 O38F 128 320 0 0 O38F 192 320 0 0 O38F 256 320 0 0 O38F 0 384 0 0 O38F 64 384 0 0 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48752 320 55 0 0 48752 320 3 2 AE r R438 A4 r R438 O607 0 48 O45 912 48 O4BA 912 0 3 2 AE r R892 A4 r R892 O600 1408 240 O601 1408 0 O4BA 1408 240 3 2 AE r R866 A4 r R866 O600 28024 240 O601 28024 0 O4BA 28024 240 3 2 AE r R85A A4 r R85A O600 39224 240 O601 39224 0 O4BA 39224 240 3 2 AE r R52C A4 r R52C O600 3008 240 O601 3008 0 O4BA 3008 240 3 2 AE r R4FF A4 r R4FF O600 7224 240 O601 7224 0 O4BA 7224 240 3 2 AE r R6EE A4 r R6EE O600 6208 240 O601 6208 0 O4BA 6208 240 3 2 AE r R43B A4 r R43B O600 7808 240 O601 7808 0 O4BA 7808 240 3 2 AE r R314 A4 r R314 O600 42424 240 O601 42424 0 O4BA 42424 240 3 2 AE r R500 A4 r R500 O600 31224 240 O601 31224 0 O4BA 31224 240 3 2 AE r R618 A4 r R618 O600 9408 240 O601 9408 0 O4BA 9408 240 3 2 AE r R9C2 A4 r R9C2 O600 14208 240 O601 14208 0 O4BA 14208 240 3 2 AE r R5EE A4 r R5EE O600 10424 240 O601 10424 0 O4BA 10424 240 3 2 AE r R3F9 A4 r R3F9 O600 47224 240 O601 47224 0 O4BA 47224 240 3 2 AE r R32A A4 r R32A O600 34424 240 O601 34424 0 O4BA 34424 240 33 2 AE r RC A4 r RC O603 10808 240 O605 10808 0 O604 10808 240 O603 11208 240 O605 11208 0 O604 11208 240 O603 11624 240 O605 11624 0 O604 11624 240 O603 12024 240 O605 12024 0 O604 12024 240 O603 22208 240 O605 22208 0 O604 22208 240 O603 22624 240 O605 22624 0 O604 22624 240 O603 23024 240 O605 23024 0 O604 23024 240 O603 36408 240 O605 36408 0 O604 36408 240 O603 36808 240 O605 36808 0 O604 36808 240 O603 37224 240 O605 37224 0 O604 37224 240 O603 37624 240 O605 37624 0 O604 37624 240 14 2 AE r R43C A4 r R43C O627 A9 8512 32 A6 AB 0 40240 240 O45 45040 240 O45 48240 240 O45 40240 240 O45 46640 240 O45 41840 240 O4BA 40240 240 O601 40240 0 O4BA 41840 240 O4BA 45040 240 O4BA 46640 240 O4BA 48240 240 O4BA 40240 240 O601 40240 0 3 2 AE r RBD A4 r RBD O606 47984 112 O45 47984 112 O608 47984 0 39 2 AE r R931 A4 r R931 O628 A9 38672 32 A6 AB 0 0 240 O45 240 240 O45 1840 240 O45 6640 240 O45 9840 240 O45 16240 240 O45 19440 240 O45 27440 240 O45 30640 240 O45 33840 240 O45 35440 240 O45 32240 240 O45 29040 240 O45 21040 240 O45 17840 240 O45 14640 240 O45 8240 240 O45 3440 240 O45 736 240 O45 38640 240 O4BA 38640 240 O4BA 240 240 O601 736 0 O4BA 1840 240 O4BA 3440 240 O4BA 6640 240 O4BA 8240 240 O4BA 9840 240 O4BA 14640 240 O4BA 16240 240 O4BA 17840 240 O4BA 19440 240 O4BA 21040 240 O4BA 27440 240 O4BA 29040 240 O4BA 30640 240 O4BA 32240 240 O4BA 33840 240 O4BA 35440 240 3 2 AE r R196 A4 r R196 O600 39808 240 O601 39808 0 O4BA 39808 240 3 2 AE r R198 A4 r R198 O600 41408 240 O601 41408 0 O4BA 41408 240 3 2 AE r R324 A4 r R324 O600 44608 240 O601 44608 0 O4BA 44608 240 3 2 AE r R261 A4 r R261 O600 46208 240 O601 46208 0 O4BA 46208 240 3 2 AE r RCA A4 r RCA O60C 47720 240 O4BA 47808 240 O601 47720 0 3 2 AE r R910 A4 r R910 O600 18424 240 O601 18424 0 O4BA 18424 240 3 2 AE r RCB A4 r RCB O609 47896 176 O45 47896 176 O60B 47896 0 3 2 AE r R4F3 A4 r R4F3 O600 824 240 O601 824 0 O4BA 824 240 3 2 AE r R922 A4 r R922 O600 13064 240 O601 13064 0 O4BA 13064 240 3 2 AE r R9C3 A4 r R9C3 O600 15808 240 O601 15808 0 O4BA 15808 240 3 2 AE r R917 A4 r R917 O600 21624 240 O601 21624 0 O4BA 21624 240 3 2 AE r R948 A4 r R948 O600 17408 240 O601 17408 0 O4BA 17408 240 3 2 AE r R6F0 A4 r R6F0 O600 19008 240 O601 19008 0 O4BA 19008 240 3 2 AE r R4FC A4 r R4FC O600 4024 240 O601 4024 0 O4BA 4024 240 3 2 AE r R9C4 A4 r R9C4 O600 20608 240 O601 20608 0 O4BA 20608 240 3 2 AE r R9C5 A4 r R9C5 O600 27008 240 O601 27008 0 O4BA 27008 240 3 2 AE r R1CE A4 r R1CE O600 40824 240 O601 40824 0 O4BA 40824 240 48 2 AE r RB A4 r RB O603 4408 240 O605 4408 0 O604 4408 240 O603 4808 240 O605 4808 0 O604 4808 240 O603 5224 240 O605 5224 0 O604 5224 240 O603 5624 240 O605 5624 0 O604 5624 240 O603 23608 240 O605 23608 0 O604 23608 240 O603 24008 240 O605 24008 0 O604 24008 240 O603 24424 240 O605 24424 0 O604 24424 240 O603 24824 240 O605 24824 0 O604 24824 240 O603 25208 240 O605 25208 0 O604 25208 240 O603 25608 240 O605 25608 0 O604 25608 240 O603 26024 240 O605 26024 0 O604 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0 0 O38F 384 0 0 0 O38F 448 0 0 0 O38F 512 0 0 0 O38F 576 0 0 0 O662 A9 640 64 A6 AB 0 0 0 0 0 O663 A9 640 64 A6 AA 0 0 0 0 0 0 0 640 64 R2 1061683200 0 0 1 A17 i 83775 916 51144 0 1 A4 r RB O660 896 47392 0 1 A4 r RB O664 A2 0 0 640 64 12 O38F 0 0 0 0 O38F 64 0 0 0 O38F 128 0 0 0 O38F 192 0 0 0 O38F 256 0 0 0 O38F 320 0 0 0 O38F 384 0 0 0 O38F 448 0 0 0 O38F 512 0 0 0 O38F 576 0 0 0 O662 0 0 0 0 O663 0 0 0 0 0 0 640 64 R2 1061683200 0 0 1 A17 i 83774 916 47400 0 1 A4 r RB O660 896 43456 0 1 A4 r RB O665 A2 0 0 640 64 12 O38F 0 0 0 0 O38F 64 0 0 0 O38F 128 0 0 0 O38F 192 0 0 0 O38F 256 0 0 0 O38F 320 0 0 0 O38F 384 0 0 0 O38F 448 0 0 0 O38F 512 0 0 0 O38F 576 0 0 0 O662 0 0 0 0 O663 0 0 0 0 0 0 640 64 R2 1061683200 0 0 1 A17 i 83769 916 43464 0 1 A4 r RB O660 896 40096 0 1 A4 r RB O666 A2 0 0 640 64 12 O38F 0 0 0 0 O38F 64 0 0 0 O38F 128 0 0 0 O38F 192 0 0 0 O38F 256 0 0 0 O38F 320 0 0 0 O38F 384 0 0 0 O38F 448 0 0 0 O38F 512 0 0 0 O38F 576 0 0 0 O662 0 0 0 0 O663 0 0 0 0 0 0 640 64 R2 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WD6 WB9 WB7 WF0 WEA WA9 W111 WBF W7D W9F WA3 W85 W79 W11D WA8 WE7 WC2 W115 W8C WFF WE5 W9C W119 W89 WB5 WDF W98 W8B WCF W10D WAC W8A WC0 WA6 WCB WE3 WF6 WF9 WDB W7E WD4 W90 WB1 W118 WE9 WED WAD W95 WC9 WDA WF4 W10C W102 WCE WDE WBD W94 WD5 WF5 W106 W7C W9E W109 WCA W11A WD9 WBE WA1 W9D W80 WD7 W96 WA0 WC8 WF3 W112 WA4 WFA WFE W88 W117 WCC W8E WB3 WBB W11B W107 WDC WAB W110 WCD W81 W108 WEE WF7 W113 W97 WC6 W103 WA2 W9B WDD WFB WFC WB6 W10E W10A WAF W11C W87 W83 W93 WD1 WEF W99 W9A WEB W105 WA7 WC1 WF2 W92 WFD WB4 W62 1 A35 CMosBTrans 18736 13936 0 C1 W0 167 0 W1 0 3 A0 r RC A1 48 O80 32776 42320 0 O80 32776 42320 0 O80 32776 38576 0 O80 32776 38576 0 O80 32776 34640 0 O80 32776 34640 0 O80 0 31280 0 O80 0 31280 0 O80 32776 27280 0 O80 32776 27280 0 O80 32776 23472 0 O80 32776 23472 0 O80 0 18576 0 O80 0 18576 0 O80 32776 14320 0 O80 32776 14320 0 O80 32776 10640 0 O80 32776 10640 0 O80 32776 7664 0 O80 32776 7664 0 O80 32776 4240 0 O80 32776 4240 0 O80 32776 752 0 O80 32776 752 0 O80 0 752 0 O80 0 752 0 O80 0 4240 0 O80 0 4240 0 O80 0 7664 0 O80 0 7664 0 O80 0 10640 0 O80 0 10640 0 O80 0 14320 0 O80 0 14320 0 O80 32776 18576 0 O80 32776 18576 0 O80 0 23472 0 O80 0 23472 0 O80 0 27280 0 O80 0 27280 0 O80 32776 31280 0 O80 32776 31280 0 O80 0 34640 0 O80 0 34640 0 O80 0 38576 0 O80 0 38576 0 O80 0 42320 0 O80 0 42320 0 A36 GivenName a A36 W2 0 3 A37 Side a A38 top A1 1 O135 17144 42376 0 A0 r R414 W3 0 3 A37 a A39 left A1 1 O6AF A9 24 24 A6 AA 0 0 7908 0 A0 r RC1 W4 0 3 A37 a A3A bottom A1 1 O135 4984 0 0 A0 r RB0 W5 0 3 A37 a A39 A1 1 O6AF 0 15012 0 A0 r R3F8 W6 0 3 A37 a A39 A1 1 O6AF 0 10820 0 A0 r R339 W7 0 3 A37 a A3B right A1 1 O6AF 32776 23716 0 A0 r R5E7 W8 0 3 A37 a A3B A1 1 O6AF 32776 22276 0 A0 r R435 W9 0 3 A37 a A3B A1 1 O6AF 32776 14820 0 A0 r R1A0 WA 0 3 A37 a A39 A1 1 O6AF 0 4356 0 A0 r R1C8 WB 0 3 A37 a A38 A1 2 O135 14664 42376 0 O135 13784 42376 0 A0 r R917 WC 0 3 A37 a A3B A1 1 O6AF 32776 10820 0 A0 r R19F WD 0 3 A37 a A39 A1 1 O6AF 0 18820 0 A0 r R52C WE 0 3 A37 a A39 A1 1 O6AF 0 22084 0 A0 r R509 WF 0 3 A37 a A3B A1 1 O6AF 32776 24996 0 A0 r R5F4 W10 0 3 A37 a A3B A1 1 O6AF 32776 19140 0 A0 r R403 W11 0 3 A37 a A3A A1 1 O135 14744 0 0 A0 r RD3 W12 0 3 A37 a A39 A1 1 O6AF 0 19268 0 A0 r R529 W13 0 3 A37 a A38 A1 1 O135 12824 42376 0 A0 r R262 W14 0 3 A37 a A3B A1 1 O6AF 32776 22660 0 A0 r RCF W15 0 3 A37 a A3B A1 1 O6AF 32776 21956 0 A0 r RCA W16 0 3 A37 a A3A A1 1 O135 14664 0 0 A0 r REC W17 0 3 A37 a A3B A1 1 O6AF 32776 13508 0 A0 r R266 W18 0 3 A37 a A39 A1 1 O6AF 0 15268 0 A0 r R42F W19 0 3 A37 a A38 A1 1 O135 27064 42376 0 A0 r R9C3 W1A 0 3 A37 a A3B A1 1 O6AF 32776 27460 0 A0 r R275 W1B 0 3 A37 a A3A A1 1 O135 4904 0 0 A0 r RE3 W1C 0 3 A37 a A3B A1 1 O6AF 32776 19076 0 A0 r R314 W1D 0 3 A37 a A3B A1 1 O6AF 32776 25316 0 A0 r R1A1 W1E 0 3 A37 a A38 A1 1 O135 16104 42376 0 A0 r R6C0 W1F 0 3 A37 a A3A A1 1 O135 14264 0 0 A0 r R116 W20 0 3 A37 a A3A A1 1 O135 10344 0 0 A0 r RC5 W21 0 3 A37 a A3B A1 1 O6AF 32776 32612 0 A0 r R794 W22 0 3 A37 a A3A A1 1 O135 17064 0 0 A0 r R9BA W23 0 3 A37 a A39 A1 1 O6AF 0 28164 0 A0 r R6EE W24 0 3 A37 a A39 A1 1 O6AF 0 25572 0 A0 r R5EE W25 0 3 A37 a A3A A1 1 O135 21464 0 0 A0 r R9BD W26 0 3 A37 a A39 A1 1 O6AF 0 23652 0 A0 r R613 W27 0 3 A37 a A3B A1 1 O6AF 32776 37764 0 A0 r R858 W28 0 3 A37 a A3A A1 1 O135 15864 0 0 A0 r R9BF W29 0 3 A37 a A39 A1 1 O6AF 0 23716 0 A0 r R5DF W2A 0 3 A37 a A39 A1 1 O6AF 0 22532 0 A0 r R4FD W2B 0 3 A37 a A3B A1 1 O6AF 32776 18756 0 A0 r R502 W2C 0 3 A37 a A3A A1 1 O135 14184 0 0 A0 r RA6 W2D 0 3 A37 a A3A A1 1 O135 16344 0 0 A0 r R9B8 W2E 0 3 A37 a A3B A1 1 O6AF 32776 18692 0 A0 r R324 W2F 0 3 A37 a A3B A1 1 O6AF 32776 22212 0 A0 r RCB W30 0 3 A37 a A3A A1 1 O135 11944 0 0 A0 r RE6 W31 0 3 A37 a A39 A1 1 O6AF 0 22404 0 A0 r R503 W32 0 3 A37 a A3A A1 1 O135 17384 0 0 A0 r R9BE W33 0 3 A37 a A39 A1 1 O6AF 0 15204 0 A0 r R315 W34 0 3 A37 a A39 A1 1 O6AF 0 19396 0 A0 r R516 W35 0 3 A37 a A39 A1 1 O6AF 0 22660 0 A0 r R511 W36 0 3 A37 a A39 A1 1 O6AF 0 14500 0 A0 r R263 W37 0 3 A37 a A39 A1 1 O6AF 0 932 0 A0 r RC3 W38 0 3 A37 a A39 A1 1 O6AF 0 7780 0 A0 r R28B W39 0 3 A37 a A3A A1 1 O135 14584 0 0 A0 r RB6 W3A 0 3 A37 a A3B A1 1 O6AF 32776 14628 0 A0 r R260 W3B 0 3 A37 a A38 A1 1 O135 17064 42376 0 A0 r R1CC W3C 0 3 A37 a A39 A1 1 O6AF 0 20164 0 A0 r R4FC W3D 0 3 A37 a A39 A1 1 O6AF 0 37764 0 A0 r R88E W3E 0 3 A37 a A38 A1 1 O135 16184 42376 0 A0 r R3F5 W3F 0 3 A37 a A3B A1 1 O6AF 32776 17252 0 A0 r RC2 W40 0 3 A37 a A39 A1 1 O6AF 0 14756 0 A0 r R322 W41 0 3 A37 a A39 A1 1 O6AF 0 21892 0 A0 r R4F3 W42 0 3 A37 a A39 A1 1 O6AF 0 33636 0 A0 r R792 W43 0 3 A37 a A3A A1 1 O135 4824 0 0 A0 r RF6 W44 0 3 A37 a A3B A1 1 O6AF 32776 23652 0 A0 r R5EA W45 0 3 A37 a A39 A1 1 O6AF 0 18756 0 A0 r R400 W46 0 3 A37 a A39 A1 1 O6AF 0 27844 0 A0 r R6C4 W47 0 3 A37 a A3B A1 1 O6AF 32776 14436 0 A0 r R404 W48 0 3 A37 a A38 A1 1 O135 4264 42376 0 A0 r R9C2 W49 0 3 A37 a A3A A1 1 O135 13544 0 0 A0 r RD2 W4A 0 3 A37 a A39 A1 1 O6AF 0 13444 0 A0 r R357 W4B 0 3 A37 a A3A A1 1 O135 26744 0 0 A0 r R9B7 W4C 0 3 A37 a A39 A1 1 O6AF 0 21956 0 A0 r R4E5 W4D 0 3 A37 a A3B A1 1 O6AF 32776 13380 0 A0 r RCE W4E 0 3 A37 a A3B A1 1 O6AF 32776 15204 0 A0 r RCC W4F 0 3 A37 a A38 A1 1 O135 16984 42376 0 A0 r R85A W50 0 3 A37 a A38 A1 1 O135 6824 42376 0 A0 r R909 W51 0 3 A37 a A3B A1 1 O6AF 32776 18884 0 A0 r R1A5 W52 0 3 A37 a A39 A1 1 O6AF 0 7844 0 A0 r R289 W53 0 3 A37 a A3B A1 1 O6AF 32776 18820 0 A0 r R1A3 W54 0 3 A37 a A39 A1 1 O6AF 0 19076 0 A0 r R4E8 W55 0 3 A37 a A3A A1 1 O135 18664 0 0 A0 r R9BC W56 0 3 A37 a A39 A1 1 O6AF 0 34756 0 A0 r R892 W57 0 3 A37 a A3B A1 1 O6AF 32776 19204 0 A0 r RBD W58 0 3 A37 a A3B A1 1 O6AF 32776 22532 0 A0 r R3F9 W59 0 3 A37 a A3A A1 1 O135 17144 0 0 A0 r R9B9 W5A 0 3 A37 a A39 A1 1 O6AF 0 25188 0 A0 r R60B W5B 0 3 A37 a A3B A1 1 O6AF 32776 22596 0 A0 r REE W5C 0 3 A37 a A3B A1 1 O6AF 32776 14948 0 A0 r R19A W5D 0 3 A37 a A3B A1 1 O6AF 32776 22340 0 A0 r R1CE W5E 0 3 A37 a A38 A1 1 O135 16264 42376 0 A0 r R6D1 W5F 0 3 A37 a A38 A1 1 O135 12904 42376 0 A0 r R866 W60 0 3 A37 a A3B A1 1 O6AF 32776 29636 0 A0 r R6E6 W61 0 3 A37 a A3B A1 1 O6AF 32776 19012 0 A0 r R4F0 W62 0 3 A37 a A3A A1 1 O135 17864 0 0 A0 r R9C1 W63 0 3 A37 a A39 A1 1 O6AF 0 22596 0 A0 r R4FA W64 0 3 A37 a A3B A1 1 O6AF 32776 22404 0 A0 r R50E W65 0 3 A37 a A3B A1 1 O6AF 32776 22148 0 A0 r R196 W66 0 3 A37 a A38 A1 1 O135 14744 42376 0 A0 r R914 W67 0 3 A37 a A39 A1 1 O6AF 0 23588 0 A0 r R611 W68 0 3 A37 a A39 A1 1 O6AF 0 24740 0 A0 r R5E2 W69 0 3 A37 a A38 A1 1 O135 22504 42376 0 A0 r R948 W6A 0 3 A37 a A3B A1 1 O6AF 32776 13444 0 A0 r RD0 W6B 0 3 A37 a A39 A1 1 O6AF 0 14884 0 A0 r R438 W6C 0 3 A37 a A3B A1 1 O6AF 32776 24164 0 A0 r R1A6 W6D 0 3 A37 a A3A A1 1 O135 12024 0 0 A0 r R104 W6E 0 3 A37 a A39 A1 1 O6AF 0 14628 0 A0 r R41E W6F 0 3 A37 a A39 A1 1 O6AF 0 14564 0 A0 r R424 W70 0 3 A37 a A39 A1 1 O6AF 0 19140 0 A0 r R52B W71 0 3 A37 a A3B A1 1 O6AF 32776 14692 0 A0 r R26A W72 0 3 A37 a A39 A1 1 O6AF 0 22340 0 A0 r R4F8 W73 0 3 A37 a A39 A1 1 O6AF 0 15140 0 A0 r R3FC W74 0 3 A37 a A3B A1 1 O6AF 32776 15012 0 A0 r R40D W75 0 3 A37 a A3B A1 1 O6AF 32776 14564 0 A0 r R43C W76 0 3 A37 a A39 A1 1 O6AF 0 14692 0 A0 r R43B W77 0 3 A37 a A39 A1 1 O6AF 0 22276 0 A0 r R4EF W78 0 3 A37 a A38 A1 1 O135 16344 42376 0 A0 r R32A W79 0 3 A37 a A38 A1 1 O135 15224 42376 0 A0 r R500 W7A 0 3 A37 a A39 A1 1 O6AF 0 31716 0 A0 r R7C2 W7B 0 3 A37 a A39 A1 1 O6AF 0 22468 0 A0 r R4F7 W7C 0 3 A37 a A3B A1 1 O6AF 32776 10756 0 A0 r R19B W7D 0 3 A37 a A39 A1 1 O6AF 0 22020 0 A0 r R523 W7E 0 3 A37 a A3A A1 1 O135 11544 0 0 A0 r REA W7F 0 3 A37 a A3A A1 1 O135 14104 0 0 A0 r R111 W80 0 3 A37 a A38 A1 1 O135 18904 42376 0 A0 r R931 W81 0 3 A37 a A38 A1 1 O135 16904 42376 0 A0 r R6F0 W82 0 3 A37 a A3B A1 1 O6AF 32776 15972 0 A0 r RC0 W83 0 3 A37 a A3A A1 1 O135 19784 0 0 A0 r R9C0 W84 0 3 A37 a A39 A1 1 O6AF 0 26340 0 A0 r R618 W85 0 3 A37 a A3B A1 1 O6AF 32776 23780 0 A0 r R616 W86 0 3 A37 a A39 A1 1 O6AF 0 23844 0 A0 r R5EB W87 0 3 A37 a A38 A1 1 O135 17464 42376 0 A0 r R910 W88 0 3 A37 a A3B A1 1 O6AF 32776 21252 0 A0 r R261 W89 0 3 A37 a A38 A1 1 O135 16424 42376 0 A0 r R7A4 W8A 0 3 A37 a A39 A1 1 O6AF 0 22148 0 A0 r R4FF W8B 0 3 A37 a A39 A1 1 O6AF 0 34820 0 A0 r R883 W8C 0 3 A37 a A3B A1 1 O6AF 32776 38948 0 A0 r R93B W8D 0 3 A37 a A38 A1 1 O135 18184 42376 0 A0 r R9C5 W8E 0 3 A37 a A39 A1 1 O6AF 0 19012 0 A0 r R4F4 W8F 0 3 A37 a A39 A1 1 O6AF 0 13508 0 A0 r R345 W90 0 3 A37 a A3B A1 1 O6AF 32776 25124 0 A0 r R5F1 W91 0 3 A37 a A38 A1 1 O135 16824 42376 0 A0 r R4E4 W92 0 3 A37 a A38 A1 1 O135 15144 42376 0 A0 r R504 W93 0 3 A37 a A3A A1 1 O135 4744 0 0 A0 r REF W94 0 3 A37 a A38 A1 2 O135 17224 42376 0 O135 16664 42376 0 A0 r R922 W95 0 3 A37 a A38 A1 2 O135 18824 42376 0 O135 17544 42376 0 A0 r R90C W96 0 3 A37 a A3A A1 1 O135 13704 0 0 A0 r RC6 W97 0 3 A37 a A39 A1 1 O6AF 0 18948 0 A0 r R4EC W98 0 3 A37 a A39 A1 1 O6AF 0 22212 0 A0 r R4FB W99 0 3 A37 a A39 A1 1 O6AF 0 18692 0 A0 r R40A W9A 0 3 A37 a A39 A1 1 O6AF 0 14436 0 A0 r R42D W9B 0 3 A37 a A3B A1 1 O6AF 32776 28356 0 A0 r R6D3 W9C 0 3 A37 a A3B A1 1 O6AF 32776 22468 0 A0 r R316 W9D 0 3 A37 a A39 A1 1 O6AF 0 10756 0 A0 r R348 W9E 0 3 A37 a A39 A1 1 O6AF 0 18884 0 A0 r R3FD W9F 0 3 A37 a A3B A1 1 O6AF 32776 15844 0 A0 r R18F WA0 0 3 A37 a A38 A1 1 O135 8344 42376 0 A0 r R9C4 WA1 0 3 A37 a A39 A1 1 O6AF 0 41508 0 A0 r R91F WA2 0 3 A37 a A3A A1 1 O135 15704 0 0 A0 r R9BB WA3 0 3 A37 a A3B A1 1 O6AF 32776 19716 0 A0 r R198 WA4 0 3 A37 a A39 A1 1 O6AF 0 19204 0 A0 r R4E3 WA5 0 3 A37 a A38 A1 1 O135 16504 42376 0 A0 r R5DB WA6 0 3 A37 a A3A A1 1 O135 13624 0 0 A0 r RDD WA7 0 3 A0 r RB A1 48 O80 32776 41568 0 O80 32776 41568 0 O80 32776 37824 0 O80 32776 37824 0 O80 32776 33888 0 O80 32776 33888 0 O80 32776 30528 0 O80 32776 30528 0 O80 32776 26528 0 O80 32776 26528 0 O80 32776 22720 0 O80 32776 22720 0 O80 32776 17824 0 O80 32776 17824 0 O80 32776 13568 0 O80 32776 13568 0 O80 32776 9888 0 O80 32776 9888 0 O80 32776 6912 0 O80 32776 6912 0 O80 32776 3488 0 O80 32776 3488 0 O80 32776 0 0 O80 32776 0 0 O80 0 0 0 O80 0 0 0 O80 0 3488 0 O80 0 3488 0 O80 0 6912 0 O80 0 6912 0 O80 0 9888 0 O80 0 9888 0 O80 0 13568 0 O80 0 13568 0 O80 0 17824 0 O80 0 17824 0 O80 0 22720 0 O80 0 22720 0 O80 0 26528 0 O80 0 26528 0 O80 0 30528 0 O80 0 30528 0 O80 0 33888 0 O80 0 33888 0 O80 0 37824 0 O80 0 37824 0 O80 0 41568 0 O80 0 41568 0 A36 a A36 5 A34 O11 AC O11 A32 a A3C SC A3D numRows i 12 A0 r R9A0 R9C7 "Import" R9C8 "MIInner.core" 924680 1 C0 C1 2449 R8EF R8F4 R8EE R8F3 R8ED R8F2 R7EF R7EE R8EC R8F1 R7EE R7ED R8EB R8F0 R6EF R6E8 R7ED R7EC R8EA R8EF R6EE R6E7 R7EC R7EB R5EF R5D5 R6ED R6E5 R7EB R7EA R5EE R5D4 R6EC R6E4 R7EA R7E9 R4EF R4B9 R5ED R5D3 R6EB R6E3 R4EE R4B8 R5EC R5D2 R6EA R6E2 R3EF R3A6 R4ED R4B7 R5EB R5D1 R3EE R3A5 R4EC R4B6 R5EA R5D0 R3ED R3A4 R2EF R29C R4EB R4B5 R8E9 R8EE R3EC R3A3 R2EE R29B R4EA R4B4 R8E8 R8ED R3EB R3A2 R2ED R29A R1EF R185 R95F R96E R8E7 R8EC R3EA R3A1 R2EC R299 R1EE R184 R7E9 R7E8 R95E R96D R8E6 R8EB R2EB R298 R1ED R183 R7E8 R7E7 R95D R96C R8E5 R8EA R85F R860 R2EA R297 R1EC R182 R6E9 R6E1 R7E7 R7E6 R95C R96B R8E4 R8E9 R85E R85F R1EB R181 R6E8 R6E0 R7E6 R7E5 R95B R96A R8E3 R8E8 R85D R85E R1EA R180 R5E9 R5CF R6E7 R6DF R7E5 R7E4 R75F R75A R95A R969 R8E2 R8E7 R85C R85D R5E8 R5CE R6E6 R6DE R7E4 R7E3 R75E R759 R8E1 R8E6 R85B R85C R4E9 R4B3 R5E7 R5CD R6E5 R6DD R7E3 R7E2 R65F R653 R75D R758 R8E0 R8E5 R85A R85B R4E8 R4B2 R5E6 R5CC R6E4 R6DC R7E2 R7E1 R65E R652 R75C R757 R3E9 R3A0 R4E7 R4B1 R5E5 R5CB R6E3 R6DB R7E1 R7E0 R55F R545 R65D R651 R75B R756 R3E8 R39F R4E6 R4B0 R5E4 R5CA R6E2 R6DA R7E0 R7DF R55E R544 R65C R650 R75A R755 R3E7 R39E R2E9 R296 R4E5 R4AF R5E3 R5C9 R6E1 R6D9 R45F R422 R55D R543 R65B R64F R3E6 R39D R2E8 R295 R4E4 R4AE R5E2 R5C8 R6E0 R6D8 R45E R421 R55C R542 R65A R64E R3E5 R39C R2E7 R294 R1E9 R17F R4E3 R4AD R5E1 R5C7 R35F R30C R45D R420 R55B R541 R959 R968 R3E4 R39B R2E6 R293 R1E8 R17E R4E2 R4AC R5E0 R5C6 R35E R30B R45C R41F R55A R540 R958 R967 R3E3 R39A R2E5 R292 R1E7 R17D R4E1 R4AB R35D R30A R25F R203 R45B R41D R957 R966 R859 R859 R3E2 R399 R2E4 R291 R1E6 R17C R4E0 R4AA R35C R309 R25E R202 R45A R41C R956 R965 R858 R857 R3E1 R398 R2E3 R290 R1E5 R17B R35B R308 R25D R201 R15F RF1 R955 R964 R857 R856 R3E0 R397 R2E2 R28F R1E4 R17A R35A R307 R25C R200 R15E RF0 R759 R754 R954 R963 R856 R855 R2E1 R28E R1E3 R179 R25B R1FF R15D RED R758 R753 R953 R962 R855 R854 R2E0 R28D R1E2 R178 R25A R1FE R15C REB R659 R64D R757 R752 R952 R961 R854 R853 R1E1 R177 R15B RE9 R658 R64C R756 R751 R951 R960 R853 R852 R1E0 R176 R15A RE8 R559 R53F R657 R64B R755 R750 R950 R95F R852 R851 R558 R53E R656 R64A R754 R74F R851 R850 R459 R41B R557 R53D R655 R649 R753 R74E R850 R84F R458 R41A R556 R53C R654 R648 R752 R74D R359 R306 R457 R419 R555 R53B R653 R647 R751 R74C R358 R305 R456 R418 R554 R53A R652 R646 R750 R74B RFE R77 R357 R304 R259 R1FD R455 R417 R553 R539 R651 R645 R356 R303 R258 R1FC R454 R416 R552 R538 R650 R644 REE R67 R355 R302 R257 R1FB R159 RE7 R453 R415 R551 R537 R354 R301 R256 R1FA R158 RE5 R452 R413 R550 R536 RDE R57 R353 R300 R255 R1F9 R157 RE4 R451 R412 R352 R2FF R254 R1F8 R156 RE2 R450 R411 RCE R47 R351 R2FE R253 R1F7 R155 RE1 R350 R2FD R252 R1F6 R154 RE0 RBE R37 R251 R1F5 R153 RDF R250 R1F4 R152 RDE RAE R27 R151 RDC R150 RDB RF5 R6E RE5 R5E RD5 R4E RC5 R3E RB5 R2E R9E R18F RA5 RDD R8E R345 R7E R111 R6E R424 R5E R866 R4E R85A R3E RC2 R2E RCB R1E R116 R95 RC6 R85 R5EB R75 R43B R65 R914 R55 R892 R45 R6C4 R35 R263 R25 R613 R15 REC R8DF R8E4 R8DE R8E3 R8DD R8E2 R7DF R7DE R8DC R8E1 R7DE R7DD R8DB R8E0 R6DF R6D7 R7DD R7DC R8DA R8DF R6DE R6D6 R7DC R7DB R5DF R5C5 R6DD R6D5 R7DB R7DA R5DE R5C4 R6DC R6D4 R7DA R7D9 R4DF R4A9 R5DD R5C3 R6DB R6D2 R4DE R4A8 R5DC R5C2 R6DA R6D0 R3DF R396 R4DD R4A7 R5DB R5C1 R3DE R395 R4DC R4A6 R5DA R5C0 R3DD R394 R2DF R28C R4DB R4A5 R8D9 R8DE R3DC R393 R2DE R28A R4DA R4A4 R8D8 R8DD R3DB R392 R2DD R288 R1DF R175 R94F R95E R8D7 R8DC R3DA R391 R2DC R287 R1DE R174 R7D9 R7D8 R94E R95D R8D6 R8DB R2DB R286 R1DD R173 R7D8 R7D7 R94D R95C R8D5 R8DA R84F R84E R2DA R285 R1DC R172 R6D9 R6CF R7D7 R7D6 R94C R95B R8D4 R8D9 R84E R84D R1DB R171 R6D8 R6CE R7D6 R7D5 R94B R95A R8D3 R8D8 R84D R84C R1DA R170 R5D9 R5BF R6D7 R6CD R7D5 R7D4 R74F R74A R94A R959 R8D2 R8D7 R84C R84B R5D8 R5BE R6D6 R6CC R7D4 R7D3 R74E R749 R8D1 R8D6 R84B R84A R4D9 R4A3 R5D7 R5BD R6D5 R6CB R7D3 R7D2 R64F R643 R74D R748 R8D0 R8D5 R84A R849 R4D8 R4A2 R5D6 R5BC R6D4 R6CA R7D2 R7D1 R64E R642 R74C R747 R3D9 R390 R4D7 R4A1 R5D5 R5BB R6D3 R6C9 R7D1 R7D0 R54F R535 R64D R641 R74B R746 R3D8 R38F R4D6 R4A0 R5D4 R5BA R6D2 R6C8 R7D0 R7CF R54E R534 R64C R640 R74A R745 R3D7 R38E R2D9 R284 R4D5 R49F R5D3 R5B9 R6D1 R6C7 R44F R410 R54D R533 R64B R63F R3D6 R38D R2D8 R283 R4D4 R49E R5D2 R5B8 R6D0 R6C6 R44E R40F R54C R532 R64A R63E R3D5 R38C R2D7 R282 R1D9 R16F R4D3 R49D R5D1 R5B7 R34F R2FC R44D R40E R54B R531 R949 R958 R3D4 R38B R2D6 R281 R1D8 R16E R4D2 R49C R5D0 R5B6 R34E R2FB R44C R40C R54A R530 R948 R957 R3D3 R38A R2D5 R280 R1D7 R16D R4D1 R49B R34D R2FA R24F R1F3 R44B R40B R947 R956 R849 R848 R3D2 R389 R2D4 R27F R1D6 R16C R4D0 R49A R34C R2F9 R24E R1F2 R44A R409 R946 R955 R848 R847 R3D1 R388 R2D3 R27E R1D5 R16B R34B R2F8 R24D R1F1 R14F RDA R945 R954 R847 R846 R3D0 R387 R2D2 R27D R1D4 R16A R34A R2F7 R24C R1F0 R14E RD9 R749 R744 R944 R953 R846 R845 R2D1 R27C R1D3 R169 R24B R1EF R14D RD8 R748 R743 R943 R952 R845 R844 R2D0 R27B R1D2 R168 R24A R1EE R14C RD7 R649 R63D R747 R742 R942 R951 R844 R843 R1D1 R167 R14B RD6 R648 R63C R746 R741 R941 R950 R843 R842 R1D0 R166 R14A RD5 R549 R52F R647 R63B R745 R740 R940 R94F R842 R841 R548 R52E R646 R63A R744 R73F R841 R840 R449 R408 R547 R52D R645 R639 R743 R73E R840 R83F R448 R407 R546 R52A R644 R638 R742 R73D R349 R2F6 R447 R406 R545 R528 R643 R637 R741 R73C R348 R2F5 R446 R405 R544 R527 R642 R636 R740 R73B RFD R76 R347 R2F4 R249 R1ED R445 R402 R543 R526 R641 R635 R346 R2F3 R248 R1EC R444 R401 R542 R525 R640 R634 RED R66 R345 R2F2 R247 R1EB R149 RD4 R443 R3FF R541 R524 R344 R2F1 R246 R1EA R148 RD1 R442 R3FE R540 R522 RDD R56 R343 R2F0 R245 R1E9 R147 RCD R441 R3FB R342 R2EF R244 R1E8 R146 RC9 R440 R3FA RCD R46 R341 R2EE R243 R1E7 R145 RC8 R340 R2ED R242 R1E6 R144 RC7 RBD R36 R241 R1E5 R143 RC4 R240 R1E4 R142 RBF RAD R26 R141 RBE R140 RBC RF4 R6D RE4 R5D RD4 R4D RC4 R3D RB4 R2D R9D R3FD RA4 R5DB R8D R4F4 R7D REA R6D R41E R5D R6D1 R4D RCC R3D R3F5 R2D R324 R1D R6C0 R94 R90C R84 R616 R74 R43C R64 R196 R54 R9BC R44 R400 R34 R511 R24 R9BD R14 RCA R8CF R8D4 R8CE R8D3 R8CD R8D2 R7CF R7CE R8CC R8D1 R7CE R7CD R8CB R8D0 R6CF R6C5 R7CD R7CC R8CA R8CF R6CE R6C3 R7CC R7CB R5CF R5B5 R6CD R6C2 R7CB R7CA R5CE R5B4 R6CC R6C1 R7CA R7C9 R4CF R499 R5CD R5B3 R6CB R6BF R4CE R498 R5CC R5B2 R6CA R6BE R3CF R386 R4CD R497 R5CB R5B1 R3CE R385 R4CC R496 R5CA R5B0 R3CD R384 R2CF R27A R4CB R495 R8C9 R8CE R3CC R383 R2CE R279 R4CA R494 R8C8 R8CD R3CB R382 R2CD R278 R1CF R165 R93F R94E R8C7 R8CC R3CA R381 R2CC R277 R1CE R164 R7C9 R7C8 R93E R94D R8C6 R8CB R2CB R276 R1CD R163 R7C8 R7C7 R93D R94C R8C5 R8CA R83F R83E R2CA R274 R1CC R162 R6C9 R6BD R7C7 R7C6 R93C R94B R8C4 R8C9 R83E R83D R1CB R161 R6C8 R6BC R7C6 R7C5 R93B R94A R8C3 R8C8 R83D R83C R1CA R160 R5C9 R5AF R6C7 R6BB R7C5 R7C4 R73F R73A R93A R949 R8C2 R8C7 R83C R83B R5C8 R5AE R6C6 R6BA R7C4 R7C3 R73E R739 R8C1 R8C6 R83B R83A R4C9 R493 R5C7 R5AD R6C5 R6B9 R7C3 R7C1 R63F R633 R73D R738 R8C0 R8C5 R83A R839 R4C8 R492 R5C6 R5AC R6C4 R6B8 R7C2 R7C0 R63E R632 R73C R737 R3C9 R380 R4C7 R491 R5C5 R5AB R6C3 R6B7 R7C1 R7BF R53F R521 R63D R631 R73B R736 R3C8 R37F R4C6 R490 R5C4 R5AA R6C2 R6B6 R7C0 R7BE R53E R520 R63C R630 R73A R735 R3C7 R37E R2C9 R273 R4C5 R48F R5C3 R5A9 R6C1 R6B5 R43F R3F7 R53D R51F R63B R62F R3C6 R37D R2C8 R272 R4C4 R48E R5C2 R5A8 R6C0 R6B4 R43E R3F6 R53C R51E R63A R62E R3C5 R37C R2C7 R271 R1C9 R15F R4C3 R48D R5C1 R5A7 R33F R2EC R43D R3F4 R53B R51D R939 R947 R3C4 R37B R2C6 R270 R1C8 R15E R4C2 R48C R5C0 R5A6 R33E R2EB R43C R3F3 R53A R51C R938 R946 R3C3 R37A R2C5 R26F R1C7 R15D R4C1 R48B R33D R2EA R23F R1E3 R43B R3F2 R937 R945 R839 R838 R3C2 R379 R2C4 R26E R1C6 R15C R4C0 R48A R33C R2E9 R23E R1E2 R43A R3F1 R936 R944 R838 R837 R3C1 R378 R2C3 R26D R1C5 R15B R33B R2E8 R23D R1E1 R13F RBB R935 R943 R837 R836 R3C0 R377 R2C2 R26C R1C4 R15A R33A R2E7 R23C R1E0 R13E RBA R739 R734 R934 R942 R836 R835 R2C1 R26B R1C3 R159 R23B R1DF R13D RB9 R738 R733 R933 R941 R835 R834 R2C0 R269 R1C2 R158 R23A R1DE R13C RB8 R639 R62D R737 R732 R932 R940 R834 R833 R1C1 R157 R13B RB7 R638 R62C R736 R731 R931 R93F R833 R832 R1C0 R156 R13A RB5 R539 R51B R637 R62B R735 R730 R930 R93E R832 R831 R538 R51A R636 R62A R734 R72F R831 R830 R439 R3F0 R537 R519 R635 R629 R733 R72E R830 R82F R438 R3EF R536 R518 R634 R628 R732 R72D R339 R2E6 R437 R3EE R535 R517 R633 R627 R731 R72C R338 R2E5 R436 R3ED R534 R515 R632 R626 R730 R72B RFC R75 R337 R2E4 R239 R1DD R435 R3EC R533 R514 R631 R625 R336 R2E3 R238 R1DC R434 R3EB R532 R513 R630 R624 REC R65 R335 R2E2 R237 R1DB R139 RB4 R433 R3EA R531 R512 R334 R2E1 R236 R1DA R138 RB3 R432 R3E9 R530 R510 RDC R55 R333 R2E0 R235 R1D9 R137 RB2 R431 R3E8 R332 R2DF R234 R1D8 R136 RB1 R430 R3E7 RCC R45 R331 R2DE R233 R1D7 R135 RAF R330 R2DD R232 R1D6 R134 RAE RBC R35 R231 R1D5 R133 RAD R230 R1D4 R132 RAC RAC R25 R131 RAB R130 RAA RF R403 RE R5F4 RF3 R6C RD R509 RC R52C RE3 R5C RB R19F RA R917 RD3 R4C RC3 R3C RB3 R2C R9C R348 RA3 R4E3 R8C R9C5 R9 R1C8 R8 R1A0 R7C R523 R7 R435 R6 R5E7 R6C R104 R5 R339 R4 R3F8 R5C R1CE R3 RB0 R2 RC1 R4C RCE R1 R414 R0 RC R3C R88E R2C R9B8 R1C R1A1 R93 R922 R83 R618 R73 R40D R63 R50E R53 R4E8 R43 R5EA R33 R516 R23 R5EE R13 RCF R8BF R8C4 R8BE R8C3 R8BD R8C2 R7BF R7BD R8BC R8C1 R7BE R7BC R8BB R8C0 R6BF R6B3 R7BD R7BB R8BA R8BF R6BE R6B2 R7BC R7BA R5BF R5A5 R6BD R6B1 R7BB R7B9 R5BE R5A4 R6BC R6B0 R7BA R7B8 R4BF R489 R5BD R5A3 R6BB R6AF R4BE R488 R5BC R5A2 R6BA R6AE R3BF R376 R4BD R487 R5BB R5A1 R3BE R375 R4BC R486 R5BA R5A0 R3BD R374 R2BF R268 R4BB R485 R8B9 R8BE R3BC R373 R2BE R267 R4BA R484 R8B8 R8BD R3BB R372 R2BD R265 R1BF R155 R92F R93D R8B7 R8BC R3BA R371 R2BC R264 R1BE R154 R7B9 R7B7 R92E R93C R8B6 R8BB R2BB R25F R1BD R153 R7B8 R7B6 R92D R93A R8B5 R8BA R82F R82E R2BA R25E R1BC R152 R6B9 R6AD R7B7 R7B5 R92C R939 R8B4 R8B9 R82E R82D R1BB R151 R6B8 R6AC R7B6 R7B4 R92B R938 R8B3 R8B8 R82D R82C R1BA R150 R5B9 R59F R6B7 R6AB R7B5 R7B3 R72F R72A R92A R937 R8B2 R8B7 R82C R82B R5B8 R59E R6B6 R6AA R7B4 R7B2 R72E R729 R8B1 R8B6 R82B R82A R4B9 R483 R5B7 R59D R6B5 R6A9 R7B3 R7B1 R62F R623 R72D R728 R8B0 R8B5 R82A R829 R4B8 R482 R5B6 R59C R6B4 R6A8 R7B2 R7B0 R62E R622 R72C R727 R3B9 R370 R4B7 R481 R5B5 R59B R6B3 R6A7 R7B1 R7AF R52F R50F R62D R621 R72B R726 R3B8 R36F R4B6 R480 R5B4 R59A R6B2 R6A6 R7B0 R7AE R52E R50D R62C R620 R72A R725 R3B7 R36E R2B9 R25D R4B5 R47F R5B3 R599 R6B1 R6A5 R42F R3E6 R52D R50C R62B R61F R3B6 R36D R2B8 R25C R4B4 R47E R5B2 R598 R6B0 R6A4 R42E R3E5 R52C R50B R62A R61E R3B5 R36C R2B7 R25B R1B9 R14F R4B3 R47D R5B1 R597 R32F R2DC R42D R3E4 R52B R50A R929 R936 R3B4 R36B R2B6 R25A R1B8 R14E R4B2 R47C R5B0 R596 R32E R2DB R42C R3E3 R52A R508 R928 R935 R3B3 R36A R2B5 R259 R1B7 R14D R4B1 R47B R32D R2DA R22F R1D3 R42B R3E2 R927 R934 R829 R828 R3B2 R369 R2B4 R258 R1B6 R14C R4B0 R47A R32C R2D9 R22E R1D2 R42A R3E1 R926 R933 R828 R827 R3B1 R368 R2B3 R257 R1B5 R14B R32B R2D8 R22D R1D1 R12F RA9 R925 R932 R827 R826 R3B0 R367 R2B2 R256 R1B4 R14A R32A R2D7 R22C R1D0 R12E RA8 R729 R724 R924 R930 R826 R825 R2B1 R255 R1B3 R149 R22B R1CF R12D RA7 R728 R723 R923 R92F R825 R824 R2B0 R254 R1B2 R148 R22A R1CD R12C RA5 R629 R61D R727 R722 R922 R92E R824 R823 R1B1 R147 R12B RA4 R628 R61C R726 R721 R921 R92D R823 R822 R1B0 R146 R12A RA3 R529 R507 R627 R61B R725 R720 R920 R92C R822 R821 R528 R506 R626 R61A R724 R71F R821 R820 R429 R3E0 R527 R505 R625 R619 R723 R71E R820 R81F R428 R3DF R526 R501 R624 R617 R722 R71D R329 R2D6 R427 R3DE R525 R4FE R623 R615 R721 R71C R328 R2D5 R426 R3DD R524 R4F9 R622 R614 R720 R71B RFB R74 R327 R2D4 R229 R1CB R425 R3DC R523 R4F6 R621 R612 R326 R2D3 R228 R1CA R424 R3DB R522 R4F5 R620 R610 REB R64 R325 R2D2 R227 R1C9 R129 RA2 R423 R3DA R521 R4F2 R324 R2D1 R226 R1C7 R128 RA1 R422 R3D9 R520 R4F1 RDB R54 R323 R2D0 R225 R1C6 R127 RA0 R421 R3D8 R322 R2CF R224 R1C5 R126 R9F R420 R3D7 RCB R44 R321 R2CE R223 R1C4 R125 R9E R320 R2CD R222 R1C3 R124 R9D RBB R34 R221 R1C2 R123 R9C R220 R1C1 R122 R9B RAB R24 R121 R9A R120 R99 RF2 R6B RE2 R5B RD2 R4B RC2 R3B RB2 R2B R9B R316 RA2 R198 R8B R93B R7B R19B R6B R1A6 R5B R19A R4B R4E5 R3B R4FC R2B RA6 R1B R314 R92 REF R82 R9C0 R72 R3FC R62 R4FA R52 R1A3 R42 RF6 R32 R315 R22 R6EE R12 R262 R8AF R8B4 R8AE R8B3 R8AD R8B2 R7AF R7AD R8AC R8B1 R7AE R7AC R8AB R8B0 R6AF R6A3 R7AD R7AB R8AA R8AF R6AE R6A2 R7AC R7AA R5AF R595 R6AD R6A1 R7AB R7A9 R5AE R594 R6AC R6A0 R7AA R7A8 R4AF R479 R5AD R593 R6AB R69F R89F R8A4 R4AE R478 R5AC R592 R6AA R69E R89E R8A3 R3AF R366 R4AD R477 R5AB R591 R89D R8A2 R79F R79C R3AE R365 R4AC R476 R5AA R590 R89C R8A1 R79E R79B R3AD R364 R2AF R253 R4AB R475 R89B R8A0 R69F R693 R79D R79A R8A9 R8AE R3AC R363 R2AE R252 R4AA R474 R89A R89F R69E R692 R79C R799 R8A8 R8AD R3AB R362 R2AD R251 R1AF R145 R59F R585 R69D R691 R79B R798 R91F R92B R8A7 R8AC R3AA R361 R2AC R250 R1AE R144 R7A9 R7A7 R59E R584 R69C R690 R79A R797 R91E R92A R8A6 R8AB R2AB R24F R1AD R143 R7A8 R7A6 R49F R469 R59D R583 R69B R68F R91D R929 R8A5 R8AA R81F R81E R2AA R24E R1AC R142 R6A9 R69D R7A7 R7A5 R49E R468 R59C R582 R69A R68E R91C R928 R8A4 R8A9 R81E R81D R1AB R141 R6A8 R69C R7A6 R7A3 R39F R355 R49D R467 R59B R581 R91B R927 R8A3 R8A8 R81D R81C R1AA R140 R5A9 R58F R6A7 R69B R7A5 R7A2 R71F R71A R39E R354 R49C R466 R59A R580 R91A R926 R8A2 R8A7 R81C R81B R5A8 R58E R6A6 R69A R7A4 R7A1 R71E R719 R39D R353 R29F R243 R49B R465 R8A1 R8A6 R81B R81A R4A9 R473 R5A7 R58D R6A5 R699 R7A3 R7A0 R61F R60F R71D R718 R899 R89E R39C R352 R29E R242 R49A R464 R8A0 R8A5 R81A R819 R4A8 R472 R5A6 R58C R6A4 R698 R7A2 R79F R61E R60E R71C R717 R898 R89D R39B R351 R29D R241 R19F R135 R3A9 R360 R4A7 R471 R5A5 R58B R6A3 R697 R7A1 R79E R51F R4EE R61D R60D R71B R716 R897 R89C R39A R350 R29C R240 R19E R134 R799 R796 R3A8 R35F R4A6 R470 R5A4 R58A R6A2 R696 R7A0 R79D R51E R4ED R61C R60C R71A R715 R896 R89B R29B R23F R19D R133 R798 R795 R3A7 R35E R2A9 R24D R4A5 R46F R5A3 R589 R6A1 R695 R41F R3D6 R51D R4EB R61B R60A R895 R89A R29A R23E R19C R132 R699 R68D R797 R793 R3A6 R35D R2A8 R24C R4A4 R46E R5A2 R588 R6A0 R694 R41E R3D5 R51C R4EA R61A R609 R894 R899 R19B R131 R698 R68C R796 R791 R3A5 R35C R2A7 R24B R1A9 R13F R4A3 R46D R5A1 R587 R31F R2CC R41D R3D4 R51B R4E9 R893 R898 R19A R130 R599 R57F R697 R68B R795 R790 R919 R925 R3A4 R35B R2A6 R24A R1A8 R13E R4A2 R46C R5A0 R586 R31E R2CB R41C R3D3 R51A R4E7 R990 R99F R892 R897 R598 R57E R696 R68A R794 R78F R918 R924 R3A3 R35A R2A5 R249 R1A7 R13D R4A1 R46B R31D R2CA R21F R1C0 R41B R3D2 R891 R896 R499 R463 R597 R57D R695 R689 R793 R78E R917 R923 R819 R818 R3A2 R359 R2A4 R248 R1A6 R13C R4A0 R46A R31C R2C9 R21E R1BF R41A R3D1 R890 R895 R498 R462 R596 R57C R694 R688 R792 R78D R916 R921 R818 R817 R3A1 R358 R2A3 R247 R1A5 R13B R31B R2C8 R21D R1BE R11F R98 R399 R34F R497 R461 R595 R57B R693 R687 R791 R78C R915 R920 R817 R816 R3A0 R356 R2A2 R246 R1A4 R13A R31A R2C7 R21C R1BD R11E R97 R719 R714 R398 R34E R496 R460 R594 R57A R692 R686 R790 R78B R914 R91E R816 R815 R2A1 R245 R1A3 R139 R21B R1BC R11D R96 R718 R713 R397 R34D R299 R23D R495 R45F R593 R579 R691 R685 R913 R91D R815 R814 R2A0 R244 R1A2 R138 R21A R1BB R11C R95 R619 R608 R717 R712 R396 R34C R298 R23C R494 R45E R592 R578 R690 R684 R912 R91C R814 R813 R1A1 R137 R11B R94 R618 R607 R716 R711 R395 R34B R297 R23B R199 R12F R493 R45D R591 R577 R911 R91B R813 R812 R1A0 R136 R11A R93 R519 R4E6 R617 R606 R715 R710 R394 R34A R296 R23A R198 R12E R492 R45C R590 R576 R910 R91A R812 R811 R518 R4E2 R616 R605 R714 R70F R393 R349 R295 R239 R197 R12D R491 R45B R811 R810 R419 R3D0 R517 R4E1 R615 R604 R713 R70E R392 R347 R294 R238 R196 R12C R490 R45A R810 R80F R418 R3CF R516 R4E0 R614 R603 R712 R70D R391 R346 R293 R237 R195 R12B R319 R2C6 R417 R3CE R515 R4DF R613 R602 R711 R70C R390 R344 R292 R236 R194 R12A R318 R2C5 R416 R3CD R514 R4DE R612 R601 R710 R70B R291 R235 R193 R129 RFA R73 R317 R2C4 R219 R1BA R415 R3CC R513 R4DD R611 R600 R290 R234 R192 R128 R316 R2C3 R218 R1B9 R414 R3CB R512 R4DC R610 R5FF R191 R127 REA R63 R315 R2C2 R217 R1B8 R119 R92 R413 R3CA R511 R4DB R190 R126 R314 R2C1 R216 R1B7 R118 R91 R412 R3C9 R510 R4DA RDA R53 R313 R2C0 R215 R1B6 R117 R90 R411 R3C8 R312 R2BF R214 R1B5 R116 R8F R410 R3C7 RCA R43 R311 R2BE R213 R1B4 R115 R8E R310 R2BD R212 R1B3 R114 R8D RBA R33 R211 R1B2 R113 R8C RF9 R72 R210 R1B1 R112 R8B RAA R23 R111 R8A RE9 R62 R110 R89 RD9 R52 RC9 R42 RB9 R32 RF1 R6A RA9 R22 RE1 R5A RD1 R4A RC1 R3A RB1 R2A R9A R6D3 RA1 R9BB R8A R883 R7A R4F7 R6A R438 R5A REE R99 R42D R4A R9B7 R89 R4FF R3A R1CC R79 R7C2 R2A R502 R69 RD0 R1A RE3 R59 R60B R91 R504 R49 R357 R81 RC0 R39 R260 R71 R4F8 R29 R4FD R61 R9C1 R19 R275 R51 R289 R41 R792 R31 R9BE R21 R9BA R11 R529 R98F R99E R98E R99D R98D R99C R88F R894 R98C R99B R88E R893 R98B R99A R88D R891 R78F R78A R98A R999 R88C R890 R78E R789 R88B R88F R68F R683 R78D R788 R88A R88D R68E R682 R78C R787 R58F R575 R68D R681 R78B R786 R90F R919 R58E R574 R68C R680 R78A R785 R90E R918 R48F R459 R58D R573 R68B R67F R90D R916 R80F R80E R48E R458 R58C R572 R68A R67E R90C R915 R80E R80D R38F R343 R48D R457 R58B R571 R90B R913 R80D R80C R70F R70A R989 R998 R38E R342 R48C R456 R58A R570 R90A R912 R80C R80B R70E R709 R988 R997 R38D R341 R28F R233 R48B R455 R80B R80A R60F R5FE R70D R708 R987 R996 R889 R88C R38C R340 R28E R232 R48A R454 R80A R809 R60E R5FD R70C R707 R986 R995 R888 R88B R38B R33F R28D R231 R18F R125 R50F R4D9 R60D R5FC R70B R706 R985 R994 R887 R88A R38A R33E R28C R230 R18E R124 R789 R784 R50E R4D8 R60C R5FB R70A R705 R984 R993 R886 R889 R28B R22F R18D R123 R788 R783 R40F R3C6 R50D R4D7 R60B R5FA R983 R992 R885 R888 R28A R22E R18C R122 R689 R67D R787 R782 R40E R3C5 R50C R4D6 R60A R5F9 R982 R991 R884 R887 R18B R121 R688 R67C R786 R781 R30F R2BC R40D R3C4 R50B R4D5 R981 R990 R883 R886 R18A R120 R589 R56F R687 R67B R785 R780 R909 R911 R30E R2BB R40C R3C3 R50A R4D4 R980 R98F R882 R885 R588 R56E R686 R67A R784 R77F R908 R90F R30D R2BA R20F R1B0 R40B R3C2 R881 R884 R489 R453 R587 R56D R685 R679 R783 R77E R907 R90E R809 R808 R30C R2B9 R20E R1AF R40A R3C1 R880 R882 R488 R452 R586 R56C R684 R678 R782 R77D R906 R90D R808 R807 R30B R2B8 R20D R1AE R10F R88 R389 R33D R487 R451 R585 R56B R683 R677 R781 R77C R905 R90B R807 R806 R30A R2B7 R20C R1AD R10E R87 R709 R704 R388 R33C R486 R450 R584 R56A R682 R676 R780 R77B R904 R90A R806 R805 R20B R1AC R10D R86 R708 R703 R387 R33B R289 R22D R485 R44F R583 R569 R681 R675 R903 R908 R805 R804 R20A R1AB R10C R85 R609 R5F8 R707 R702 R386 R33A R288 R22C R484 R44E R582 R568 R680 R674 R902 R907 R804 R803 R10B R84 R608 R5F7 R706 R701 R385 R338 R287 R22B R189 R11F R483 R44D R581 R567 R901 R906 R803 R802 R10A R83 R509 R4D3 R607 R5F6 R705 R700 R384 R337 R286 R22A R188 R11E R482 R44C R580 R566 R900 R905 R802 R801 R508 R4D2 R606 R5F5 R704 R6FF R383 R336 R285 R229 R187 R11D R481 R44B R801 R800 R409 R3C0 R507 R4D1 R605 R5F3 R703 R6FE R382 R335 R284 R228 R186 R11C R480 R44A R800 R7FF R408 R3BF R506 R4D0 R604 R5F2 R702 R6FD R381 R334 R283 R227 R185 R11B R309 R2B6 R407 R3BE R505 R4CF R603 R5F0 R701 R6FC R380 R333 R282 R226 R184 R11A R308 R2B5 R406 R3BD R504 R4CE R602 R5EF R700 R6FB R281 R225 R183 R119 R307 R2B4 R209 R1AA R405 R3BC R503 R4CD R601 R5ED R280 R224 R182 R118 R306 R2B3 R208 R1A9 R404 R3BB R502 R4CC R600 R5EC R181 R117 R305 R2B2 R207 R1A8 R109 R82 R403 R3BA R501 R4CB R180 R115 R304 R2B1 R206 R1A7 R108 R81 R402 R3B9 R500 R4CA R303 R2B0 R205 R1A4 R107 R80 R401 R3B8 R302 R2AF R204 R1A2 R106 R7F R400 R3B7 R301 R2AE R203 R19E R105 R7E R300 R2AD R202 R19D R104 R7D R201 R19C R103 R7C RF8 R71 R200 R199 R102 R7B R101 R7A RE8 R61 R100 R79 RD8 R51 RC8 R41 RB8 R31 RF0 R69 RA8 R2 RE0 R59 RD0 R49 RC0 R39 RB0 R29 RA0 R91F R98 R40A R88 R7A4 R78 R500 R68 R948 R58 R9B9 R90 R4E4 R48 RD2 R80 R6F0 R38 RB6 R70 R26A R28 R5DF R60 R4F0 R18 R9C3 R50 R1A5 R40 R4F3 R30 R503 R20 R794 R10 RD3 R97F R98E R97E R98D R97D R98C R87F R881 R97C R98B R87E R880 R97B R98A R87D R87F R77F R77A R97A R989 R87C R87E R77E R779 R87B R87D R67F R673 R77D R778 R87A R87C R67E R672 R77C R777 R57F R565 R67D R671 R77B R776 R57E R564 R67C R670 R77A R775 R47F R449 R57D R563 R67B R66F R47E R448 R57C R562 R67A R66E R37F R332 R47D R447 R57B R561 R979 R988 R37E R331 R47C R446 R57A R560 R978 R987 R37D R330 R27F R223 R47B R445 R977 R986 R879 R87B R37C R32F R27E R222 R47A R444 R976 R985 R878 R87A R37B R32E R27D R221 R17F R114 R975 R984 R877 R879 R37A R32D R27C R220 R17E R113 R779 R774 R974 R983 R876 R878 R27B R21F R17D R112 R778 R773 R973 R982 R875 R877 R27A R21E R17C R110 R679 R66D R777 R772 R972 R981 R874 R876 R17B R10F R678 R66C R776 R771 R971 R980 R873 R875 R17A R10E R579 R55F R677 R66B R775 R770 R970 R97F R872 R874 R578 R55E R676 R66A R774 R76F R871 R873 R479 R443 R577 R55D R675 R669 R773 R76E R870 R872 R478 R442 R576 R55C R674 R668 R772 R76D R379 R32C R477 R441 R575 R55B R673 R667 R771 R76C R378 R32B R476 R440 R574 R55A R672 R666 R770 R76B R377 R329 R279 R21D R475 R43F R573 R559 R671 R665 R376 R328 R278 R21C R474 R43E R572 R558 R670 R664 R375 R327 R277 R21B R179 R10D R473 R43D R571 R557 R374 R326 R276 R21A R178 R10C R472 R43A R570 R556 R373 R325 R275 R219 R177 R10B R471 R439 R372 R323 R274 R218 R176 R10A R470 R437 R371 R321 R273 R217 R175 R109 R370 R320 R272 R216 R174 R108 R271 R215 R173 R107 R270 R214 R172 R106 R171 R105 R170 R103 RF7 R70 RE7 R60 RD7 R50 RC7 R40 RB7 R30 RA7 R9A0 R97 R4FB R87 R261 R77 R32A R67 R5E2 R57 R3F9 R47 R9C2 R37 R28B R27 R9BF R17 R42F R8FF R904 R8FE R903 R8FD R902 R7FF R7FE R8FC R901 R7FE R7FD R8FB R900 R7FD R7FC R6FF R6FA R8FA R8FF R7FC R7FB R6FE R6F9 R7FB R7FA R5FF R5E9 R6FD R6F8 R7FA R7F9 R5FE R5E8 R6FC R6F7 R4FF R4C9 R5FD R5E6 R6FB R6F6 R4FE R4C8 R5FC R5E5 R6FA R6F5 R3FF R3B6 R4FD R4C7 R5FB R5E4 R3FE R3B5 R4FC R4C6 R5FA R5E3 R2FF R2AC R3FD R3B4 R4FB R4C5 R8F9 R8FE R2FE R2AB R3FC R3B3 R4FA R4C4 R8F8 R8FD R3FB R3B2 R2FD R2AA R1FF R197 R96F R97E R8F7 R8FC R7F9 R7F8 R3FA R3B1 R2FC R2A9 R1FE R195 R96E R97D R8F6 R8FB R7F8 R7F7 R2FB R2A8 R1FD R194 R96D R97C R8F5 R8FA R86F R871 R2FA R2A7 R1FC R193 R6F9 R6F4 R7F7 R7F6 R96C R97B R8F4 R8F9 R86E R870 R1FB R192 R6F8 R6F3 R7F6 R7F5 R96B R97A R8F3 R8F8 R86D R86F R1FA R191 R5F9 R5E1 R6F7 R6F2 R7F5 R7F4 R76F R76A R96A R979 R8F2 R8F7 R86C R86E R5F8 R5E0 R6F6 R6F1 R7F4 R7F3 R76E R769 R8F1 R8F6 R86B R86D R4F9 R4C3 R5F7 R5DE R6F5 R6EF R7F3 R7F2 R66F R663 R76D R768 R8F0 R8F5 R86A R86C R4F8 R4C2 R5F6 R5DD R6F4 R6ED R7F2 R7F1 R66E R662 R76C R767 R3F9 R3B0 R4F7 R4C1 R5F5 R5DC R6F3 R6EC R7F1 R7F0 R56F R555 R66D R661 R76B R766 R3F8 R3AF R4F6 R4C0 R5F4 R5DA R6F2 R6EB R7F0 R7EF R56E R554 R66C R660 R76A R765 R3F7 R3AE R2F9 R2A6 R4F5 R4BF R5F3 R5D9 R6F1 R6EA R46F R436 R56D R553 R66B R65F R3F6 R3AD R2F8 R2A5 R4F4 R4BE R5F2 R5D8 R6F0 R6E9 R46E R434 R56C R552 R66A R65E R3F5 R3AC R2F7 R2A4 R1F9 R190 R4F3 R4BD R5F1 R5D7 R36F R31F R46D R433 R56B R551 R969 R978 R3F4 R3AB R2F6 R2A3 R1F8 R18E R4F2 R4BC R5F0 R5D6 R36E R31E R46C R432 R56A R550 R968 R977 R3F3 R3AA R2F5 R2A2 R1F7 R18D R4F1 R4BB R36D R31D R26F R213 R46B R431 R967 R976 R869 R86B R3F2 R3A9 R2F4 R2A1 R1F6 R18C R4F0 R4BA R36C R31C R26E R212 R46A R430 R966 R975 R868 R86A R3F1 R3A8 R2F3 R2A0 R1F5 R18B R36B R31B R26D R211 R16F R102 R965 R974 R867 R869 R3F0 R3A7 R2F2 R29F R1F4 R18A R36A R31A R26C R210 R16E R101 R769 R764 R964 R973 R866 R868 R2F1 R29E R1F3 R189 R26B R20F R16D R100 R768 R763 R963 R972 R865 R867 R2F0 R29D R1F2 R188 R26A R20E R16C RFF R669 R65D R767 R762 R962 R971 R864 R865 R1F1 R187 R16B RFE R668 R65C R766 R761 R961 R970 R863 R864 R1F0 R186 R16A RFD R569 R54F R667 R65B R765 R760 R960 R96F R862 R863 R568 R54E R666 R65A R764 R75F R861 R862 R469 R42E R567 R54D R665 R659 R763 R75E R860 R861 R468 R42C R566 R54C R664 R658 R762 R75D R369 R319 R467 R42B R565 R54B R663 R657 R761 R75C R368 R318 R466 R42A R564 R54A R662 R656 R760 R75B RFF R78 R367 R317 R269 R20D R465 R429 R563 R549 R661 R655 R366 R313 R268 R20C R464 R428 R562 R548 R660 R654 REF R68 R365 R312 R267 R20B R169 RFC R463 R427 R561 R547 R364 R311 R266 R20A R168 RFB R462 R426 R560 R546 RDF R58 R363 R310 R265 R209 R167 RFA R461 R425 R362 R30F R264 R208 R166 RF9 R460 R423 RCF R48 R361 R30E R263 R207 R165 RF8 R360 R30D R262 R206 R164 RF7 RBF R38 R261 R205 R163 RF5 R260 R204 R162 RF4 RAF R28 R161 RF3 R160 RF2 RF6 R6F RE6 R5F RD6 R4F RC6 R3F RB6 R2F R9F R9C4 RA6 RB R8F R5F1 R7F R931 R6F R52B R5F R6E6 R4F R909 R3F R322 R2F RE6 R1F RC5 R96 R4EC R86 R910 R76 R4EF R66 R611 R56 RBD R46 R404 R36 RC3 R26 R858 R16 R266 50 A12 A10 A2A A28 A15 A13 A7 A37 A2D A2B A18 A16 A6 AB A1A A18 A5 A0 A1D A1B A4 AA A30 A3C A3 A6 A2 A9 A20 A1E A1 A1 A23 A21 A26 A24 A0 A36 A29 A27 A10 AE A13 A11 A2B A29 A16 A14 A2E A3D A19 A17 A1B A19 A1E A1C AF A4 AE A2 A31 A34 AD AD AC AC A21 A1F A24 A22 AB A3B A27 A25 AA A3A A11 AF A14 A12 A2C A2A A17 A15 A2F A32 A1C A1A A1F A1D A22 A20 A25 A23 A9 A39 A28 A26 A8 A38 168 W20 W20 W9F W9F W10 W10 W8F W8F W7F W7F W9E W9E W6F W6F W8E W8E W5F W5F W7E W7E W9D W9D W4F W4F W6E W6E W8D W8D W3F W3F W5E W5E W7D W7D W2F W2F W9C W9C W4E W4E W6D W6D W1F W1F W8C W8C W3E W3E W5D W5D W7C W7C W2E W2E W9B W9B W4D W4D W1E W1E W6C W6C W8B W8B W3D W3D W5C W5C W7B W7B W2D W2D W9A W9A W4C W4C W6B W6B W1D W1D W8A W8A W3C W3C W5B W5B W7A W7A W2C W2C W4B W4B W6A W6A W1C W1C W3B W3B W5A W5A W2B W2B W4A W4A W1B W1B W3A W3A W2A W2A W1A W1A WA7 WA7 WA6 WA6 W99 W99 W89 W89 WA5 WA5 W79 W79 W98 W98 W69 W69 W88 W88 W59 W59 WA4 WA4 W78 W78 W97 W97 W49 W49 W68 W68 W87 W87 W39 W39 W58 W58 WA3 WA3 W77 W77 W29 W29 W96 W96 W48 W48 W67 W67 W19 W19 W86 W86 W38 W38 W57 W57 WA2 WA2 W76 W76 W28 W28 W95 W95 W47 W47 W66 W66 W18 W18 W85 W85 W37 W37 W56 W56 WA1 WA1 W75 W75 W27 W27 W94 W94 W46 W46 W65 W65 W17 W17 W84 W84 WF WF W36 W36 W55 W55 WE WE WA0 WA0 W74 W74 WD WD W26 W26 W93 W93 W45 W45 WC WC W16 W16 WB WB W64 W64 W83 W83 W35 W35 WA WA W54 W54 W73 W73 W25 W25 W92 W92 W44 W44 W63 W63 W15 W15 W82 W82 W34 W34 W53 W53 W72 W72 W24 W24 W91 W91 W43 W43 W9 W9 W14 W14 W8 W8 W62 W62 W81 W81 W33 W33 W7 W7 W52 W52 W6 W6 W71 W71 W23 W23 W5 W5 W90 W90 W42 W42 W4 W4 W61 W61 W13 W13 W3 W3 W80 W80 W32 W32 W2 W2 W51 W51 W1 W1 W70 W70 W22 W22 W0 W0 W41 W41 W60 W60 W12 W12 W31 W31 W50 W50 W21 W21 W40 W40 W11 W11 W30 W30 1 A3E CoreGeometryIOObjects 939 O2EF O2DF O2EE O2DE O2ED O2DD O1EF O1FD O2CF O2C2 O2EC O2DC O1EE O1FC O2CE O1DC O2EB O2DB O1ED O1FB O2CD O2C1 O1CF O1DD O2EA O2DA O2AF O2A7 O1EC O1FA O2CC O2C0 O1CE O1DC O2AE O1D2 O1EB O1F9 O2CB O2BF O1CD O1DB O2AD O2A6 O1EA O1F8 O1AF O1BD O2CA O207 O1CC O1DA O3AA O383 O2AC O22F O1AE O1BC O1CB O1D9 O2AB O1C1 O1AD O1BB O1CA O1D8 O2AA O1CD O1AC O1BA O1AB O1B9 O1AA O1B8 O39F O378 O2E9 O2D9 O39E O377 O2E8 O2D8 O39D O376 O2E7 O2D7 O29F O29B O1E9 O1F7 O37F O35C O2C9 O2BE O3A9 O382 O39C O375 O2E6 O2D6 O29E O29A O1E8 O1F6 O37E O35B O2C8 O2BD O3A8 O381 O39B O2C0 O2E5 O1DE O29D O299 O1E7 O1F5 O19F O1AD O37D O35A O2C7 O2BC O27F O179 O1C9 O1D7 O3A7 O380 O39A O374 O35F O33F O2E4 O2D5 O2A9 O2A5 O29C O298 O1E6 O1F4 O19E O1AC O37C O359 O2C6 O2BB O27E O27E O1C8 O1D6 O3A6 O37F O35E O27F O2E3 O2D4 O2A8 O2A4 O29B O297 O1E5 O1F3 O19D O1AB O37B O179 O2C5 O2BA O27D O27D O1C7 O1D5 O17F O18D O3A5 O37E O35D O33E O2E2 O2D3 O2A7 O2A3 O29A O296 O25F O265 O1E4 O1F2 O1A9 O1B7 O19C O1AA O37A O358 O33F O323 O2C4 O2B9 O27C O27C O1C6 O1D4 O17E O18C O3A4 O37D O35C O33D O2E1 O2D2 O2A6 O2A2 O25E O264 O1E3 O1F1 O1A8 O1B6 O19B O1A9 O33E O322 O2C3 O2B8 O27B O27B O1C5 O1D3 O17D O18B O3A3 O37C O35B O33C O2A5 O2A1 O2E0 O2D1 O25D O263 O1E2 O1F0 O1A7 O1B5 O19A O1A8 O15F O16D O33D O321 O2C2 O2B7 O27A O27A O23F O249 O1C4 O1D2 O17C O18A O3A2 O37B O35A O284 O31F O307 O2A4 O2A0 O25C O262 O1E1 O1EF O1A6 O1B4 O15E O16C O33C O281 O2C1 O1DB O23E O248 O1C3 O1D1 O17B O189 O3A1 O37A O31E O306 O2A3 O29F O25B O261 O1E0 O1EE O1A5 O1B3 O15D O16B O33B O320 O2C0 O2B6 O23D O247 O1C2 O1D0 O17A O188 O13F O14D O3A0 O379 O31D O305 O2A2 O29E O25A O260 O21F O113 O1A4 O1B2 O15C O16A O33A O31F O23C O246 O1C1 O1CF O13E O14C O399 O373 O31C O304 O2A1 O29D O21E O229 O1A3 O1B1 O15B O169 O23B O245 O1C0 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O2BA O2B0 O1BC O1CA O1BB O1C9 O1BA O1C8 O2F9 O2E6 O2F8 O2E5 O2F7 O2E4 O1F9 O207 O38F O36A O2D9 O2CB O2F6 O1F2 O1F8 O206 O38E O1D3 O2D8 O2CA O2F5 O2E3 O1F7 O205 O38D O369 O2D7 O2C9 O28F O18E O1D9 O1E7 O36F O34F O2F4 O2E2 O2B9 O2AF O1F6 O204 O38C O368 O2D6 O2C8 O28E O28B O1D8 O1E6 O36E O34E O2F3 O287 O2B8 O2AE O1F5 O203 O38B O2CF O2D5 O120 O28D O28A O1D7 O1E5 O18F O19D O36D O34D O2F2 O1BD O2B7 O2AD O26F O271 O1F4 O202 O1B9 O1C7 O38A O367 O34F O331 O2D4 O2C7 O28C O289 O1D6 O1E4 O18E O19C O36C O34C O2F1 O2E1 O2B6 O2AC O26E O270 O1F3 O201 O1B8 O1C6 O34E O330 O2D3 O2C6 O28B O288 O1D5 O1E3 O18D O19B O36B O34B O2F0 O2E0 O2B5 O2AB O26D O1BD O1F2 O200 O1B7 O1C5 O16F O17D O34D O32F O2D2 O2C5 O28A O287 O24F O256 O1D4 O1E2 O18C O19A O36A O34A O32F O315 O2B4 O2AA O26C O26F O1F1 O1FF O1B6 O1C4 O16E O17C O34C O32E O2D1 O2C4 O24E O255 O1D3 O1E1 O18B O199 O32E O314 O2B3 O2A9 O26B O26E O1F0 O1FE O1B5 O1C3 O16D O17B O34B O274 O2D0 O2C3 O24D O156 O1D2 O1E0 O18A O198 O14F O15D O32D O313 O2B2 O190 O26A O26D O22F O239 O1B4 O1C2 O16C O17A O34A O32D O30F O2FA O24C O254 O1D1 O1DF O14E O15C O32C O312 O2B1 O2A8 O22E O238 O1B3 O1C1 O16B O179 O30E O2F9 O24B O1D1 O1D0 O1DE O14D O15B O32B O311 O2B0 O1E0 O22D O237 O1B2 O1C0 O16A O178 O12F O13D O30D O2F8 O24A O253 O20F O21D O14C O15A O32A O310 O22C O236 O1B1 O1BF O12E O13C O389 O366 O30C O2F7 O20E O21C O14B O159 O22B O235 O1B0 O1BE O12D O13B O388 O365 O30B O2F6 O20D O21B O14A O158 O10F O11D O22A O234 OFF O10D O12C O13A O387 O364 O30A O209 O289 O286 O20C O21A O10E O11C O369 O349 O12B O139 O386 O363 O288 O285 O20B O219 O10D O11B O368 O348 OEF OFD O12A O138 O385 O362 O287 O284 O20A O218 OFD O10B O189 O197 O10C O11A O367 O347 O269 O22C O384 O361 O349 O32C O286 O283 O188 O196 O10B O119 O366 O346 O268 O186 ODF OED O383 O360 O348 O32B O285 O282 OED OFB O187 O195 O10A O118 O365 O345 O267 O26C OFB O109 O169 O177 O382 O35F O347 O285 O284 O281 O249 O252 O186 O194 O364 O344 O329 O30F O266 O26B OCF ODD O168 O176 O381 O35E O346 O32A O283 O280 O248 O251 ODD OEB O185 O193 O363 O343 O328 O30E O265 O26A OEB OF9 O167 O175 O380 O35D O345 O329 O282 O27F O247 O250 O184 O192 O149 O157 O362 O342 O327 O294 O264 O269 O229 O233 OBF OCD O166 O174 O344 O328 O309 O2F5 O281 O1D4 O246 O24F OCD ODB O183 O191 O148 O156 O361 O341 O326 O30D O263 O268 O228 O232 ODB OE9 O165 O173 O343 O327 O308 O2F4 O280 O181 O245 O24E O182 O190 O147 O155 O360 O340 O325 O30C O262 O1D8 O227 O231 OAF OBD O164 O172 O129 O137 O342 O326 O307 O2F3 O244 O24D O209 O217 OBD OCB O181 O18F O146 O154 O324 O30B O261 O267 O226 O230 OCB OD9 O163 O171 O128 O136 O341 O325 O306 O2F2 O243 O24C O208 O216 O180 O18E O145 O153 O323 O30A O260 O266 O225 O22F O162 O170 O127 O134 O340 O324 O305 O229 O242 O24B O207 O215 OAD OBB O144 O152 O109 O117 O322 O309 O224 O22E OBB OC9 O161 O16F O126 O133 O304 O2F1 O241 O24A O206 O214 O143 O151 O108 O116 O321 O308 O223 O22D O160 O16E O125 O132 O303 O2F0 O240 O148 O205 O213 O142 O150 O107 O115 O320 O231 O222 O22C OAB OB9 O124 O131 O302 O2EF O204 O212 O141 O14F O106 O114 O221 O22B O123 O130 O301 O2EE O203 O211 O140 O14E O105 O113 O220 O22A O122 O12F O300 O2ED O202 O210 OF8 O106 O104 O112 OF O1D O121 O12E O201 O20F O103 O111 OE O1C O120 O12D OE8 OF6 O102 O110 O200 O20E OF6 O104 OD O1B O101 O10F OC O1A OD8 OE6 O100 O10E OE6 OF4 OB O19 OF4 O102 OA O18 OC8 OD6 OD6 OE4 OE4 OF2 OF2 O100 OB8 OC6 O9F OAD OC6 OD4 OD4 OE2 OE2 OF0 OA8 OB6 OF0 OFE O8F O9D OB6 OC4 O9D OAB OC4 OD2 OD2 OE0 OE0 OEE O7F O8D OA6 OB4 O8D O9B OB4 OC2 O9B OA9 O9 O17 OC2 OD0 OD0 ODE O6F O7D O8 O16 O7D O8B OA4 OB2 O8B O99 O7 O15 OB2 OC0 OC0 OCE O5F O6D O6 O14 O6D O7B O7B O89 O5 O13 OA2 OB0 OB0 OBE O4 O12 O4F O5D O5D O6B O3 O11 O6B O79 OA0 OAE O3F O4D O2 O6AF O4D O5B O5B O69 O1 O135 O2F O3D O0 O80 O3D O4B O4B O59 O1F O2D O2D O3B O3B O49 O98 OA6 O1D O2B O2B O39 O88 O96 O96 OA4 O1B O29 O78 O86 O86 O94 O94 OA2 O68 O76 O76 O84 O84 O92 O92 OA0 O58 O66 O66 O74 O74 O82 O82 O90 O48 O56 O90 O9E O56 O64 O64 O72 O72 O80 O38 O46 O80 O8E O46 O54 O54 O62 O62 O70 O28 O36 O70 O7E O36 O44 O44 O52 O52 O60 O18 O26 O60 O6E O26 O34 O34 O42 O42 O50 O50 O5E O16 O24 O24 O32 O32 O40 O40 O4E O14 O22 O22 O30 O30 O3E O12 O20 O20 O2E O10 O1E W11F 8 0 W62 W60 W11D W11C W10 W11B W61 W63 1 A35 4368 57168 0 C2 W0 8 0 W1 0 2 A1 1 O432 1600 72 2 A0 r RB W2 0 2 A1 4 O3D5 1600 3416 2 O3 1600 3728 2 O3F4 384 3416 2 O4 1600 3728 2 A0 r R9 W3 0 2 A1 2 O415 264 0 1 O3FB 232 0 0 A0 r R9AC W4 0 2 A1 2 O3FC 1248 0 0 O3FB 1248 0 0 A0 r R9A8 W5 0 2 A1 1 O0 328 1880 0 A0 r R1 W6 0 2 A1 2 O3E5 664 0 0 O3FB 664 0 0 A0 r R9AD W7 0 2 A1 6 O3C7 1600 1312 2 O3C4 0 1312 0 O3 1600 672 2 O4 1600 672 2 O3C5 288 1312 2 O3C3 1600 1312 2 A0 r RA W8 0 2 A1 1 O42A 1600 352 2 A0 r RC 4 A0 r R9C9 "IOTstPad" A34 O395 AC O395 A32 a A3F GetAndFlatten R9C6 9 W9 13 0 W1 W2 WA 0 0 W5 W6 WB 0 1 A0 r R9CA "push" WC 0 1 A0 r R9CB "pull" WD 0 0 WE 0 0 W4 W3 W7 W8 WF 4 0 W8 W1 WA W3 0 C3 W0 4 0 W1 0 2 A0 r RC A40 PortData l agg n 0 W2 0 2 A0 r RB A40 l agg n 0 W3 0 2 A0 r R9CC "Input" A40 l agg n 0 W4 0 2 A0 r R9CD "nOutput" A40 l agg d 0 3 A0 r R9CE "Inverter" A41 RoseBehave r R9CE A42 CoreCutLabel lor 1 R9CF "JustAboveTransistors" R9C6 2 W0 W5 3 0 W3 W1 W4 0 C4 W0 3 0 W1 0 1 A0 r R9D0 "gate" W2 0 1 A0 r R9D1 "ch1" W3 0 1 A0 r R9D2 "ch2" 1 A43 RoseTransistorSize d R9D3 "Transistor" pE 2 100 W6 3 0 W3 W4 W2 0 C5 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 nE 2 40 W10 3 0 W5 W8 WA 0 C6 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 0 R9D3 pE 2 18 W11 3 0 W5 WA W1 0 C7 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 0 R9D3 nE 2 35 W12 3 0 WB W7 W5 0 C8 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 0 R9D3 nE 2 252 W13 5 0 W8 W1 WE WD WB 0 C9 W0 5 0 W1 0 1 A0 r RC W2 0 1 A0 r RB W3 0 1 A0 r R9D4 "Input0" W4 0 1 A0 r R9D5 "Input1" W5 0 1 A0 r R9CD 1 A0 r R9D6 "NOr2" R9C6 1 W6 6 0 W1 W2 W3 W4 W5 W7 2 0 W3 W4 W8 4 0 W1 W2 W7 W5 0 CA W0 4 0 W1 0 1 A0 r RC W2 0 1 A0 r RB W3 2 1 A0 r R9CC W4 0 0 W5 0 0 W6 0 2 A0 r R9CD A40 b agg d 0 3 A0 r R9D7 "NOr" A41 r R9D7 A42 lor 1 R9CF R9C6 4 W7 5 0 W1 W2 W3 W6 W8 1 1 A0 r R9D8 "stack" W9 0 0 WA 3 0 W5 W6 W2 0 CB W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 nE 2 12 WB 3 0 W5 W9 W6 0 CC W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 pE 2 60 WC 3 0 W4 W6 W2 0 CB WD 3 0 W4 W1 W9 0 CC W14 3 0 WC W5 W2 0 C8 W15 4 0 W8 W1 W4 WE 0 CD W0 4 0 W1 0 2 A0 r RC A40 l agg n 0 W2 0 2 A0 r RB A40 l agg n 0 W3 0 2 A0 r R9CC A40 l agg n 0 W4 0 2 A0 r R9CD A40 l agg d 0 3 A0 r R9CE A41 r R9CE A42 lor 1 R9CF R9C6 2 W0 W5 3 0 W3 W1 W4 0 CE W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 pE 2 25 W6 3 0 W3 W4 W2 0 CF W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 nE 2 10 W16 5 0 W8 W1 W4 WD WC 0 C9 W17 4 0 W8 W1 W6 WD 0 C10 W0 4 0 W1 0 2 A0 r RC A40 l agg n 0 W2 0 2 A0 r RB A40 l agg n 0 W3 0 2 A0 r R9CC A40 l agg n 0 W4 0 2 A0 r R9CD A40 l agg d 0 3 A0 r R9CE A41 r R9CE A42 lor 1 R9CF R9C6 2 W0 W5 3 0 W3 W1 W4 0 C11 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 pE 2 10 W6 3 0 W3 W4 W2 0 C12 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 nE 2 4 W120 8 0 W62 W60 W11A W119 W11 W11B W61 W63 1 A35 5968 57168 0 C2 W121 8 0 W62 W60 W118 W117 W12 W11B W61 W63 1 A35 7568 57168 0 C2 W122 8 0 W62 W60 W116 W115 W13 W11B W61 W63 1 A35 9168 57168 0 C2 W123 4 0 W62 W60 W61 W63 1 A35 10768 57168 0 C13 W0 4 0 W1 0 2 A1 9 O467 352 0 2 O432 1600 72 2 O469 352 0 2 O467 752 0 2 O469 752 0 2 O467 1168 0 2 O469 1168 0 2 O467 1568 0 2 O469 1568 0 2 A0 r RB W2 0 2 A1 3 O5 1600 3152 2 O6 1600 3152 2 O7 328 1880 0 A0 r R9 W3 0 2 A1 2 O46E 1600 672 2 O441 1600 672 2 A0 r RA W4 0 2 A1 1 O42A 1600 352 2 A0 r RC 4 A0 r R9D9 "PadGndPad" A34 O465 AC O465 A32 a A44 Get R9C6 0 W5 4 0 W1 W2 W3 W4 W124 8 0 W62 W60 W114 W113 W14 W11B W61 W63 1 A35 12368 57168 0 C2 W125 8 0 W62 W60 W112 W111 W15 W11B W61 W63 1 A35 13968 57168 0 C2 W126 8 0 W62 W60 W110 W10F W16 W11B W61 W63 1 A35 15568 57168 0 C2 W127 4 0 W62 W60 W61 W63 1 A35 17168 57168 0 C14 W0 4 0 W1 0 2 A1 1 O432 1600 72 2 A0 r RB W2 0 2 A1 2 O5 1600 3152 2 O6 1600 3152 2 A0 r R9 W3 0 2 A1 3 OB 328 1880 0 O441 1600 672 2 O46E 1600 672 2 A0 r RA W4 0 2 A1 9 O474 1168 0 2 O475 1168 0 2 O474 352 0 2 O475 352 0 2 O42A 1600 352 2 O475 752 0 2 O474 752 0 2 O475 1568 0 2 O474 1568 0 2 A0 r RC 4 A0 r R9DA "PadVddPad" A34 O472 AC O472 A32 a A44 R9C6 0 W5 4 0 W1 W2 W3 W4 W128 6 0 W62 W60 W64 W10E W61 W63 1 A35 18768 57168 0 C15 W0 6 0 W1 0 2 A1 1 O432 1600 72 2 A0 r RB W2 0 2 A1 2 O3 1600 3728 2 O4 1600 3728 2 A0 r R9 W3 0 2 A1 1 O0 320 1880 0 A0 r R1 W4 0 2 A1 2 O3A9 688 0 0 O3FB 688 0 0 A0 r R9AC W5 0 2 A1 4 O448 1600 1488 2 O448 0 1488 0 O461 1600 672 2 O441 1600 672 2 A0 r RA W6 0 2 A1 1 O42A 1600 352 2 A0 r RC 4 A0 r R9DB "InPad" A34 O433 AC O433 A32 a A44 R9C6 3 W7 7 0 W1 W2 W8 0 0 W3 W4 W5 W6 W9 4 0 W6 W1 W8 W4 0 C16 W0 4 0 W1 0 2 A0 r RC A40 l agg n 0 W2 0 2 A0 r RB A40 l agg n 0 W3 0 2 A0 r R9CC A40 l agg n 0 W4 0 2 A0 r R9CD A40 l agg d 0 3 A0 r R9CE A41 r R9CE A42 lor 1 R9CF R9C6 2 W0 W5 3 0 W3 W1 W4 0 C17 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 pE 2 100 W6 3 0 W3 W4 W2 0 C18 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 nE 2 40 WA 3 0 W3 W6 W8 0 C19 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 0 R9D3 pE 2 20 WB 3 0 W3 W8 W1 0 C1A W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 0 R9D3 nE 2 40 W129 8 0 W62 W60 W10D W10C W17 W11B W61 W63 1 A35 20368 57168 0 C2 W12A 8 0 W62 W60 W10B W10A W18 W11B W61 W63 1 A35 21968 57168 0 C2 W12B 8 0 W62 W60 W109 W108 W19 W11B W61 W63 1 A35 23568 57168 0 C2 W12C 8 0 W62 W60 W107 W106 W1A W11B W61 W63 1 A35 25168 57168 0 C2 W12D 8 0 W62 W60 W105 W104 W1B W11B W61 W63 1 A35 26768 57168 0 C2 W12E 4 0 W62 W60 W61 W63 1 A35 28368 57168 0 C1B W0 4 0 W1 0 2 A1 2 O48C 0 72 0 O48B 1600 64 1 A0 r RB W2 0 2 A1 2 O5 1600 3152 2 O6 1600 3152 2 A0 r R9 W3 0 2 A1 3 O46E 1600 672 2 O48D 0 672 0 O48D 1600 672 1 A0 r RA W4 0 2 A1 9 O48E 1368 0 2 O467 1368 0 2 O48E 552 0 2 O467 552 0 2 O490 0 352 0 O467 968 0 2 O48E 968 0 2 O490 1312 352 0 OD 328 1880 0 A0 r RC 4 A0 r R9DC "VddPad" A34 O489 AC O489 A32 a A44 R9C6 0 W5 4 0 W1 W2 W3 W4 W12F 4 0 W62 W60 W61 W63 1 A35 29968 57168 0 C13 W130 4 0 W62 W60 W61 W63 1 A35 31568 57168 0 C1C W0 4 0 W1 0 2 A1 10 O469 1568 0 2 O467 1568 0 2 O469 1168 0 2 O467 1168 0 2 O467 352 0 2 O432 1600 72 2 O469 352 0 2 O467 752 0 2 O469 752 0 2 OC 312 1880 0 A0 r RB W2 0 2 A1 2 O5 1600 3152 2 O6 1600 3152 2 A0 r R9 W3 0 2 A1 3 O46E 1600 672 2 O48D 0 672 0 O48D 1600 672 1 A0 r RA W4 0 2 A1 2 O495 1600 352 1 O495 0 352 0 A0 r RC 4 A0 r R9DD "GndPad" A34 O493 AC O493 A32 a A44 R9C6 0 W5 4 0 W1 W2 W3 W4 W131 8 0 W62 W60 W103 W102 W1C W11B W61 W63 1 A35 33168 57168 0 C2 W132 8 0 W62 W60 W101 W100 W1D W11B W61 W63 1 A35 34768 57168 0 C2 W133 8 0 W62 W60 WFF WFE W1E W11B W61 W63 1 A35 36368 57168 0 C2 W134 8 0 W62 W60 WFD WFC W1F W11B W61 W63 1 A35 37968 57168 0 C2 W135 8 0 W62 W60 WFB WFA W20 W11B W61 W63 1 A35 39568 57168 0 C2 W136 8 0 W62 W60 WF9 WF8 W21 W11B W61 W63 1 A35 41168 57168 0 C2 W137 4 0 W62 W60 W61 W63 1 A35 42768 57168 0 C14 W138 8 0 W62 W60 WF7 WF6 W65 W11B W61 W63 1 A35 44368 57168 0 C2 W139 8 0 W62 W60 WF5 WF4 W3E WF3 W61 W63 1 A35 45968 57168 0 C2 W13A 8 0 W62 W60 WF2 WF1 W3F WF3 W61 W63 1 A35 47568 57168 0 C2 W13B 4 0 W62 W60 W61 W63 1 A35 49168 57168 0 C13 W13C 8 0 W62 W60 WF0 WEF W40 WF3 W61 W63 1 A35 50768 57168 0 C2 W13D 8 0 W62 W60 WEE WED W41 WF3 W61 W63 1 A35 52368 57168 0 C2 W13E 8 0 W62 W60 WEC WEB W42 WF3 W61 W63 1 A35 53968 57168 0 C2 W13F 8 0 W62 W60 WEA WE9 W43 WF3 W61 W63 1 A35 55568 57168 0 C2 W140 4 0 W62 W60 W61 W63 1 A35 57168 57168 0 C1D W0 4 0 W1 0 2 A1 2 O38B 320 72 2 O38B 320 320 4 A0 r RB W2 0 2 A1 4 O8 3152 0 0 O9 3800 3152 2 OA 4368 0 2 OA 0 3152 0 A0 r R9 W3 0 2 A1 4 O390 672 0 0 O387 1312 672 2 O388 0 672 0 O388 1552 0 2 A0 r RA W4 0 2 A1 2 O38C 640 600 4 O389 640 352 2 A0 r RC 4 A0 r R9DE "CornerPad" A34 O385 AC O385 A32 a A44 R9C6 0 W5 4 0 W1 W2 W3 W4 W141 6 0 W62 W60 W30 WE8 W61 W63 1 A35 57168 57168 6 C15 W142 6 0 W62 W60 W31 WE7 W61 W63 1 A35 57168 55568 6 C15 W143 8 0 W62 W60 WE6 WE5 W44 WF3 W61 W63 1 A35 57168 53968 6 C2 W144 8 0 W62 W60 WE4 WE3 W45 WF3 W61 W63 1 A35 57168 52368 6 C2 W145 4 0 W62 W60 W61 W63 1 A35 57168 50768 6 C13 W146 8 0 W62 W60 WE2 WE1 W46 WF3 W61 W63 1 A35 57168 49168 6 C2 W147 8 0 W62 W60 WE0 WDF W47 WF3 W61 W63 1 A35 57168 47568 6 C2 W148 4 0 W62 W60 W61 W63 1 A35 57168 45968 6 C14 W149 8 0 W62 W60 WDE WDD W48 WF3 W61 W63 1 A35 57168 44368 6 C2 W14A 8 0 W62 W60 WDC WDB W49 WF3 W61 W63 1 A35 57168 42768 6 C2 W14B 8 0 W62 W60 WDA WD9 W4A WF3 W61 W63 1 A35 57168 41168 6 C2 W14C 8 0 W62 W60 WD8 WD7 W4B WF3 W61 W63 1 A35 57168 39568 6 C2 W14D 8 0 W62 W60 WD6 WD5 W4C WF3 W61 W63 1 A35 57168 37968 6 C2 W14E 8 0 W62 W60 WD4 WD3 W4D WF3 W61 W63 1 A35 57168 36368 6 C2 W14F 6 0 W62 W60 W66 WD2 W61 W63 1 A35 57168 34768 6 C15 W150 4 0 W62 W60 W61 W63 1 A35 57168 33168 6 C1C W151 4 0 W62 W60 W61 W63 1 A35 57168 31568 6 C13 W152 6 0 W62 W60 W67 WD1 W61 W63 1 A35 57168 29968 6 C15 W153 4 0 W62 W60 W61 W63 1 A35 57168 28368 6 C1B W154 6 0 W62 W60 W68 WD0 W61 W63 1 A35 57168 26768 6 C15 W155 6 0 W62 W60 W32 WCF W61 W63 1 A35 57168 25168 6 C15 W156 7 0 W62 W60 WCE W69 W62 W61 W63 1 A35 57168 23568 6 C1E W0 7 0 W1 0 2 A1 1 O432 1600 72 2 A0 r RB W2 0 2 A1 4 O3D5 1600 3416 2 O3 1600 3728 2 O3F4 384 3416 2 O4 1600 3728 2 A0 r R9 W3 0 2 A1 2 O3E5 664 0 0 O3FB 664 0 0 A0 r R9AD W4 0 2 A1 1 O2 328 1880 0 A0 r R1 W5 0 2 A1 2 O3FC 1248 0 0 O3FB 1248 0 0 A0 r R9A8 W6 0 2 A1 6 O3C7 1600 1312 2 O3C4 0 1312 0 O3 1600 672 2 O4 1600 672 2 O3C5 288 1312 2 O3C3 1600 1312 2 A0 r RA W7 0 2 A1 1 O42A 1600 352 2 A0 r RC 4 A0 r R9DF "TristatePad" A34 O46F AC O46F A32 a A3F R9C6 9 W8 13 0 W1 W2 W4 W9 0 1 A0 r R9CA WA 0 0 WB 0 1 A0 r R9CB WC 0 0 W5 W3 WD 0 2 A36 a A36 A0 r R9CD WE 0 0 W6 W7 WF 4 0 W7 W1 WE WD 0 C1F W0 4 0 W1 0 2 A0 r RC A40 l agg n 0 W2 0 2 A0 r RB A40 l agg n 0 W3 0 2 A0 r R9CC A40 l agg n 0 W4 0 2 A0 r R9CD A40 l agg d 0 3 A0 r R9CE A41 r R9CE A42 lor 1 R9CF R9C6 2 W0 W5 3 0 W3 W1 W4 0 C20 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 pE 2 100 W6 3 0 W3 W4 W2 0 C21 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 nE 2 40 W10 3 0 W4 W7 WE 0 C6 W11 3 0 W4 WE W1 0 C22 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 0 R9D3 nE 2 35 W12 3 0 W9 W6 W4 0 C23 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 0 R9D3 nE 2 252 W13 5 0 W7 W1 WA WC W9 0 C9 W14 3 0 WB W4 W2 0 C23 W15 4 0 W7 W1 W5 WA 0 C24 W0 4 0 W1 0 2 A0 r RC A40 l agg n 0 W2 0 2 A0 r RB A40 l agg n 0 W3 0 2 A0 r R9CC A40 l agg n 0 W4 0 2 A0 r R9CD A40 l agg d 0 3 A0 r R9CE A41 r R9CE A42 lor 1 R9CF R9C6 2 W0 W5 3 0 W3 W1 W4 0 C25 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 pE 2 25 W6 3 0 W3 W4 W2 0 C26 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 nE 2 10 W16 5 0 W7 W1 W5 WC WB 0 C9 W17 4 0 W7 W1 W3 WC 0 C27 W0 4 0 W1 0 2 A0 r RC A40 l agg n 0 W2 0 2 A0 r RB A40 l agg n 0 W3 0 2 A0 r R9CC A40 l agg n 0 W4 0 2 A0 r R9CD A40 l agg d 0 3 A0 r R9CE A41 r R9CE A42 lor 1 R9CF R9C6 2 W0 W5 3 0 W3 W1 W4 0 C28 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 pE 2 10 W6 3 0 W3 W4 W2 0 C29 W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 1 A43 d R9D3 nE 2 4 W157 6 0 W62 W60 W6A WCD W61 W63 1 A35 57168 21968 6 C15 W158 6 0 W62 W60 W33 WCC W61 W63 1 A35 57168 20368 6 C15 W159 6 0 W62 W60 W34 WCB W61 W63 1 A35 57168 18768 6 C15 W15A 4 0 W62 W60 W61 W63 1 A35 57168 17168 6 C14 W15B 6 0 W62 W60 W35 WCA W61 W63 1 A35 57168 15568 6 C15 W15C 6 0 W62 W60 WC9 W6B W61 W63 1 A35 57168 13968 6 C2A W0 6 0 W1 0 2 A1 1 O432 1600 72 2 A0 r RB W2 0 2 A1 4 O3D5 1600 3416 2 O3 1600 3728 2 O3F4 384 3416 2 O4 1600 3728 2 A0 r R9 W3 0 2 A1 2 O483 1480 0 0 O3FB 1480 0 0 A0 r R9A8 W4 0 2 A1 1 OE 328 1880 0 A0 r R1 W5 0 2 A1 6 O3C4 0 1312 0 O3 1600 672 2 O4 1600 672 2 O3C5 288 1312 2 O3C3 1600 1312 2 O3C7 1600 1312 2 A0 r RA W6 0 2 A1 2 O464 1600 608 2 O42A 1600 352 2 A0 r RC 4 A0 r R9E0 "OutPad" A34 O476 AC O476 A32 a A3F R9C6 4 W7 8 0 W1 W2 W4 W8 0 1 A0 r R9AA W3 W9 0 1 A0 r R9A9 W5 W6 WA 4 0 W6 W1 W3 W9 0 C27 WB 4 0 W6 W1 W9 W8 0 C27 WC 3 0 W8 W5 W4 0 C2B W0 3 0 W1 0 1 A0 r R9D0 W2 0 1 A0 r R9D1 W3 0 1 A0 r R9D2 0 R9D3 nE 2 4 WD 3 0 W9 W4 W2 0 C2B W15D 4 0 W62 W60 W61 W63 1 A35 57168 12368 6 C13 W15E 6 0 W62 W60 W6C WC8 W61 W63 1 A35 57168 10768 6 C15 W15F 6 0 W62 W60 WC7 W6D W61 W63 1 A35 57168 9168 6 C2A W160 6 0 W62 W60 W6E WC6 W61 W63 1 A35 57168 7568 6 C15 W161 6 0 W62 W60 WC5 W6F W61 W63 1 A35 57168 5968 6 C2A W162 4 0 W62 W60 W61 W63 1 A35 57168 4368 6 C1D W163 4 0 W62 W60 W61 W63 1 A35 57168 4368 4 C1C W164 6 0 W62 W60 W36 WC4 W61 W63 1 A35 55568 4368 4 C15 W165 7 0 W62 W60 WC2 W4F WC3 W61 W63 1 A35 53968 4368 4 C1E W166 7 0 W62 W60 WC2 W50 WC1 W61 W63 1 A35 52368 4368 4 C1E W167 7 0 W62 W60 WC2 W51 WC0 W61 W63 1 A35 50768 4368 4 C1E W168 7 0 W62 W60 WC2 W52 WBF W61 W63 1 A35 49168 4368 4 C1E W169 7 0 W62 W60 WC2 W53 WBE W61 W63 1 A35 47568 4368 4 C1E W16A 7 0 W62 W60 WC2 W54 WBD W61 W63 1 A35 45968 4368 4 C1E W16B 4 0 W62 W60 W61 W63 1 A35 44368 4368 4 C14 W16C 7 0 W62 W60 WC2 W55 WBC W61 W63 1 A35 42768 4368 4 C1E W16D 7 0 W62 W60 WC2 W56 WBB W61 W63 1 A35 41168 4368 4 C1E W16E 7 0 W62 W60 WC2 W57 WBA W61 W63 1 A35 39568 4368 4 C1E W16F 7 0 W62 W60 WC2 W58 WB9 W61 W63 1 A35 37968 4368 4 C1E W170 7 0 W62 W60 WC2 W59 WB8 W61 W63 1 A35 36368 4368 4 C1E W171 7 0 W62 W60 WC2 W5A WB7 W61 W63 1 A35 34768 4368 4 C1E W172 4 0 W62 W60 W61 W63 1 A35 33168 4368 4 C1C W173 4 0 W62 W60 W61 W63 1 A35 31568 4368 4 C13 W174 4 0 W62 W60 W61 W63 1 A35 29968 4368 4 C1B W175 6 0 W62 W60 WB6 W70 W61 W63 1 A35 28368 4368 4 C2A W176 6 0 W62 W60 WB5 W71 W61 W63 1 A35 26768 4368 4 C2A W177 7 0 W62 W60 WC2 W72 WB4 W61 W63 1 A35 25168 4368 4 C1E W178 7 0 W62 W60 WC2 W5C WB3 W61 W63 1 A35 23568 4368 4 C1E W179 7 0 W62 W60 WC2 W5D WB2 W61 W63 1 A35 21968 4368 4 C1E W17A 7 0 W62 W60 WC2 W5E WB1 W61 W63 1 A35 20368 4368 4 C1E W17B 4 0 W62 W60 W61 W63 1 A35 18768 4368 4 C14 W17C 7 0 W62 W60 WC2 W5F WB0 W61 W63 1 A35 17168 4368 4 C1E W17D 6 0 W62 W60 W37 WAF W61 W63 1 A35 15568 4368 4 C15 W17E 7 0 W62 W60 WC2 W73 WAE W61 W63 1 A35 13968 4368 4 C1E W17F 4 0 W62 W60 W61 W63 1 A35 12368 4368 4 C13 W180 6 0 W62 W60 W74 WAD W61 W63 1 A35 10768 4368 4 C15 W181 6 0 W62 W60 W38 WAC W61 W63 1 A35 9168 4368 4 C15 W182 8 0 W62 W60 WAB WAA W75 W11B W61 W63 1 A35 7568 4368 4 C2 W183 8 0 W62 W60 WA9 WA8 W26 W11B W61 W63 1 A35 5968 4368 4 C2 W184 4 0 W62 W60 W61 W63 1 A35 4368 4368 4 C1D W185 6 0 W62 W60 W39 WA7 W61 W63 1 A35 4368 4368 2 C15 W186 6 0 W62 W60 WA6 W76 W61 W63 1 A35 4368 5968 2 C2A W187 8 0 W62 W60 WA5 WA4 W27 W11B W61 W63 1 A35 4368 7568 2 C2 W188 8 0 W62 W60 WA3 WA2 W28 W11B W61 W63 1 A35 4368 9168 2 C2 W189 4 0 W62 W60 W61 W63 1 A35 4368 10768 2 C13 W18A 8 0 W62 W60 WA1 WA0 W29 W11B W61 W63 1 A35 4368 12368 2 C2 W18B 8 0 W62 W60 W9F W9E W2A W11B W61 W63 1 A35 4368 13968 2 C2 W18C 4 0 W62 W60 W61 W63 1 A35 4368 15568 2 C14 W18D 8 0 W62 W60 W9D W9C W2B W11B W61 W63 1 A35 4368 17168 2 C2 W18E 8 0 W62 W60 W9B W9A W23 W11B W61 W63 1 A35 4368 18768 2 C2 W18F 8 0 W62 W60 W99 W98 W24 W11B W61 W63 1 A35 4368 20368 2 C2 W190 8 0 W62 W60 W97 W96 W2 W11B W61 W63 1 A35 4368 21968 2 C2 W191 8 0 W62 W60 W95 W94 W3 W11B W61 W63 1 A35 4368 23568 2 C2 W192 8 0 W62 W60 W93 W92 W4 W11B W61 W63 1 A35 4368 25168 2 C2 W193 8 0 W62 W60 W91 W90 W5 W11B W61 W63 1 A35 4368 26768 2 C2 W194 4 0 W62 W60 W61 W63 1 A35 4368 28368 2 C1C W195 4 0 W62 W60 W61 W63 1 A35 4368 29968 2 C13 W196 6 0 W62 W60 W8F W77 W61 W63 1 A35 4368 31568 2 C2A W197 4 0 W62 W60 W61 W63 1 A35 4368 33168 2 C1B W198 8 0 W62 W60 W8E W8D W6 W11B W61 W63 1 A35 4368 34768 2 C2 W199 8 0 W62 W60 W8C W8B W7 W11B W61 W63 1 A35 4368 36368 2 C2 W19A 8 0 W62 W60 W8A W89 W8 W11B W61 W63 1 A35 4368 37968 2 C2 W19B 8 0 W62 W60 W88 W87 W9 W11B W61 W63 1 A35 4368 39568 2 C2 W19C 8 0 W62 W60 W86 W85 WA W11B W61 W63 1 A35 4368 41168 2 C2 W19D 8 0 W62 W60 W84 W83 WB W11B W61 W63 1 A35 4368 42768 2 C2 W19E 4 0 W62 W60 W61 W63 1 A35 4368 44368 2 C14 W19F 8 0 W62 W60 W82 W81 WC W11B W61 W63 1 A35 4368 45968 2 C2 W1A0 8 0 W62 W60 W80 W7F WD W11B W61 W63 1 A35 4368 47568 2 C2 W1A1 4 0 W62 W60 W61 W63 1 A35 4368 49168 2 C13 W1A2 8 0 W62 W60 W7E W7D WE W11B W61 W63 1 A35 4368 50768 2 C2 W1A3 8 0 W62 W60 W7C W7B WF W11B W61 W63 1 A35 4368 52368 2 C2 W1A4 6 0 W62 W60 W2E W7A W61 W63 1 A35 4368 53968 2 C15 W1A5 6 0 W62 W60 W2F W79 W61 W63 1 A35 4368 55568 2 C15 W1A6 4 0 W62 W60 W61 W63 1 A35 4368 57168 2 C1D