Project Name: Synthe8(635)\b13B
Designer: Jim Cherrye8\b9B
Filed on: [ivy]<speech>Synth>Synth.historye12j\f1 8f0 34f1
History:

8/29/79	Design completed, Rowson's DRC performed. 
8/3/80		[ivy]<speech>Synth>Synth.cif 8/29/80 Fabricated on XPA879e12j\b8B
1/20/80	Simulation performed.  Multiplier timing bug discovered and fixed.
1/28/80	[ivy]<speech>Synth>Synth.cif 1/28/80 Fabricated on MPC380
4/80		Layout bug in multiplier discovered and fixed.
5/21/80	Charge sharing bug in multiplier LSBtime gating discovered .
5/27/80	[ivy]<speech>Synth>Synth.Synth.ic!1Fabricated on MPC580
7/20/80	[ivy]<speech>Synth>Synth.Synth.ic!1  Fabricated on MPC780
11/6/80	New library pads, including PadInBuffered (Synth.ic!2)
11/17/80	Design rule error in ClockDriver (2x2 lambda corner-corner dif-dif) fixed (Synth.ic!3).
11/20/80	Old 11/6/80 version passed Baker's DRC except for error corrected 11/17/80.
1/81		Testing:	
				MPC580 F MEC   11 tested, 3 (l=2.5m) functional chips found. Vbb from -1V to -5V.
				MPC780 BG AMI 3 tested, all bad. Timing worked on a few.
1/25/80	[ivy]<speech>Synth>Synth.Synth.ic!3  Fabricated on MPC11A with l=2.0m, l=2.5m.
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