Heading:
MOS LSI Testers
Page Numbers: Yes X: 527 Y: 10.5"
Inter-Office Memorandum
ToSSL-LSIDateAugust 30, 1979
FromJerry RoylanceLocationPalo Alto
SubjectMOS LSI TestersOrganizationPARC
XEROX
Filed on: [ivy]<Roylance>RMTester.memo
Rob Mathews of Stanford designed a tester using CMOS parts. His design came out of many discussions with people here and also a meeting held near the beginning of the summer with people from Stanford, Cal Tech, CMU, and MIT. Sproull was a vehement supporter of a tester that has an RS-232C interface at that meeting. He reasoned that only such a device could be "portable": Everyone has RS-232C interfaces; not everyone has an Alto.
Mathews will be teaching a course at Stanford this fall, and so needs a tester to use on Stanford’s computers (at least they will be prepared; this contrasts heavily with my MIT experience). I volunteered to do the SIL diagrams for his design. He has tested the stitchwelded board we gave him; it works, but he wishes to make some design improvements during the next week. (These improvements have been made.)
Tester Description. The tester is designed to work in conjunction with a computer terminal. Both the terminal and the tester share the same EIA port, but a switch on the tester decides which of the two devices will send data to the computer. In operation, the user would log on to the computer and get ready to run the program; after starting the program he would flip the switch. When the program was finished exercising the chip, he would flip the switch back and use the terminal normally.
The tester has a UART so it can send and receive data from the computer. A crystal oscillator and baud rate generator set the speed of the data connection. When the tester receives a character from the computer, it interprets the character as a command to set a particular pin. The low order bit of the character specifies the value (either "0" or "1") to set the pin and the next six bits as the pin address. Six bits will specify 64 pins, but the current prototype only uses 40.
To save on control logic, the tester will also sample the pin it just set and send the sampled value back to the computer. While this may sound stupid, it isn’t. Though the tester does try to set the pin to a certain value, the impedance is high. If the pin is an output, it will not be affected by the attempt to set it, and the tester will read the correct output. The high output impedance of the drivers also protects the drivers from damage. Ground or VDD can be connected to the pins without damage.
The circuit was made by Rosemary Atkinson on an S100 board I got from Ted Strollo. The board does not have a power supply on it, but does have the EIA interface (less connector) and 40 pin drivers and receivers. Forty of the stitchweld pins were wired up to serve as a test socket; power connections to the IC under test can be made through the board’s edge connector. The baud rate is selected with a DIP switch mounted on the board.
The board is only a prototype, though it may see service for the class. Mathews plans to make a printed circuit board that contains all of the tester’s parts (ie the EIA sockets and power supply).
Advantages. This tester’s EIA interface lets it be used on almost any computer system. The baud rate is selectable so that it could be used on a 300 baud line or a 9600 baud line (or several rates in between). The pin driving circuits always remain connected to their respective pins even if the pin is an output or a power connection. This feature makes the test jig simple because no connections have to be broken; only power and ground have to be added.
Disadvantages. There is no software to drive the tester yet. Those programs will have to open the terminal in an "image" mode because control characters may be sent to the tester; this "image" mode might prove to be a minor nuisance. The tester is also be at the mercy of the operating system; characters might be sent in bursts and some games may be needed to circumvent the ↑S ↑Q protocols that the operating system might send to "turn off" and "turn on" the tester.
Files. The sil files are on [ivy]<Roylance>RMTester-Rev-X.dm.