Heading:

NCO Project Documentation

Page Numbers: Yes X: 527 Y: 10.5"

Inter-Office Memorandum

ToLynn ConwayDateSeptember 12, 1979

Dick Lyon
Forest Baskett

FromRich PascoLocationPalo Alto

SubjectNCO Project onOrganizationSSL-LSI

August 1979 MultiProjectChip

XEROX

Filed on[ivy]<Pasco>NCO.memoThis text and appendix

[ivy]<Pasco>NCOblock.SilFigure 1NCO Project Block Diagram
[ivy]<Pasco>ORstick.SilFigure 2OR Gate Stick Diagrams
[ivy]<Pasco>ORic.pressFigure 3Layout of Two-Inverter OR Gate
[ivy]<Pasco>DivideBy2.SilFigure 4Divide-by-2, Divide-by-4 Stick Diagrams
[ivy]<Pasco>DivideByN.SilFigure 5Divide-by-N Stick Diagram
[ivy]<Pasco>NCOlayout.pressFigure 6NCO Project IC Layout

Project NCO on the August, 1979 Multi-Project Chip is a 24-bit serial accumulator with input prescaling, constructed of modules designed to be compatible with other modules being designed for the speech recognition project.

Figure 1 shows a block diagram of NCO project. The project name, NCO, is an acronym for Number Controlled Oscillator, a term descriptive of an application of the device in frequency synthesis. Given a sequence of 24-bit twos-complement numbers, NCO divides each by a specifed power of 2 (which may be different for each successive number), and either loads an accumulator with the quotient or adds or subtracts the quotient from the previous contents of the accumulator. NCO uses 24-bit serial pipelined arithmetic, where successive 24-bit numbers come "head-to-tail," i.e. the least significant bit of a subsequent computation follows the most significant bit of the preceding, with no idle clock cycles between. Two wires are required to handle serial data: one, Data, carries the data itself, and the other, LSBtime, provides word synchronization by being true while Data is carrying the least significant bit of a new data word.

Scale factor N = 2n is selected by control inputs n2, n1, and n0 which are the binary representation of the exponent n. The scaler can divide each input by any N between 1 and 128, inclusive.

Control lines Add/Sub~ and Load/Add~ determine operation as follows:

Add/Sub~Load/Add~Operation
LowLowSubtract from previous result
LowHighLoad the negative of the input
HighLowAdd to previous result
HighHighLoad the input

All control lines are singly buffered; they are loaded during LSBtime at the point where they take effect. This relaxes restrictions on when they may change. One restriction remains: if multiple control bits change at once, the change must not occur between the LSBtimes at the multiple control points, lest one word receive some old control bits and some new control bits.

Two different methods are used for enabling the control inputs. For n2, n1, n0, and Add/Sub~, a pass transistor is inserted in series with the appropriate input. For Load/Add~, LSBtime multiplexes either the new or the previous Load/Add~ into the OR gate which follows.

The structure of the OR gate is unusual enough to warrant special discussion. Figure 2 illustrates stick diagrams of two simple OR gates. In each case, input A controls a multiplexer which selects itself when A is true, otherwise input B, thus implementing the Boolean expression if A then A else B, which reduces to A OR B. The first realization is the simplest, but cannot be driven from pass-transistor logic because its input itself drives a pass-transistor. The second realization contains a second inverter to buffer the input. Its layout is shown in Figure 3. This latter configuration was selected to perform the OR gate function of Figure 1.

The input scaling is accomplished by a cascade of three dividers, DivideBy2, DivideBy4, and DivideBy16, each of which is individually turned on or off by the corresponding control bit. As illustrated in Figures 4 and 5, Divide-By-N, where N = 2n, requires a delay of n+1 cycles, n of which can be bypassed under control of the divide input. By always delaying LSBtime, but optionally allowing the data to bypass n cycles with sign extension, correct division of twos-complement numbers is obtained. This operation is equivalent to an "arithmetic shift right."

NCO was laid out using ICARUS. Appendix 1 is a nested list of the ICARUS symbols used. The project is a single instance of the symbol NCOproject, which contains symbol NCO (the active circuitry), pads, clock circuits, and top-level wiring. Its dimensions are 536 lambda wide by 896 lambda high (dx=1608, dy=2688 icarus units). Figure 6 shows the layout of symbols NCOproject and NCO. The completed project resides on [ivy]<pasco>NCO.ic.



Appendix: ICARUS Symbols Used in Project NCO

NCOproject
NCO
NCOguts
NCOregs
ShiftPair [eleven, second through 23rd bits of data storage]
ForeAndBackPair
GtoR
GtoR
ForeAndBackPair [two, top halves = first bit of data storage
bottom halves = LSB delay around adder]
PlainAddSub
GtoR
BackwardInverterPair [one, buffer & invert Load/Add’]
DivideBy16
[Control]
SRinv1 [one, at first LSB stage]
SRrich [two, at second & third LSB stages]
SRinv2 [one, at fourth LSB stage]
SRout [one, at fifth LSB stage]
SRnor [four, on top of first through fourth LSB stages]
[DataPath]
SRin [one, at first data stage]
SRrich [three, at second through fourth data stages]
MuxReg [one, at fifth data stage]
GtoR
DivideBy4
[Control]
SRinv1 [one, at first LSB stage]
SRinv2 [one, at second LSB stage]
SRout [one, at third LSB stage]
SRnor [two, on top of first and second LSB stages]
[DataPath]
SRin [one, at first data stage]
SRrich [one, at second data stage]
MuxReg [one, at third data stage]
GtoR
DivideBy2
[Control]
SRinv12i [one, at first LSB stage]
SRout [one, at second LSB stage]
SRnor [one, on top of first LSB stage]
[DataPath]
SRin [one, at first data stage]
MuxReg [one, at second data stage]
GtoR
GridTop
GridBottom
ClockDriver
PadClockBar2
PadBlank2
Clock
LeftClock
RightClock
PadVdd2
PadBlank2
PadIn2
PadBlank2
PadOutNew2
PadDriver2
PadBlank2
PadGround2
PadBlank2
Pasco24
P24
A24
S24
C24
O24
Rich24
R24
I24
C24
H24