July 18, 1979PLA Speed CalculationsJim CherryFiled on: [ivy]PLAspeed.press, .bravoIntroductionEver wonder if your PLA can break the sound barrier ?Here is a rule of thumb to see if it will.ttotal = t[5M + 4.3N + 4.6I + 4]wherettotalis the PLA propagation delayMis the number of mintermsNis the number of outputsI is the number of inputstis the process transit time, e.g. .5nsThis expression is independent of the value of l. The basic attitude taken in itsderivation is one of extreme conservatism. This partially because incorporating thestatistics of how one programs the PLA would greatly complicate the expression.The PLA is assumed to be built from the standard library cells in A Guide to LSIImplementation [Hon and Sequin].DerivationThe basic formula used is the propagation delay for an inverter driving a capacitivenode [Mead and Conway].tr = tkCl/CgWheretris the rise time for the driven nodetis the process transit timeЪН@@ОbpТXН!≤О\1qТiН&3ОX⌡r НЇОQ)pТXП-НЇОJрqНЇОGГY3ю2kis the inverter's pull-up/pull-down ratioClis the node capacitance that the inverter is driving, including both gates and strays from interconnectCgis the gate capacitance of the inverterNote that this is the worst case transition, i.e. from low to high, since it includes thefactor k. In general this derivation assumes all transitions to be worst case to simplifythe expressions. The calculations of Cl and Cg are done by counting squares in the PLA cells whichare 1l by 1l, and multiplying by the appropriate capacitance/l2. The capacitanceconstants used are enumerated in the following table.Cggate-channelCddiffusionCppolyCmdmetal over diffusionCmpmetal over polyThe basic algorithm for calculating the total delay through the PLA is to calculate thetime constant for each section and sum them to give a final propagation timeconstant.An input to the PLA is first buffered by a pair of series connected inverters whichprovide both the true and false versions of the input to the AND plane. Each ofthese input buffers have the same loading (the AND plane input gates), ignoring theloading of the second inverter on the first. Thus, a falling and rising input haveapproximately the same amount of delay. Assuming that each output drives all ofthe minterm gates, this delay is given bytAND = t(k+1)[ (8Cg+6Cp)M ]/16Cgwhere M is the number of minterms in the PLA. k+1 is used because one inverteroutput will be rising, and the other falling. With a normal input k=4. If the input isdriven by a pass transistor, the first inverter will have k=8, but since its pull-downdoubles in width, nothing changes. This expression includes the loading from theAND plane gates and the poly line itself.НGООf╙pН`ОaвrНЮТП)Н`О^AО]ЄpНЮО^ArП5Н`О\Т─НЮТП(Н`ОXvОWИpНЮОXvrП'НЇОTvТ≤П1Т≥П(НЇОR╚Т─Т│ПEНЇОPЮТprНЇОMnНЇОKёТ■Т∙ОKpОKёrОKpОKёrП4НЇОIKТЁtrtrП1tОIьsОIKrТЄНЇОG─ТП5Н ОCЙОC]sН ОCЙrН ОAыОALsН ОAыrН О?хО?;sН О?хrН О=ЇО=*sН О=ЇrН О;іО;sН О;іrНЇО7йТ─Т│ПNНЇО5ЪТЫП5ТЗНЇО44НЇО.ВТ╙П/Т╚П$НЇО-,ТЇП@Т╦НЇО+aТ▌ПFТ▐НЇО)√Те ТфПIНЇО'кТ╟ПBТ╠ НЇО&ТП)Н О цО 6sТFО цrТitr О 6sО цrО 6sО цrО 6sНЇО@rТ√П-Т≈П"НЇОuТ─ПGТ│НЇО╙Т╔ТіПMНЇОъТ╦П(Т╧П)НЇОТП)Ъ╗Їм=ГT>)3Each AND plane output must drive the strays associated with the metal line whichcrosses all of its inputs in addition to the gates of the OR plane. The time constant isthustOR = tk[ (8Cg+6Cp)N + 2{8Cmd+8Cmp+12Cd}I ]/8Cgwhere N is the number of PLA outputs, and I is the number of PLA inputs. Again,k=4. This formula accounts for the gates driven in the OR plane (N) and the straysof the corresponding poly line. Note that in the library PLA cells a diffusion flashand contact to the output metal wire appears even if there is no programming flashto connect it (a bit of a bug). The bracketed quantity {} is the capacitance per polyline that the metal output bus crosses including these diffusion flashes. Since eachAND plane output crosses two of these for each PLA input, there is a factor of twoin there.An OR plane gate drives both the bracketed quantity above for each minterm, andan output buffer. Thus the delay through this stage istout = tk[8Cg+{8Cmd+8Cmp+12Cd}M]/8Cgwith k=4.Collecting all of the propagation delays, the final expression becomesttotal = tAND+tOR+toutttotal = t[(2.5Cg +1.88Cp +4Cmd+4Cmp +6Cd)M +(4Cg +3Cp)N +(8Cmd +8Cmp +12Cd)I +4Cg]/CgReasonable process values for the capacitances above areCg4x10-4pf/mm2Cd1x10-4pf/mm2Cp.4x10-4pf/mm2Cmd.4x10-4pf/mm2Cmp.4x10-4pf/mm2Plugging these into the ttotal expression and noting that the units of all capacitancescancel yield the desired result.НGООf╙pНЇО^erТїП+Т╗П%НЇО\ Т┐ПDТ└НЇОZоНОU▓ОUspТXОU▓rТitrОUsОU▓rОUsОU▓rОUsОU▓rОUsОU▓rОUsОU▓rОUsНЇОPUrТ▒П@Т▓НЇОN┼Т▀П#Т▄П0НЇОL©Т Т⌡ПBНЇОJТТ÷Т═П9НЇОI)Т·Т÷ПEНЇОG^Т╙ПIТ╚НЇОE⌠Т П9Т⌡НЇОCхТНЇО>▀Т╔ТіП8НЇО<юТП7НHО7┐О6ЖspТXО7┐rТitrО6ЖsО7┐rО6ЖsО7┐rО6ЖsО7┐rО6ЖsО7┐rО6ЖsНЇО4rТНЇО0{ПFН`О- О,|sО- rТiО,|sО- rО,|sО- rО,|sН`О)-rО(═sО)-rtrО(═sО)-rО(═sО)-rО(═sО)-rО(═sО)-rО(═sО)-rНЮО'О&▐sО'rО&▐sО'rО&▐sО'rО&▐sО'rО&▐sО'rО&▐sО'rО&▐sНЇО#нrТП8Н О О┬sН О rО ╒pО rtrО ╒pН ОЎrО1sН ОЎrОKpОЎrtrОKpН ОgrОзsН ОgrОТpОgrtrОТpН ОrО┐sН ОrО²pОrtrО²pН О╧rО,sН О╧rОFpО╧rtrОFpНЇОkrТ╘ОчsОkrТ╙П*НЇОZТЪ▄Ї=ГVЬ÷4ttotal = t[5M + 4.3N + 4.6I + 4]whereMis the number of mintermsNis the number of outputsI is the number of inputstis the process transit timeNotice that the constant term of 4 may be ignored for a reasonably sized PLA. Atypical value for t is about .5ns, and with a good HMOS process it may be as low as.2ns. Note if the geometries are scaled this expression is still valid, since it is theratio of load capacitance to driver gate capacitance that determines all of theconstants involved.ЪНGООf╙pН`ОZоrОZBsОZоrТtrНЇОU(Н`НЮН`ОS]НЮН`ОQ▓Т─НЮТН`ОOгtНЮrНЇОJ┼ТґП)ТўП'НЇОH©Т▌trТ▐П@НЇОFТТ╩П8Т╪НЇОE)Т ПKТНЇОC^ТЛЇAL=Г&©^ TIMESROMAN TIMESROMAN TIMESROMAN TIMESROMANHIPPO TIMESROMAN@в a╒ЪЪj/⌠рм▌ЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪЪplaspeed.bravoCherryAugust 4, 1979 4:12 AM