[IO]<DoradoDrawings>DskEth-Rev-Ce.ps!1

SIGNAL NAMES:

+: 1(1) 2(1) 3(1) 4(1) 8(1) 9(1)
10(1)11(1)12(1)13(1)14(1)15(1)
16(1)17(1)18(1)19(1)20(1)24(1)
25(1)26(1)27(1)28(1)29(1)30(1)
31(1)32(1)33(1)34(1)35(1)36(1)
37(1)38(1)
Active: 8(3)10(1)18(1)
bClkEn’: 1(1)27(1)31(1)33(1)
bClkEn’%: 4(1)
bIOB.00: 2(1)10(1)15(1)17(2)30(1)35(1)
bIOB.01: 2(1)10(1)15(1)17(2)29(1)30(1)
bIOB.02: 2(1)10(1)15(1)17(2)29(1)30(1)
bIOB.03: 2(1)10(1)15(1)17(2)29(1)30(1)
bIOB.04: 2(1) 9(1)10(1)15(1)17(2)28(1)
30(1)35(1)
bIOB.05: 2(1) 8(1) 9(1)10(1)15(1)17(2)
28(1)30(1)
bIOB.06: 2(1) 8(1) 9(1)10(1)15(1)17(2)
28(1)30(1)
bIOB.07: 2(1) 8(1) 9(1)10(1)15(1)17(2)
30(1)
bIOB.08: 1(1) 2(1) 8(1) 9(1)10(1)15(1)
17(1)30(1)35(1)
bIOB.09: 1(1) 2(1) 8(1) 9(1)10(1)15(1)
17(1)30(1)34(1)
bIOB.10: 1(1) 2(1) 8(1) 9(1)10(1)15(1)
17(1)30(1)34(1)
bIOB.11: 1(1) 2(1) 8(1) 9(1)10(1)15(1)
17(1)30(1)34(1)
bIOB.12: 1(1) 2(1) 8(1) 9(1)10(1)15(1)
17(1)30(1)35(1)
bIOB.13: 1(1) 2(1) 8(1) 9(1)10(1)15(1)
17(1)30(1)34(1)
bIOB.14: 1(1) 2(1) 8(1) 9(1)10(1)15(1)
17(1)30(1)34(1)
bIOB.15: 1(1) 2(1) 8(1) 9(1)10(1)15(1)
17(1)30(1)34(1)
bIOB.16: 2(1)15(1)17(1)30(1)
bIOB.17: 2(1)15(1)17(1)30(1)
bIOin’: 3(1)14(1)28(1)
bIOin’%: 4(1)
bIOout’!0: 1(1)17(1)19(4)
bIOout’!1: 29(1)35(2)
bIOout’!1%: 4(1)
bIOReset: 8(1)27(2)28(1)29(1)34(1)
bIOReset%: 4(1)
BitClock’A: 16(1)19(1)
BitClock’A%:19(1)
BitClock’B: 8(1)15(5)
BitClock’B%:19(1)
BitClock’C: 10(1)11(1)14(1)
BitClock’C%:19(1)
Block!: 36(1)
Blocked: 28(1)29(1)36(1)
BlockTillIndex: 8(1)17(1)
BlockTilRdy: 8(1)17(1)
BNTGtCT’b!: 36(1)
C0: 12(1)
C1: 12(1)
C2: 12(1)
C3: 12(1)
CheckBlock’: 8(1)15(1)17(1)18(1)
CheckData’: 15(2)
CheckSumErr:16(1)17(1)
CkFifoParity’:15(2)
ClearErrors: 8(1)14(2)15(1)16(1)17(3)
ClearIndexTW:17(2)
ClearSectorTW:17(2)
ClearTWs: 14(3)15(1)17(2)
CLK.disk’: 4(1)
Clk0%: 4(1)
Clk1%: 4(1)
CLKEnable’a!: 4(1)
Clock0’Bc: 17(1)
Clock0’Bc%: 35(1)
Clock0’Da: 1(1)
Clock0’Da%: 35(1)
Clock0’Dd: 36(1)
Clock0’Dd%: 35(1)
Clock1’Bb: 27(2)28(2)
Clock1’Bb%: 35(1)
Clock1’Bd: 27(2)
Clock1’Bd%: 35(1)
Clock1’Ca: 8(1)14(3)
Clock1’Ca%: 19(1)
Clock1’Cb: 17(2)
Clock1’Cb%: 19(1)
Clock1’Cc: 17(1)
Clock1’Cc%: 19(1)
Clock1’Da!0:30(4)
Clock1’Da!1%:35(1)
Clock1’Da!2:32(1)
Clock1’Db: 27(1)31(2)
Clock1’Db%: 35(1)
Clock1’Dd!0:31(2)
Clock1’Dd!1%:35(1)
Clock1’Dd!2:33(1)
ClockM0: 20(1)
ClockM0!: 13(1)
ClockM1: 20(1)
ClockM1!: 13(1)
ClockM2: 20(1)
ClockM2!: 13(1)
ClockM3: 20(1)
ClockM3!: 13(1)
ClockP0: 20(1)
ClockP0!: 13(1)
ClockP1: 20(1)
ClockP1!: 13(1)
ClockP2: 20(1)
ClockP2!: 13(1)
ClockP3: 20(1)
ClockP3!: 13(1)
CntDone’: 9(3)18(1)
Collision: 34(1)38(1)
CompareErr’:16(1)17(1)
ComputeECC: 9(1)16(1)18(1)
ComputeECC’: 9(1)16(2)
ContErrs’: 11(1)
ContRegCl’: 8(1)16(1)
ControlRegCl: 8(2) 9(1)
ControlRegCl%:19(1)
ControlRegCl’: 8(2)
ControlRegCl’%:19(1)
ControlTag: 10(2)18(1)
ContTag’: 10(1)20(1)
Curr=EthRx: 28(1)36(1)
Curr=EthTx: 29(1)36(1)
CylinderTag:10(2)18(1)
CylinderTag’:10(1)20(1)
CylOffset: 11(2)18(1)
DataM0: 13(1)20(1)
DataM0!: 13(1)
DataM1: 13(1)20(1)
DataM1!: 13(1)
DataM2: 13(1)20(1)
DataM2!: 13(1)
DataM3: 13(1)20(1)
DataM3!: 13(1)
DataP0: 13(1)20(1)
DataP0!: 13(1)
DataP1: 13(1)20(1)
DataP1!: 13(1)
DataP2: 13(1)20(1)
DataP2!: 13(1)
DataP3: 13(1)20(1)
DataP3!: 13(1)
DebugMode: 8(3)18(1)
DevCheck: 11(2)18(1)
dFifoParityErr:15(2)
dIOBParityErr:17(1)
DisableCnt: 10(1)
DisableRun: 8(4)11(1)17(2)
DiskTW: 17(1)
DMadr.01: 1(3)
DMadr.02: 1(3)
DMadr.03: 1(3)
DMadr.04: 1(4)
DMadr.05: 1(3)
DMadr.06: 1(3)
DMadr.07: 1(3)
DMadr.08: 1(3)
DMadr.09: 1(3)
DMadr.10: 1(3)
DMadr.11: 1(3)
DMuxClk!: 1(1)
DMuxData: 1(1)
DMuxData!: 1(1)
DriveTag: 10(1)18(1)
DriveTag’: 10(1)20(1)
DrSelected: 10(1)12(1)
DskData.00: 3(1)15(1)
DskData.01: 3(1)15(1)
DskData.02: 3(1)15(1)
DskData.03: 3(1)15(1)
DskData.04: 3(1)15(1)
DskData.05: 3(1)15(1)
DskData.06: 3(1)15(1)
DskData.07: 3(1)15(1)
DskData.08: 3(1)15(1)
DskData.09: 3(1)15(1)
DskData.10: 3(1)15(1)
DskData.11: 3(1)15(1)
DskData.12: 3(1)15(1)
DskData.13: 3(1)15(1)
DskData.14: 3(1)15(1)
DskData.15: 3(1)15(1)
DskData.16: 3(1)15(1)
DskData.17: 3(1)15(1)
EccComputeErr’:16(1)
EccData.21: 16(4)
EccData.32: 15(2)16(4)
EClk0%: 35(1)
EClk1%: 35(1)
EClk2%: 35(1)
ECLTrueA: 2(2) 3(1)13(8)15(2)17(2)19(1)
ECLTrueB: 25(1)26(2)27(2)38(2)
ECLTrueC: 9(3)10(2)14(3)15(2)19(1)
ECLTrueD: 1(1)30(3)31(3)32(1)33(1)35(1)
36(1)38(2)
EmptyBlock’: 8(2)
EnableRun: 8(1)18(1)
EnCheckTW’: 15(1)17(1)
EnReadTW’: 15(1)17(1)
EnWriteTW’: 8(1)15(1)17(1)
EthCtrl←IOB’:28(1)
EthCtrl←IOB’%:35(1)
EthData.00: 3(1)26(1)
EthData.01: 3(1)26(1)
EthData.02: 3(1)26(1)
EthData.03: 3(1)26(1)
EthData.04: 3(1)26(1)
EthData.05: 3(1)26(1)
EthData.06: 3(1)26(1)
EthData.07: 3(1)26(1)
EthData.08: 3(1)26(1)
EthData.09: 3(1)26(1)
EthData.10: 3(1)26(1)
EthData.11: 3(1)26(1)
EthData.12: 3(1)26(1)
EthData.13: 3(1)26(1)
EthData.14: 3(1)26(1)
EthData.15: 3(1)26(1)
EthData.16: 3(1)26(1)
EthData.17: 3(1)26(1)
EthData.18: 26(1)36(1)37(1)
EthData.18’:26(1)28(1)
EtherClk170:33(2)
EtherClk170%:35(1)
EtherClk340:33(2)
EtherClk340%:35(1)
EtherClk42.5a:24(1)
EtherClk42.5a%:35(1)
EtherClk42.5b:25(1)
EtherClk42.5b%:35(1)
EtherClk42.5c:26(1)
EtherClk42.5c%:35(1)
EthStatus.16: 3(1)38(1)
EthStatus.17: 3(1)38(1)
FHCP: 2(1)14(1)
FHCP%: 4(1)
FifoAddr.0: 14(1)15(5)
FifoAddr.1: 14(1)15(5)
FifoAddr.2: 14(1)15(5)
FifoAddr.3: 14(1)15(5)
FifoCl: 14(1)
FifoCl%: 19(1)
FifoCl’: 15(5)
FifoCl’%: 19(1)
FifoEmpty: 14(3)
FifoFull: 14(3)
FifoOverflow:11(1)14(2)18(1)
FifoParityErr:11(1)15(2)18(1)
FifoRaddr.0:14(3)18(1)
FifoRaddr.1:14(3)18(1)
FifoRaddr.2:14(3)18(1)
FifoRaddr.3:14(3)18(1)
FifoUnderflow:11(1)14(2)18(1)
FifoWaddr.0:14(3)18(1)
FifoWaddr.1:14(3)18(1)
FifoWaddr.2:14(3)18(1)
FifoWaddr.3:14(3)18(1)
FifoWaddrCl’:14(1)
FifoWaddrCl’%:19(1)
Gnd: 1(1) 2(1) 3(1) 4(1) 8(1) 9(1)
10(1)11(1)12(1)13(1)14(1)15(1)
16(1)17(1)18(1)19(1)20(1)24(1)
25(1)26(1)27(1)28(1)29(1)30(1)
31(1)32(1)33(1)34(1)35(1)36(1)
37(1)38(1)
GND: 4(1)12(5)20(1)
HeadOvfl: 11(2)18(1)
HeadTag: 10(2)18(1)
HeadTag’: 10(1)20(1)
Host.0: 3(1)38(2)
Host.1: 3(1)38(2)
Host.2: 3(1)38(2)
Host.3: 3(1)38(2)
Host.4: 3(1)38(2)
Host.5: 3(1)38(2)
Host.6: 3(1)38(2)
Host.7: 3(1)38(2)
Idle: 8(2) 9(3)10(1)
Index’: 12(1)17(1)
IndexTW: 8(1)17(1)18(1)
InRegCl’: 15(5)
InRegCl’%: 19(1)
InRegFull: 14(1)18(1)
InRegFull’: 14(2)19(2)
InReg←IOB: 14(1)19(1)
InReg←IOB%: 19(1)
InReg←SR: 19(1)
InReg←SR’: 14(1)15(5)19(1)
IOatt!: 36(1)
IOB.00: 3(1)
IOB.00!: 2(1)
IOB.01: 3(1)
IOB.01!: 2(1)
IOB.02: 3(1)
IOB.02!: 2(1)
IOB.03: 3(1)
IOB.03!: 2(1)
IOB.04: 3(1)
IOB.04!: 2(1)
IOB.05: 3(1)
IOB.05!: 2(1)
IOB.06: 3(1)
IOB.06!: 2(1)
IOB.07: 3(1)
IOB.07!: 2(1)
IOB.08: 3(1)
IOB.08!: 2(1)
IOB.09: 3(1)
IOB.09!: 2(1)
IOB.10: 3(1)
IOB.10!: 2(1)
IOB.11: 3(1)
IOB.11!: 2(1)
IOB.12: 3(1)
IOB.12!: 2(1)
IOB.13: 3(1)
IOB.13!: 2(1)
IOB.14: 3(1)
IOB.14!: 2(1)
IOB.15: 3(1)
IOB.15!: 2(1)
IOB.16: 3(1)
IOB.16!: 2(1)
IOB.17: 3(1)
IOB.17!: 2(1)
IOBParityErr:11(1)17(2)18(1)
IOHold!: 36(1)
IOin’!: 4(1)
IOout’!: 4(1)
IOReset!: 4(1)
LastRamAddr’: 8(1) 9(1)
LdSubSector0’:11(1)12(1)
LdSubSector1’:11(1)12(1)
LdSubSector2’:11(1)12(1)
LdSubSector3’:11(1)12(1)
LoadCnt’: 9(2)
LoadTag: 9(1)18(1)
LoopBack: 3(1)34(2)38(1)
MemSH’!: 4(1)
MidasEn.01T.02F.03F.04F’: 1(1)
MidasEn.05F’: 1(1)18(8)
MidasEn.05T’: 1(1)18(2)37(6)
MufAd.1: 1(1)
MufAd.2: 1(1)
MufAd.3: 1(1)
MufAd.4: 1(1)
MufAdr.06: 1(2)
MufAdr.07: 1(2)
MufAdr.08: 1(2)
MufAdr.09: 1(1)18(10)37(6)
MufAdr.10: 1(1)18(10)37(6)
MufAdr.11: 1(1)18(10)37(6)
MufAdr←IOB’: 1(2)17(2)
MufData: 1(1) 3(1)
MufData’: 1(1) 3(1)
MuxData0: 1(1)18(2)
MuxData1: 1(1)18(2)
MuxData2: 1(1)18(1)37(1)
MuxData3: 1(1)18(1)37(1)
MuxData4: 1(1)18(1)37(1)
MuxData5: 1(1)18(1)37(1)
MuxData6: 1(1)18(1)37(1)
MuxData7: 1(1)18(1)37(1)
Next.0!: 36(1)
Next.1!: 36(1)
Next.2!: 36(1)
Next.3!: 36(1)
Next=EthRx?:28(1)36(2)
Next=EthTx?:29(1)36(1)
Next=EthTx?’:36(2)
NextBlock: 9(1)18(1)
NextBlockCl: 8(2) 9(1)
NotOnLine: 11(2)18(1)
NotReady: 11(2)17(1)18(1)
NotReady’: 8(1)11(1)
NotSelected:11(1)12(1)13(1)18(1)
NoWakeups: 3(1)28(1)29(1)34(1)38(1)
OS0: 12(1)20(1)
OS1: 12(1)20(1)
OS2: 12(1)20(1)
OS3: 12(1)20(1)
OutPar.16: 15(2)
OutPar.17: 15(2)
OutRegCl’A: 15(4)
OutRegCl’A%:19(1)
OutRegCl’C: 14(1)
OutRegCl’C%:19(1)
OutRegFull: 14(3)18(1)
OutRegFull’:14(3)17(1)
OutRegWrite’:14(1)19(1)
PDCarrier: 24(1)25(1)32(1)37(1)
PDCnt.0: 24(1)37(1)
PDCnt.1: 24(1)37(1)
PDCnt.2: 24(1)37(1)
PDCnt.3: 24(1)37(1)
PDCntCtrl: 24(1)37(1)
PDEvent.0: 24(1)25(1)37(1)
PDEvent.1: 24(1)25(1)37(1)
PDInput: 24(1)34(1)
PDNew: 24(1)37(1)
PDOld: 24(1)37(1)
Pendulum!: 31(1)
PEOutput: 33(1)34(1)37(1)
PreBitClock:10(1)19(1)
PreBitClock’:19(1)
PreClock0’A:19(1)
PreClock0’A%: 4(1)
PreClock0’B:35(1)
PreClock0’B%: 4(1)
PreClock0’D:35(1)
PreClock0’D%: 4(1)
PreClock1’Ba:35(3)
PreClock1’Ba%: 4(1)
PreClock1’Bb:35(3)
PreClock1’Bb%: 4(1)
PreClock1’Ca:19(4)
PreClock1’Ca%: 4(1)
PreClock1’Cb:19(3)
PreClock1’Cb%: 4(1)
PreClock1’D:35(3)
PreClock1’D%: 4(1)
PrePreBitClock:13(1)17(1)
PrePreBitClock’:19(2)
PrePreBitClock’%:13(1)
PrePreClock’%: 4(1)
PreReadData:13(1)17(1)
PreSHCP’: 1(1)
PreSHCP’%: 4(1)
Prev=EthRx: 28(1)36(1)
Prev=EthTx: 29(1)36(1)
PromA4: 9(2)
PromA4’: 9(3)
R0: 12(1)
R1: 12(1)
R2: 12(1)
R3: 12(1)
Ram.04: 9(2)10(1)18(1)
Ram.05: 9(2)10(1)18(1)
Ram.06: 9(2)10(1)18(1)
Ram.07: 9(2)10(1)18(1)
Ram.08: 9(2)10(1)18(1)
Ram.09: 9(2)10(1)18(1)
Ram.10: 9(2)10(1)18(1)
Ram.11: 9(2)10(1)18(1)
Ram.12: 9(2)10(1)18(1)
Ram.13: 9(2)10(1)18(1)
Ram.14: 9(2)10(1)18(1)
Ram.15: 9(2)10(1)18(1)
RamAddr.0: 9(1)18(1)
RamAddr.1: 9(1)18(1)
RamAddr.2: 9(1)18(1)
RamAddr.3: 9(1)18(1)
RamCl’A: 8(1) 9(1)
RamCl’A%: 19(1)
RamCl’C: 9(1)
RamCl’C%: 19(1)
RcvData: 34(1)38(1)
RdFifoTW: 17(1)18(1)
RdOnlyBlock’: 8(1)15(1)18(1)
RdOnlyData’:15(2)
ReadBlock: 8(1) 9(1)
ReadData: 13(1)15(1)16(1)18(1)
ReadDataErr:11(1)16(2)18(1)
ReadError: 11(1)18(1)
ReadOnly: 11(2)18(1)
ReadTW’: 14(1)17(1)
ReportCollisions:24(1)34(1)37(1)
RxBOP: 28(2)37(1)
RxBusRegClk’:26(4)
RxBusRegClk’%:35(1)
RxBusRegFull:27(1)28(2)37(1)
RxCollision:25(1)26(1)33(1)37(1)
RxCRCClk: 25(1)27(1)37(1)
RxCRCError: 26(1)27(1)37(1)
RxCRCReset: 25(1)27(1)37(1)
RxCtrlClk’: 28(1)
RxCtrlClk’%:35(1)
RxData: 25(1)26(1)27(1)37(1)
RxDataLate: 26(1)27(1)37(1)
RxEOP: 25(1)26(1)37(1)
RxFifoAd.0: 26(5)27(1)
RxFifoAd.1: 26(5)27(1)
RxFifoAd.2: 26(5)27(1)
RxFifoAd.3: 26(5)27(1)
RxFifoEmpty:27(2)37(1)
RxFifoFull: 27(2)37(1)
RxFifoFull’:27(2)
RxFifoWE’: 26(5)
RxFifoWE’%: 35(1)
RxIncTrans: 25(1)26(1)37(1)
RxOff: 28(2)
RxOn: 3(1)28(1)38(1)
RxReadFifo’:27(1)28(1)35(1)
RxSR.00: 26(2)
RxSR.01: 26(2)
RxSR.02: 26(2)
RxSR.03: 26(2)
RxSR.04: 26(2)
RxSR.05: 26(2)
RxSR.06: 26(2)
RxSR.07: 26(2)
RxSR.08: 26(2)
RxSR.09: 26(2)
RxSR.10: 26(2)
RxSR.11: 26(2)
RxSR.12: 26(2)
RxSR.13: 26(2)
RxSR.14: 26(2)
RxSR.15: 26(2)
RxSR.16: 26(2)
RxSR.17: 26(2)
RxSR.18: 26(1)
RxSR.18’: 26(1)27(1)
RxSRCtrl.0: 25(2)26(1)37(1)
RxSRCtrl.1: 25(2)26(1)37(1)
RxSRDump: 27(2)
RxSRDump’: 27(3)
RxSRFull’: 25(1)37(1)
RxState.0: 25(1)37(1)
RxState.1: 25(1)37(1)
RxState.2: 25(1)37(1)
RxSync’: 25(1)35(1)37(1)
RxSyncClk’: 26(1)27(1)
RxSyncClk’%:35(1)
RxWriteFifo’:27(2)35(1)
SampleIOBparity’:17(1)
sCountBits: 19(1)
sCountBits%:19(1)
SecIndx0’: 12(1)20(1)
SecIndx1’: 12(1)20(1)
SecIndx2’: 12(1)20(1)
SecIndx3’: 12(1)20(1)
Sector: 8(2)12(1)
Sector’: 12(1)17(1)
Sector0’: 12(2)
Sector1’: 12(2)
Sector2’: 12(2)
Sector3’: 12(2)
SectorOvfl: 8(2)11(1)18(1)
SectorTW: 17(1)18(1)
SeekInc: 11(2)18(1)
SeekTagTW: 17(1)18(1)
Select.0: 11(1)13(1)18(1)
Select.1: 11(1)13(1)18(1)
Select0: 11(1)
Select0’: 11(1)20(1)
Select1: 11(1)
Select1’: 11(1)20(1)
Select2: 11(1)
Select2’: 11(1)20(1)
Select3: 11(1)
Select3’: 11(1)20(1)
Selected0’: 12(1)20(1)
Selected1’: 12(1)20(1)
Selected2’: 12(1)20(1)
Selected3’: 12(1)20(1)
SetTagTW: 10(1)17(1)
ShiftIn: 9(1)13(1)17(1)18(1)19(1)
ShiftIn’: 9(1)19(1)
ShiftOut: 9(1)18(1)
ShiftOut’: 9(1)19(1)
ShiftReg.00:15(4)16(1)
ShiftReg.01:15(3)
ShiftReg.02:15(3)
ShiftReg.03:15(3)
ShiftReg.04:15(3)
ShiftReg.05:15(3)
ShiftReg.06:15(3)
ShiftReg.07:15(3)
ShiftReg.08:15(3)19(1)
ShiftReg.09:15(3)
ShiftReg.10:15(3)
ShiftReg.11:15(3)
ShiftReg.12:15(3)
ShiftReg.13:15(3)
ShiftReg.14:15(3)
ShiftReg.15:15(3)19(1)
ShiftReg.16:15(2)
ShiftReg.17:15(2)
ShiftReg.in:15(2)
ShiftRegLd’:14(2)15(5)19(1)
SingleStep: 3(1)34(1)35(1)38(1)
sPendulum: 29(1)31(1)
Tag.0: 10(1)18(1)
Tag.00: 10(1)18(1)
Tag.000: 10(1)18(1)19(1)
Tag.1: 10(1)18(1)
Tag.2: 10(1)18(1)
Tag.3: 10(1)18(1)
Tag.4: 10(1)18(1)
Tag.5: 10(1)18(1)
Tag.6: 10(1)18(1)
Tag.7: 10(1)18(1)
Tag.8: 10(1)18(1)
Tag.9: 10(1)18(1)
TagBus.0’: 10(1)20(1)
TagBus.00’: 10(1)20(1)
TagBus.000’:10(1)20(1)
TagBus.1’: 10(1)20(1)
TagBus.2’: 10(1)20(1)
TagBus.3’: 10(1)20(1)
TagBus.4’: 10(1)20(1)
TagBus.5’: 10(1)20(1)
TagBus.6’: 10(1)20(1)
TagBus.7’: 10(1)20(1)
TagBus.8’: 10(1)20(1)
TagBus.9’: 10(1)20(1)
TagClock: 10(2)
TagClock’: 10(1)
TagDone: 10(2)
TagEnable: 10(1)
TagStrobe: 10(1)
Tag←IOB: 10(1)11(1)
Tag←IOB%: 19(1)
Tag←Ram: 9(1)10(1)
TempRef!: 4(1)
TempSense: 18(1)
TempSense!: 4(1)
TestCtrlClk:35(1)
TestCtrlClk!1%:35(1)
TestCtrlClk’!0:34(1)
TestCtrlClk’!2:34(1)
TestCtrlClk’%:35(1)
TIOA-Ad.0: 2(1)
TIOA-Ad.1: 2(1)
TIOA-Ad.2: 2(1)
TIOA-Ad.3: 2(1)
TIOA-Ad.4: 2(1)
TIOA.0!: 2(1)
TIOA.1!: 2(1)
TIOA.2!: 2(1)
TIOA.3!: 2(1)
TIOA.4!: 2(1)
TIOA.5!: 2(1)
TIOA.5a: 2(1) 3(1)
TIOA.6!: 2(1)
TIOA.6a: 2(1)
TIOA.7!: 2(1)
TIOA.7a: 2(1) 3(1)
TIOA=Cont’: 2(1) 8(1)19(1)
TIOA=Data’: 2(1) 8(1)14(1)19(1)
TIOA=EthCtrl’: 2(1)35(1)
TIOA=EthData’: 2(1)28(1)29(1)35(1)
TIOA=Muff’: 1(1) 2(1)
TIOA=Ram’: 2(1)19(1)
TIOA=Tag’: 2(1)19(1)
TIOA=Us’: 2(2) 3(1)17(1)
TskAd.0: 36(1)
TskAd.1: 36(1)
TskAd.2: 36(1)
TtlDeviceCk’:11(1)20(1)
TtlDriveTag’:10(1)11(2)
TtlEndOfCyl’:11(1)20(1)
TtlIndex’: 12(1)20(1)
TtlOffSet’: 11(1)20(1)
TtlOnLine’: 11(1)20(1)
TtlReadOnly’:11(1)20(1)
TtlReady’: 11(1)20(1)
TtlRunOK: 11(2)
TtlRunOK’: 11(2)
TtlSector’: 12(1)20(1)
TtlSeekInc’:11(1)20(1)
TtlSelect.0:11(2)12(1)
TtlSelect.1:11(2)12(1)
TtlTag.0: 10(1)12(4)
TtlTag.00: 10(1)12(4)
TtlTag.000: 10(1)12(4)
TtlTag.1: 10(1)12(4)
TtlTag.2: 10(1)12(4)
TtlTag.3: 10(1)12(4)
TtlTag.4: 10(1)11(1)
TtlTag.5: 10(1)11(1)
TtlTag.6: 10(1)11(1)
TtlTag.7: 10(1)11(1)
TtlTag.8: 10(1)11(1)
TtlTag.9: 10(1)11(1)
TtlTerm’: 11(1)20(1)
TTLTrueA: 12(5)20(1)
TTLTrueB: 27(1)31(1)38(1)
TTLTrueC: 11(2)20(1)
TxAbort’: 32(1)36(1)
TxBusRegClk’:30(3)
TxBusRegClk’%:35(1)
TxBusRegFull’:29(1)31(1)37(1)
TxCntDwn’: 29(1)37(1)
TxCollision: 3(1)32(1)33(1)38(1)
TxCRCClk: 31(1)32(1)
TxCRCEnbl: 31(2)32(1)37(1)
TxCtrlClk’: 29(3)
TxCtrlClk’%:35(1)
TxData: 30(1)31(2)32(1)33(1)37(1)
TxDataLate: 3(1)31(1)32(1)38(1)
TxEnd: 32(1)
TxEOP: 29(1)31(1)32(2)37(1)
TxFifo.00: 30(2)
TxFifo.01: 30(2)
TxFifo.02: 30(2)
TxFifo.03: 30(2)
TxFifo.04: 30(2)
TxFifo.05: 30(2)
TxFifo.06: 30(2)
TxFifo.07: 30(2)
TxFifo.08: 30(2)
TxFifo.09: 30(2)
TxFifo.10: 30(2)
TxFifo.11: 30(2)
TxFifo.12: 30(2)
TxFifo.13: 30(2)
TxFifo.14: 30(2)
TxFifo.15: 30(2)
TxFifo.16: 30(2)
TxFifo.17: 30(2)
TxFifoAd.0: 30(5)31(1)
TxFifoAd.1: 30(5)31(1)
TxFifoAd.2: 30(5)31(1)
TxFifoAd.3: 30(5)31(1)
TxFifoEmpty:31(2)32(1)37(1)
TxFifoEmpty’:31(2)
TxFifoFull: 31(2)32(1)37(1)
TxFifoPE: 3(1)30(1)32(1)38(1)
TxFifoWE’: 30(5)
TxFifoWE’%: 35(1)
TxGo: 32(1)33(1)37(1)
TxGone: 29(1)32(1)37(1)
TxGotBit: 32(1)33(1)
TxOff: 29(2)30(1)31(4)32(1)33(1)
TxOn: 3(1)29(1)38(1)
TxReadFifo: 30(1)31(1)
TxSRCtrl.0: 30(4)32(2)37(1)
TxSRCtrl.1: 30(4)32(2)37(1)
TxSREmpty’: 32(1)37(1)
TxSRLoad: 31(1)32(1)
TxSRLoad’: 31(2)32(1)
TxStart: 32(1)
TxState.0: 32(1)37(1)
TxState.1: 32(1)37(1)
TxState.2: 32(1)37(1)
TxWriteFifo’:29(1)31(1)35(1)
Unit0←Data’:11(1)13(1)
Unit1←Data’:11(1)13(1)
Unit2←Data’:11(1)13(1)
Unit3←Data’:11(1)13(1)
Vbb0!: 10(1)
Vbb1!: 10(1)
Vbb2!: 10(1)
Vbb3!: 10(1)
Vbb4: 10(1)
Vbb4!: 10(1)
Vbb5: 11(2)
Vbb5!: 13(1)
Vbb6!: 31(1)
Vbb7: 34(1)
Vbb7!: 27(1)
VCC: 4(1)11(2)12(4)13(8)20(1)
VEE: 4(1)
WakeEthRx: 28(1)
WakeEthTx: 29(1)
Whatever: 4(2)
WordClock’: 9(5)
WordClock’%:19(1)
WrFifoTW: 17(1)18(1)
WriteBlock’: 8(1) 9(1)11(2)16(1)17(1)18(1)
WriteData: 13(1)15(1)18(1)
WriteError: 11(1)18(1)
WriteInhibit’:10(1)11(1)
WriteTW’: 14(1)17(1)
XcCollision:33(1)34(1)
XmtData’: 34(1)38(1)