;-----------------------------------------------------------------
; MesaBLTLreal.Mu - Full implementation of BLTL.
; Last modified by Levin - February 27, 1979  5:43 PM
;-----------------------------------------------------------------

;-----------------------------------------------------------------
; BLTL - block transfer (long pointers)
;	assumes stack has precisely five words:
;	  stk0, stk1 - address of first word to read
;	  stk2	     - count of words to move
;	  stk3, stk4 - address of first word to write
;	the instruction is interruptible and leaves a state suitable
;	  for re-execution if an interrupt must be honored.
;-----------------------------------------------------------------
!1,1,BLTLsetBR;							shake BUS=0
!7,1,BLTLsetBRx;						shake IR_
!3,4,BLTLret0,BLTLret1,BLTLret2;
!1,2,BLTLnoint,BLTLint;
!1,2,BLTLintpend,BLTLloop;
!1,2,BLTLmore,BLTLdone;

; Note:  ROM code does stk7_L


BLTL:		MAR_BankReg;					access bank register
		T_stk1;						high source bits
		L_stk1+T;					L: high source *2
		temp_L LSH 1, IR_msr0;				temp: high source *4;
		L_MD, TASK;					L: old bank register
		saveret_L;					saveret: stashed register
		T_stk4;						T: high dest bits
		T_3.T, :BLTLsetBR;				(would like to avoid this)
;								returns to BLTLret0

BLTLloop:	L_T_stk2-1, BUS=0, :BLTLnoint;			decrement count, test done
BLTLnoint:	stk2_L, :BLTLmore;				T: -1 the last time

BLTLmore:	MAR_stk0;					fetch source word
		L_stk0+1;					bump source pointer
		stk0_L;
		L_stk3+1;					bump destination pointer
		T_MD;
		XMAR_stk3;					initiate store
		stk3_L, L_T;					L: data
		SINK_NWW, BUS=0, TASK;				check for possible interrupt
BLTLret0:	MD_M, :BLTLintpend;				stash data

BLTLintpend:	SINK_wdc, BUS=0, :BLTLloop;			check if enabled

BLTLint:	IR_sr2, :BLTLsetBR;				restore bank before interrupt
BLTLret2:	MD_saveret, :BLTint;				BLTint shakes branch

BLTLdone:	IR_sr1, :BLTLsetBR;				restore bank before exit
BLTLret1:	MD_saveret, L_saveret AND NOT T, :BLTdone;	BLTdone shakes branch


BLTLsetBR:	MAR_BankReg, :BLTLsetBRx;
BLTLsetBRx:	L_temp OR T, IDISP;				(used by BLTLret0 only)
		SINK_0, BUS=0, :BLTLret0;			force branch for BLTLret0
;								BLTLret1 and 2 must shake