Inter-Office MemorandumToFileDateOctober 6, 1978FromRoy LevinLocationPalo AltoSubjectOn the Harmonious Cooperation ofOrganizationCSLXMesa and User Microcode (version 2)XEROX Filed on: [Ivy]Doc>Microcode.bravo (and .press)This document describes an interface that permits users to load their own microcode into the RAMof an Alto II XM and execute it without interfering with the Mesa emulator. These facilities areavailable only under XMesa. Higher-level facilities of XMesa are described in a separate documentfiled on [Ivy]Doc>XMesa.press (and .bravo).Loading User MicrocodeThe XMesa emulator occupies all of ROM1 and about 25 words of RAM. The remainder of theRAM is available for use by client programs. To simplify loading of user microcode, a filecontaining the overflow portion of the XMesa emulator is included in the user's assembly,producing a single output file that can be loaded in its entirety. Addressing requirements arespecified in the file; no locations are reserved "by convention" alone. Assembly ProcedureUsers should carefully follow the steps below in constructing RAM images to be loaded underXMesa.1)Obtain MesaXRAM.mu and MesabROM.mu from the dump file[Ivy]System>XMesaMu.dm. The former is the actual microcode, the lattercontains the definitions for all registers and other symbols used by the Mesa emulator.2)Prepare a source file, Driver.mu, of the following form:#AltoConsts23.mu;standard Alto definitions; Sufficient pre-definitions should be inserted here to; reserve locations 0-17 inclusive.#MesaXRAM.mu;includes MesabROM internally#UserMicrocode.mu;user microcode source3)Assemble Driver.mu with MU, obtaining Driver.mb .4)Use the PackMU subsystem to convert Driver.mb to Driver.br .]gp c8q]r-q7Br ]q]r-q7Br Yq]r-q 7Br]W$Ssr N"qi6 Gr:& Fa DX4. B2 >t ;>r: 9[ 75$ 6F8& 4H 1Ou .rN ,X) v rv r'avr/%?"jvrv,@7## ,@+,@rvrvr$vrvrF=ZOn the Harmonious Cooperation of XMesa and User Microcode2The code in MesaXRAM.mu must be assembled to begin at RAM location 20. The user mustassure this condition by including a predefinition (with no omitted labels) at the indicated place inDriver.mu; e.g.,%17,1777,0,L0,L1,L2,L3,L4,L5,L6,L7,L10,L11,L12,L13,L14,L15,L16,L17;If the user microcode includes the code to control a non-standard I/O device (e.g., a Trident disk),at least one of the labels in this predefinition will refer to an instruction used as part of the silentboot sequence (see Alto Hardware Manual, sections 2.4, 8.4, and 9.2.2). Prudence suggests that thelocations corresponding to tasks that are not intended to execute in the RAM be filled in withdummy instructions of the formLi:TASK, :Li;Thus, if Driver.mu contains no device control microcode, L0-L17 should all have this form. Ifthere is a space crunch, however, locations 0-17 may be used for ordinary microcode, though this is usually unnecessary. Loading ProcedureDriver.br can now be loaded using the (Mesa) RamLoad package. The facilities of this packageare defined in RamDefs.bcd, and are exported by the module RamLoad.bcd. These files may allbe found on [Ivy]Utilities. RamDefs.mesa contains adequate documentation for theuse of this package; the following Mesa code illustrates a typical use.BEGIN OPEN RamDefs;driver: MuImage _ ReadPackedMuFile["Driver.br"];IF LoadRamAndBoot[driver,FALSE] ~= 0 THEN SIGNAL BogusMicrocode;ReleaseMuImage[driver];END;The second parameter to LoadRamAndBoot controls whether a silent boot is performed andshould be FALSE unless it is necessary to alter the set of running tasks (as is required whenadditional device control microcode is initialized). LoadRamAndBoot returns the number ofmismatches between the constants specified in the microcode file and those present in the Alto'sconstants ROM. If this number is non-zero, the microcode cannot execute properly on thismachine.Note to the nervous: Since RamLoad is a Mesa program, it must exercise caution to avoid smashing the emulator onwhich it is running. As long as the procedure above is meticulously followed in constructing Driver.br, RamLoad willbe able to load the RAM without committing suicide.There and Back AgainThis section describes mechanisms for transferring control between the Mesa emulator and user-supplied microcode. It assumes that this microcode is, in effect, implementing "extendedinstructions", and the linkage mechanisms described are suitable for this purpose. Device drivermicrocode (e.g., for a Trident disk) executes in a different hardware task and therefore does notrequire these linkages.The hardware-defined linkage mechanism between control memory banks is somewhat precarious.Opportunities for errors arise because of way the "next address" field of the microinstruction isinterpreted when SWMODE has been invoked (see section 8.4 of the Alto Hardware Manual). Thething to remember is that whether you are in ROM1 or RAM, to get to the other memory youmust specify an address with the 400 bit on (i.e., BITAND[address,400B] = 400B). If you preserve ft9G br v r/ `ve ^vr [vC X0r22 VA' T;( S8-1 Q NA Jvr7w IJ@8r Eu BvrG Av rv r ?\"v r( =G :exj yx 8yxyxyxy x 7yxyxj yxjyx 5my xyx 3 0vr y r0 . xr9 -&&y r +~-3 )B (. %wG* #u "@3 At r^ J)0 O  urH R F [@! X G c-ur : >][On the Harmonious Cooperation of XMesa and User Microcode3this invariant, your Alto will probably avoid most black holes.The Mesa JRAM InstructionMesa has a bytecode, JRAM, that is a straightforward mapping of the Nova JMPRAM instruction.JRAM takes the top element off the stack and dispatches on it, doing a SWMODE in the sameinstruction. The microcode therefore looks approximately like this:JRAM: IR_sr17, :Pop;pops stack into L, T; returns to JRAMrJRAMr:SINK_M, BUS, SWMODE;L_0, :zero;Thus, at entry to whatever microcode JRAM jumps to, L=0 and T has the target address of thejump.Getting back to ROM1 is equally straightforward. User microcode should terminate with:SWMODE;sigh...SWMODE and TASK are both F1s:romnext;(... and we can't TASK here)romnext is defined in MesabROM.mu, as are all the registers and other symbols used by the Mesaemulator.The safest way to force a microinstruction to a specific address in the RAM is to use MU's '%' pre-definition facility. For example,%1,1777,440,MyCode;MyCode:. . . ;start of user-written microcodewould enable the Mesa procedure MyCode (defined just below) to transfer control to themicrocode at MyCode.Setting Up a JRAM in MesaThe easiest way to access microcode in the RAM is by declaring a procedure to invoke it as follows:locationInRAM: CARDINAL = 440B;MyCode: PROCEDURE[arg1: AType, arg2: AnotherType] RETURNS [result: AThirdType] =MACHINE CODE BEGINMopcodes.zLIW, locationInRAM/256, locationInRAM MOD 256;Mopcodes.zJRAMEND;When MyCode is invoked, the arguments are pushed on the evaluation stack, then a transfer tolocation 440 in the RAM occurs. The microcode is responsible for computing result and placing iton the stack (details appear below). The return sequence described above will then cause executionto resume immediately after the invocation of MyCode. ft9G br? ^u [rC Y K X0D Tv ) S9  Q NBr= L IKW Ev)# DT) Arv r4 ?] <8+ :f" 7v 3 ) 0xryr0 . vr +u (2r#@ $y xj yx !yxj yxyxyxy xjyxyxy xj``Dy xyxyxyx`y `x ryrQ 1yr UG .yr" f>UOn the Harmonious Cooperation of XMesa and User Microcode4The Mesa StackThe Mesa stack is implemented by 8 S-registers named stk0, stk1, ..., stk7, with stk0 being thebase of the stack. An R-register, stkp, indicates the number of words on the stack and is thus inthe range [0..8]. To obtain values from the stack in the general case, therefore, requires a dispatchon stkp, but there is an important special case. If MyCode is invoked in a statement context (i.e.,one in which it stands alone and is not a term of an expression), the stack will be empty except forarg1 and arg2, which will therefore appear in stk0 and stk1, respectively. In this case stkpwill be 2 at entry, and the microcode should set it to 1 before returning to ROM1. result shouldalso be stored in stk0. It is frequently useful to restrict the use of MyCode to statement contextsso that the microcode can take advantage of the known stack depth. Note: this assumes that values oftype AType, AnotherType, and AThirdType are each represented in a single word. Multi-word quantities are stored inadjacent stack words, with consecutive memory cells being pushed in increasing address order.An argument or return record exceeding 5 words in length requires special handling that is beyondthe scope of this document. See Roy Levin for details.Other Emulator StateThe Mesa emulator has a number of temporary registers that may be freely used by code enteredvia JRAM. The following list identifies all registers used by the Mesa emulator, their intendedfunction, and whether they may be used as destroyable temporaries by user-supplied RAMmicrocode:RegisterTypeDestroyableFunctionby RAM codempcRNoprogram counterstkpRNostack pointerXTSregRNoXfer trap statusibRNoinstruction bytebrkbyteRNoXfer state variable; overlaps AC3clockregRNohigh resolution clock bitsmxRYestemporary during Xfer; overlaps AC2saveretRYesholds return dispatch values; overlaps AC1newfieldRYesused by field instructions; overlaps AC0countRYestemporary for countingtaskholeRYestemporary for holding things across TASKstempRYesgeneral temporarytemp2RYesgeneral temporarylpSNolocal frame pointer (+6)gpSNoglobal frame pointer (+4)cpSNocode segment pointerstk0-7SNo8 evaluation stack registerswdcSNowakeup disable counter (interrupt control)ATPregSYesalloc trap parameterXTPregSYesxfer trap parameterOTPregSYesother trap parametermaskSYesused by field instructions; smashed by BITBLTindexSYesused by field instructions; smashed by BITBLTalphaSYestemporary for alpha byte; smashed by BITBLTentrySYesXfer and field temporary; smashed by BITBLTframeSYesALLOC/FREE temporary; smashed by BITBLT ft9G bu ^r"vrvrvrvr ]' vr; [f Yvryr$ur X/Y Vyryrvrvrv Tr=yr S7 vr2yr QBw P zwz wz w($ N] K7rR I7 F@u BrP AIW ?)- = @: )9 @5!@)@4Q!@) @2!@)@1G!@)@/!@)!@.=!@)@+3!@)#@)!@)*@()!@)(@&!@)@%!@))@#!@)@"!@)@ !@)@!@)@!@)@|!@)@!@)*@!@)@h!@)@!@)@^!@)-@!@)-@T!@)+@ !@)+@ J!@)' H =]On the Harmonious Cooperation of XMesa and User Microcode5mySYesXfer temporary; smashed by BITBLTunused1SYessmashed by BITBLTunused2SYessmashed by BITBLTunused3SYessmashed by BITBLTUser microcode should endeavor to TASK within 5 microcycles of entry. It should also TASK asclose to the end as possible. Ideally, the penultimate instruction before returning to the emulator would TASK,but unfortunately SWMODE must appear in the same instruction and both are F1s. The Mesa emulator tries toTASK at least every 12 microcycles; user microcode should observe the same guideline.The Mesa emulator does not check for pending interrupts on every instruction. It does so onlywhen it must fetch a new instruction word from memory. Therefore, user microcode that sets apending interrupt condition must not expect that the interrupt will be noticed by the emulatorimmediately upon return to ROM1.Distribution:XMesa UsersMesa Group ft9G@br!@)!@`!@)@_!@)@]!@) X-0 WwQ Uk<r SU PtM NE M$U K| D C6 A  AG=& TIMESROMAN  HELVETICA TIMESROMAN LOGO TIMESROMAN  TIMESROMAN GACHA  TIMESROMAN HELVETICA  HELVETICA   TIMESROMAN ;}j/" Dmicrocode.bravoLevinOctober 6, 1978 9:51 AM