Wildflower Manualby B. W. LampsonAugust 18, 1978 4:44 PMThis document describes the operation of a small processor called Wildflower, from themicroprogrammer's point of view. The machine is intended for use in a workstation. It has5provision for efficient execution of Mesa code in a manner essentially compatible with otherOIS processors, and for controlling a display with 1024x808 visible points refreshed at 36 Hz,a Shugart SA-4000 disk, an Ethernet connection and an 8080 bus. Ordinary Mesainstructions execute slightly faster that 1 Mips with the display running. Main memory can be128k or 256k words, implemented with 64k RAMs; there is parity but no error correction. A10128k Wildflower is implemented with the equivalent of 200 16 to 20 pin IC packages,including all the input/output controllers.Warning: this is a draft only. There are errors,inconsistencies and omissions. 15This document is for Xerox internal use onlyThis document is for Xerox internal use onlyXEROX20PALO ALTO RESEARCH CENTER3333 Coyote Hill Road / Palo Alto / California 94304ЪНgО^╛pТНgО\1qr НgОW;sНgОREТэПRТщНgОP²Т⌡П=Т°НttНgОNУsТ·П3Т÷П)НgОMMТ▄П^НgОK╔ТП2ТНgОIЩТ├ПJТ┤НgОHUТ⌡П7Т°П#НаtНgОFґsТСП'ТТП,НgОEТП+НgО?pТыП1НgОQh.▐DRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM11. IntroductionThe purpose of this document is to describe the operation of a small processor called Wildflower,from the microprogrammer's point of view. The machine is intended for use in a workstation. Ithas provision for efficient execution of Mesa code in a manner essentially compatible with otherOIS processors, and for controlling a display with 1024x808 visible points refreshed at 36 Hz, a5Shugart SA-4000 disk, an Ethernet connection and an 8080 bus. Ordinary Mesa instructionsexecute slightly faster that 1 Mips with the display running. Main memory can be 128k or 256kwords, implemented with 64k RAMs; there is parity but no error correction. A 128k Wildflower isimplemented with the equivalent of 200 16 to 20 pin IC packages, including all the input/outputcontrollers.101.1 Conventions and notationNumbers in this document are decimal unless followed by B; thus 10-12B.Names of registers, busses and microinstruction fields are in small caps (STKP, IOIN, A). Names offunctions encoded in the microinstruction's F1 and F2 fields are in bold (MapRef, Y lcy 8).Bits in registers are numbered from the most significant bit (0) toward the least significant bit.15Fields within registers are given by following the register name with a dot and a pair of numbers:Q.2-4 describes the 3 bit field of the Q register beginning with bit 2 and ending with bit 4 inclusive.Q.2 is short for Q.2-2.The symbol "_" is used to mean "is replaced by." Thus Q.2-4 _ 2 means that the 3-bit field of Qincluding bits 2, 3 and 4 is replaced by the bit values 0, 1 and 0 respectively. The symbol "=" is20used to indicate an equality test.Certain prefixes are used with standard meanings: a prefix "p" means "pre", i.e. one cycle early; aprefix "r" means reset.Uses of "in" and "out" always refer to the processor. Thus IOIN is data coming from an io device,and MEMOUT is data going to the memory.25Memory is by convention divided into 256-word pages. Page n thus contains addresses 256*n to256*n+255 inclusive.2. Control sectionTime is divided into units called clicks. One click corresponds to one main storage reference.During one click, exactly three cycles occur; in each cycle, one microinstruction is executed. A cycle30lasts for 100 ns, and a click therefore lasts for 300 ns.2.1 TasksThe machine supports five tasks, each with its own micro-PC: emulator, disk, display, ethernet anduBus. Clicks are numbered modulo 8; consecutive clicks numbered 0..7 make up a round, whichlasts 2.4 us. Each click is a potential click for exactly one of the input-output tasks; the choice of35task depends on the click number, and is made according to the schedule below. If this task isrequesting service, its potential click becomes a service click, and it executes three instructionsduring the click; if not, the click becomes an emulator click, and the emulator executes threeНЪОeЗpТНtwТjtwtwtТ└pН!иОdRtНGіОfПНО_xТНО[ЙtТ║ПDТ╒НОZeТ П9Т⌡П'НОXЮТ╟Т╠ПSНОW[Т╦П^Т╧ННОUжТъПGТЮНОTQТєП#Т╔П;НОRлТ▄П>Т█П"НОQGТ╔П6ТіП)НОOбНaНОJОyТНОGцtП8wtwtНОD≈Т≈П:Т≤wtwtwtНОCТЙП,wtwt ТКxtxtНО?ФТаТбПDНaНО>aТ≤ПOТ≥НО<эwtТ┤П&wtП.Т┬НО;WwtТwtНО8+Т▌П"Т▐wtП'wНО6іtТ▓ПQТ⌠НaНО5!ТП"НО1УТ▓Т⌠ПEНО0pТНО-DТ▌ПГ\╨eDRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM2instructions. The schedule is:Click numberTask0display1disk2display53disk4ethernet/uBus5display6disk7ethernet/uBus10This assignment is for a 40 MHz display; the display gets serviced three times in a round, and gets32 bits each time, for a bit rate of 32*3/2.4=40 bits/us=25 ns/bit. To paint a line of 1024 bitstakes 32 clicks. Adding 7 clicks (5.1 us) for horizontal retrace gives 13 rounds or 31.2 us per scanline. Now multiplying by 875 gives 27.3 ms per frame, which corresponds to a refresh rate of 36.63Hz. The disk gets serviced at least every 900 ns, which allows the Shugart SA-4000 disk, with a15data rate of one byte every 1.1 us, to have one byte data paths. The ethernet gets serviced twiceevery 2.4 us, which is slightly more than double what is needed for its data rate of one byte every2.7 us, but avoids latency problems. The uBus gets any clocks the ethernet doesn't want, whichallows it a peak bandwidth of 3 Mbits/second when the ether is running, double that when it isn't,and a maximum latency of 13 clicks (since the ether might take two consecutive clicks), or 4 us. All20of this is far in excess of its anticipated requirements. Thus all input-output data paths are one bytewide, except for the display which loads directly from the 32-bit memory outputs.2.2 Microinstruction addressingThe machine has 2048 words of micro-instruction (I) memory, addressed by a 12 bit next instructionaddress (NIA.0-11); the extra bit allows for each expansion to 3072 or 4096 words of I memory.25NIA.3-11 are supplied by an 11 bit field in each instruction called INIA.1-11, with possiblemodifications discussed below; this means that there is no block or page structure imposed on the Imemory.Branching is done by oring into INIA.11 of the next instruction. If INIA of the next instruction iseven, this sends control to INIA or INIA+1, depending on the failure or success of the branch30respectively. If INIA is odd, the effect of the branch is cancelled. For example:100ALU=0101GOTO[200]will send control, after executing 101, to 200 if ALU#0 in 100, to 201 if ALU=0 in 100.There are several kinds of multi-way branch. Ydisp4 ors Y.12-15 into INIA.8-11; it is illegal if Y35depends on data from SU or MEMIN. X12-13Disp ors X.12-13 into INIA.10-11. NextMacrosubstitutes IB.0-7 for INIA.4-11, which must be 0; it is intended for dispatching on a Mesa bytecode,and must be executed in the second instruction of a click. It is illegal to do any other branch ordispatch together with a NextMacro (see section 5.1).There are also two 4-bit subroutine link registers (LINK1 and LINK2), intended for the emulator's40use, which can be loaded from NIA.8-11 (call) and can be ored into INIA.8-11 (return). Both calland return must be done one cycle in advance to work properly for subroutine linkage, and toemphasize this they are called pcall1/2 and preturn1/2; thus:IANIAinstruction 77100pcall145100200goto(200)ЪН_ОeЗpТНtwТjtwtwtТ└pН#)ОdRtНЩОfПНgО_ТН]О\ЎyТ─ННПОZftННПОXАННПОW\ННtНПОUвННПОTRННПОRмННПОQHННПОOцННаНgОL≈Т█П9Т▌П*НgОKТ╚П`НgОI█Т≈ПYТ≤НgОHТ└П(Т┘П;НgОF┐ТїП?Т╗П!НаНgОDЧТ÷ПNТ═НgОCyТ■П$Т∙П?НgОAТТ╞П>Т╟П!НgО@oТ▐ПSТ░НgО>ЙТ┌ПaТ┐НаНgО=eТ│П?Т┌П)НgО;ЮТПQНgО7ЮyНgО4ЄtТ┌П1wtТ┐НgО3/ТІwtП%ТЇП$wtНаНgО1╙wtТЭТЩП/wtНgО0%Т▄ПaТ█wНgО.═tНgО+tТ÷wtТ═ytwtНgО)ОТгwtwtТхП2НаНgО(jТwtП=Н]О&Н░wtН]О$█Н░wtНgО"5ТУП'ТЖ wtwt НgО ТґП$Тў xtwtwtwНаtНgО└ТПwtwtx twtТЯwtxНgОЪtТ┴wtwtП;Т┼НgОzТ·Т÷П[НgОУТxtНgОиТ╟П4wtwt Т╠НаНgОDТіwtТїwtНgО©Т╩Т╪ПMНgО:ТП=Н]ОБwН░НIt Н]О┼Т─Н░НIНаН]ОН░НIЪ╦а Ў>Г]M╛DRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM3...200201nop201202preturn1202101goto(1)will save 100 in LINK1 and will execute the instructions in the order shown. The next instruction5executed after 202 will be 101. Note the responsibility of the programmer to arrange for suitablealignment of the instruction to be returned to, and for oring in enough bits in the final instructionof the subroutine (just a 1 in this case).Any form of branch, dispatch or return may be executed in any instruction of a click, except for anIB dispatch. A return may be combined with a branch or dispatch, in which case both modifiers are10ored into INIA.2.3 Microinstruction format and summaryThe microinstruction has 44 bits, divided as follows:4A (addresses R and C)4B (addresses R)153MUX control3ALU control3LOAD control1CIN (carry in for arithmetic; also addresses SU)1ENU (enables U (or S if ENS) for reading onto X)201ENS (enables S for reading onto X, if ENU is set; enables SplitAdder)1ENW (enables W for reading onto X)1SU_ (if set, writes S if ENS, otherwise U)4F1 (addresses W and U; supplies the SC value; see below for other uses)4F2 (see below)2511NIA (next instruction address)3unassignedThe F1 and F2 fields specify a variety of miscellaneous functions, not all of which are yet defined.In particular, additional branch conditions will be defined. The current, tentative encoding of thesefields is as follows ("*" means that the function is meaningful only for the emulator):30F1Addresses U (if ENU)Supplies SC value (enable TBD)Addresses W (if ENW): _Y lcy 8 (only if Y_A), _MEMIN, _IB*, _IBL*, _IBH*, _IOIN, _STKP35Any of the uses above disables the uses belowSTKP operations: push* (STKP_STKP+1); pop* (STKP_STKP-1); STKP_*IB_*cyclepEmuU40Disk operations: KData_, KCtl_, rKReqEther operations: EData_, ECtl_, rEReqDisplay operations: Display_, rDRequBus operations: UData_, UCtl_, rUReqЪНЪОeЗpТНtwТjtwtwtТ└pН!иОdRtНGіОfПНЩО_НЩО]▒Н0НИНЩО\Н0НИНЩОZ┤Н0НИНОX/Т÷wtП7Т═ННОV╙Т·Т÷ПCНОU%Т■ПLТ∙НОS═ТП*НОPtТ┴П\Т┼НОNОwtТ┌ПBТ┐НaНОMjТ wtНОIjyП'НОF>tП5НЩОCНвwtwtwtНЩОA█НвwtwtНaНЩО?5НвwtНЩО=╟НвwtНЩО<+НвwtНЩО:іНвwtП*wtНЩО8NНвwt wtwtwtНaНЩО6иНвwt wtwtwtНЩО5DНвwt wtwtНЩО3©НвwtwtwtwtНЩО1gНвwtwtwtwtП!НЩО/БНвwtНaНЩО-┼НвwtНЩО+2Нв НО(Т°wtwtП*Т²П-НО&│Т┼П<Т▀П*НО$ЭТПWНaНЩО!пwНЩОxt wtwtНЩОСwtНЩОn wtwtxzxt ztxztxztztztНвОИxztxzНatНЩОdyП-НЩОъwtxtw txtwtzxtНЩОZzxtНЩОуxНЩОPНatНЩОкxtxtxНЩОFtxtxtxНЩОаtxНЩО Г[°DRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM4F2MEMOUT_Dispatches: NextMacro*, AlwaysNextMacro*, YDisp4, X12-13DispSubroutines: pCall1*, pRet1*, pCall2*, pRet2*Branch conditions: F<0, Y<0, X<0, Xodd, F=0 (logic only), Carry, PageCarry,5pCt=Emu, Refill*, EExceptionIBPTR_1*, IBPTR_2*, IBPTR_3*, IBPTR_4*RH_*?, MapRef*?CIN=PC16*_KData, _KStatus10_EData, _EStatus_UData, _UStatus2.4 InitializationThe machine is initialized by an asynchronous external reset signal. While this signal is true, eachtask in turn is started at 0. The tasks are run in a fixed order during each round: Emulator (415times), Disk, Ethernet, Display, uBus. They get themselves sorted out by testing the pCt=Emubranch condition in the first cycle of the click. If this condition is true, the emulator task isrunning, and the microcode writes 0 into an R register RT and sends control to the start of theemulator's microcode. Otherwise it dispatches on RT and increments it by 1. As a result, the fournon-emulator tasks will dispatch on 0, 1, 2 and 3 respectively (the emulator must shake the20dispatch). As long as reset remains true, these dispatches will be ineffective, since each click isforced to start again at 0. When reset finally is removed, however, the dispatches will take effectand initialization will be complete. Suitable microcode to accomplish initialization is:IoVec:Dispatch table mod 4 [Kinit, Einit, Dinit, Uinit]Start:AT[0], pCt=Emu?, UT_RT25goto[Io, Emu], sink_UT, Xdisp4Io:goto[IoVec], RT_RT+1Emu:goto[EmuInit], shake[7], RT_03. Arithmetic sectionThe arithmetic data paths are shown in figure 1. The processor has 16 fast R registers, and 256 slow30SU registers, divided into S registers and U registers as described below. There is also a special-purpose Q register which is intended for the exclusive use of the emulator. The R registers areaddressed directly by the 4 bit A and B fields of the instruction; two locations, whether the same ordifferent, may be read simultaneously. The U registers are addressed by F1, CIN, and the tasknumber; thus there are 32 U registers per task. Note that since CIN is part of the U address, care35must be taken in writing U using F_A and simultaneously doing arithmetic in the ALU, since CINwill affect the arithmetic. In all other cases of U references, a logic operation is being done andhence the value of CIN is ignored by the ALU. A function pEmuU allows any task to address theemulator's U registers instead of its own in the next instruction; it is illegal in the last instruction ofa click (since it would affect the next task).40The S registers are intended for the Mesa stack, and are addressed from the 4 bit stack pointer(STKP) register; there are functions to increment and decrement STKP, and it can be loaded from Yor read onto W. CIN also contributes to S addressing, and there are in fact two separate sets of 16 Sregisters, selected by CIN. There is only one STKP, however. This is not intended to be a usefulfeature. See section 5.2 for more details on S.45Н_ОeЗpТНtwТjtwtwtТ└pН#)ОdRtНЩОfПН]О_wН]О\ЎzxН]О[9tТxtxtxtx Н]ОYЄtxtxtxtxtН]ОX/zxtzxtzxtzxtzxtxНttН7ОV╙xtxН]ОU%zxtzxtzxtzxtН]ОS═zxtxtН]ОRzxtН]ОP√xtxНаtН]ОOxtxН]ОM▄txНgОI▄yНgОF`tТ√ПPТ≈НgОDшТўТ╞ПCНаНgОCVТ╦ПIТ╧xНgОAяtТкП5ТлП-НgО@LТўП(Т╞П7НgО>гТ▄П#Т█П@НgО=BТБПLТЦНаНgО;ҐТ╦П$Т╧П@НgО:8Т═Т║ПOНgО8ЁТПYНSО5┤НП1НSО4ННаНО2}НSО0ЬННSО/sННgО(ЬxНgО%лtТ─П?Т│wtНаНgО$GwtТўwtТ╞wtП8НgО"бТ╣wtПHwt ТІНgО!=Т▀wtwtТ▄П>НgО╦ТцП,wtwtwtТдНgО3Т Т⌡wtП&wtwt НаНgОўТ²wtwtП7wНgО)tТ╘П3wtТ╙НgОєТ∙Т√ wtП$xtНgОТ┴ wtТ┼ytП6НgО ТП.НаНgОnТІwtТЇП?НgОИwtТ⌠П;wtТ■wНgОdtТ├Т┤wtwtwtП;wНgОъtТ╒wtwtТёП.НgО ZТП.wtНаЪПа =ГZЬбDRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM5The fact that SU is slow means that an SU register cannot be the operand of an arithmetic operation,or be loaded from the results of an arithmetic operation, or from MEMIN.The ALU has two input multiplexors which select its two operands under control of the MUX field ofthe instruction, as shown in the figure. It is capable of three arithmetic and five logical operations,under control of the ALU field, and its results can be put on the Y bus, or written directly into Q, or5written into R directly or with a possible left or right shift by 1 bit, under control of the LOAD field.Slow sources (SU, MEMIN, and IOIN) may not be the operands of arithmetic operations.The R register addressed by B may be written from the ALU output F, possibly shifted left or rightby 1; this is legal whether or not that register is used as an operand in the same instruction. Q maybe written from F, or from the old contents of Q shifted left or right by 1. The SU register10addressed may be written from the Y bus, but not with the result of an arithmetic operation or withMEMIN, and it may not be both read and written in the same instruction.Possible values on the X bus are the addressed SU register (selected by ENU), the contents of the Wbus (selected by ENW), an 8-bit constant (specified in a manner TBD) or a four-bit small constantSC taken from F1 (enable TBD). The constant occupies X.12-15, and X.0-11 are zero.15Possible values on the W bus (with 0 in any unmentioned bits) areY lcy 8: legal only if the LOAD field specifies B_F & Y_A.MEMIN: a slow source, i.e. no arithmetic and no writing into SU.IOIN: data coming from the io device selected by F2 (it would be nice if we could find a wayto avoid the use of F2 here, perhaps by using the task number and some random piece of20information like CIN).IB: 8 bits coming from the emulator's instruction buffer in bits 8-15; see section 5.1.IBL, IBH: the 4 lsb or 4 msb of the instruction buffer, in bits 12-15.STKP: the 4-bit stack pointer, in bits 12-15.3.1 Shifts and cycles25The LOAD field of the instruction allows single and double shifts of Q and an R register, as shown infigure 1. Normally, zeros are shifted in at the ends, and on a double shift F.15 and Q.0 areconnected. The cycle function changes a double shift to a double cycle, connecting F.0 and Q.15 aswell as F.15 and Q.0. It changes a single left shift to shift PC.16 (see section 5.4) into R.15, and asingle right shift to shift Q.15 into R.0. Need a picture for this.304. MemoryA memory reference is always started on the first instruction of a click, using the contents of Y asthe 16 lsb of the memory address MAR.0-19. The 4 msb of MAR come from an auxiliary memorycalled RH.0-3, which is addressed by A. RH can be loaded from X.12-15 using RH_. If ALUspecifies an arithmetic operation, its carry is added to RH to produce the 4 msb of MAR.35If the memory operation is to be a store, the data to be stored must be supplied on Y, andMEMOUT_ must be specified, during the second instruction of the click. Otherwise the operation isassumed to be a fetch.Data from the memory is available on MEMIN during the third instruction of the click unless it wasa store. The data can be put onto W and thence onto X, and thence sent to the ALU. Only a logic40НЪОeЗpТНtwТjtwtwtТ└pН!иОdRtНGіОfПНО_Т┌ wtwtТ┐П$НО]▒ТПBwtНОZeТ│wtТ┌П4wtНОXЮТ▌П:Т▐П.НОW[Т└wtТ┘wtwtННОUжТ└wtПOТ┘wtНОTQТ wtwtwtП3НОQ%Т⌠wtwtТ■wtwtНОO═Т└П8Т┘П)wtНОNТкwtТлwtП"wtНaНОL√Т┘П!Т├wtП@НОKwtТПBНОGЕТ░wtwtwt Т▒wНОF`tТ·wtПMНОDшwtТwtП&wtwtНaНОA╞wtП)НЩО?WwtwtwtwНЩО<ЪtП8wtНЩО:їwtТ┬П-wtТ┴yП'НЩО9"ТІ{yП0ТЇНatНЩО7²yТ{tНЩО5EwtТщТчПAНЩО2МwТtП>НЩО0∙wtП)НО,∙yНatНО)iТ│wtП=wtТ┌wtНО'ДТкТлПDwtwtНО&_Т▀xtП?wtwtНО$зТ°wtwtП-wtwtТ²НО#UТwtwtyНatНОзxНОўtТ П@Т⌡wtНО)Т╒ ТёwtwtНОєТкwtwtwtwtТлzxtwНОtТШП9wtТЭ wtНaНОСТяПTwtНОnztТ█ПJТ▌НОИТНОҐТ█П%wtТ▌НО 8Т┘П#wt Т├wtП+Нa a Я=Г^иDRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM6operation is possible, and if Y_F is specified the Y data may not be sent to SU.During a fetch the memory actually supplies 32 bits from the even-odd word pair addressed byMAR. The 32 bits can be sent to the display (using Display_) or to the instruction buffer (usingIB_) in the third instruction of the click. This can be done independently of putting MEMIN on W.If MapRef is specified in the first instruction, rather than using RH,,Y.0-15 for MAR, 377B,,RH,,Y.0-75are used instead. This makes it convenient to reference a map stored at the top of memory, on theassumption that the page size is 256 words. The intended use of this facility is illustrated by thefollowing microcode for making a mapped reference from the emulator. The format of a map entryis assumed to be0-78 lsb of real page number108unused9-11referenced, dirty and write-protected bits (not present=dirty and wp)12present and references (i.e. read OK)13present, referenced and dirty (i.e., write OK)14-152 msb of real page number15 Ti are R registers:MAR_Q_address, MapRefT1_Q and 377BT2_MEMIN, RH[T1]_MEMIN, X12-13Disp20-- now proceed with the reference as usual.-- the first instruction takes the dispatch on the fault bits supplied in the third cycle of theprevious click. For a read, MapFault should be 1 mod 3, resulting in a 2-way branch onneed for special action; for a write, MapFault should be 2 mod 3 to get the same effect. Ifaction is required, it is necessary to decode T2.9-11 to figure out what has happened: page25not present, write protect fault, set referenced bit, set dirty bit. Q has the 16 lsb virtualaddress; the 4 msb must be retrieved from some know place.MAR_T1+SplitAdder[T2,0], goto(MapFault). . .5. Mesa emulator support30The instruction buffer (IB) and the stack (S, STKP) and their associated functions, as well as theSplitAdder and Cin=PC16 functions, are provided to speed up the emulation of Mesa bytecodes.5.1 Instruction bufferThere is a 5-byte instruction buffer (IB) which holds the next few bytes of the Mesa instructionstream. Its operation is somewhat complicated; this paragraph gives a birds-eye view, and the rest35of this section supplies precise details; figure 2 contains a detailed example. Bytes 1..4 can beloaded from a storage doubleword with the IB_ function. Associated with the five bytes is a pointerregister IBPTR. Its possible values are 0..6, and for the values 0..4 the corresponding byte of IBappears on the IB bus. If IBPTR>4 the value of IB is undefined. The IB bus can be read onto W orused for a dispatch; in either case IBPTR is advanced to point to the next byte. Either the left or40the right 4 bits can also be read onto W.The five bytes are called IB0, IB1, IB2, IB3 and IB4. The IB_ function must be executed in the thirdcycle of a click, immediately after AlwaysNextMacro; it doesIB1 _ MEMIN.0-7Н_ОeЗpТНtwТjtwtwtТ└pН#)ОdRtНЩОfПНgО_ТwtwtwtНgО[ЙТІПOТЇНgОZewtТіП1xtТїНgОXЮzxtТ▌ПTwtТ▐wtНgОUЄТ■xtП'Т∙wt wtwtwtНtНgОT/Т▀П;yt Т▄НgОR╙Т╒ПNТёНgОQ%Т┐ПIТ└НgОO═ТН]ОMHН0НаН]ОKцН0Н]ОJ>Н0ПEН]ОH╧Н0П%Н]ОG4Н0П.Н]ОE╞Н0НаНgОB┐ytwt Н]О@+wtwtН]О>іwtwН]О=!twtwtwtНаО;юН]О:_wtП(Н]О8зТ▓П"Т⌠П>Н]О7UТ·П/Т÷П(Н]О5пТ┬П>Т┴Н]О4KТ⌠Т■ПBНаН]О2фТўП9Т╞wtН]О1AТП:Н]О/╪wtП$Н]О.7НgО'╪xНаtНgО$░Т╩wtwtП,Т╪НgО#ТєxtТ╔П*НgОyТНgОъtТІП&wtП,ТЇНgОZТ≈П>Т≤П%НаНgОуТаП[ТбНgОPТ─П%Т│zxtП7НgОкТЇwtП$Т╦П/wНgОFtТ┘wtТ├wtwtwtwtНgОаТ²Т·wtП;НаНgО<ТП'wtНgОТ⌠wtwtzxtП!Т■НgО▀ТП$xtН]О 3wtwtlа Л=Г^²DRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM7IB2 _ MEMIN.8-15IB3 _ MEMIN.16-23IB4 _ MEMIN.24-31IB0 _ IB if IBPTR=0, otherwise undefinedThere are also four functions IBPTR_i, i IN [0..3] which set IBPTR as well as loading IB from MEMIN5as shown.If IBPTR=i (i IN [0..4]), then IBi will appear on IB; otherwise the value of IB is undefined. The ideais that IB1-4 are the four bytes of a doubleword, and IB0 is an overflow byte which is used to smoothout the fetching of another doubleword, as described below.Either IB, or IBH (IB.0-3), or IBL (IB.4-7) can be read onto W right justified. Zeros appear in bits not10supplied from IB. When IB (but not IBL or IBH) is read, IBPTR is advanced, i.e. incremented by 1, sothat if IBi was on IB before, IB(i+1) will be on IB afterwards.The NextMacro function can be used to dispatch on IB. If IBPTR <=2, then IB replaces NIA.4-11(which must be 0), and IBPTR is advanced. In this case, at least two bytes remain in IB, so that atwo or three-byte instruction can retrieve its operand bytes without having to worry about finding15the buffer empty (lines 4, 6, 7, 9, 1, 12, 16 in figure 2). If IBPTR>2, then 0 or 1 is ored into NIA,depending on whether IBPTR<5 or not, and IBPTR is not advanced (lines 2, 3, 10, 11, 15, 18, 19).The AlwaysNextMacro function dispatches in any case, and advances IBPTR mod 3; thus 3 isadvanced to 0 and 4 to 1. The idea is that control goes to 0 or 1 when IB needs to be refilled. Therefill code will fetch the next doubleword in the first cycle, repeat the dispatch with20AlwaysNextMacro in the second cycle (except when IBPTR was 5; see below), and load IB fromMEMIN with IB_ in the third cycle (lines 5, 8, 17). Since refill may occur with two bytes left in IB,there may still be one byte left after the dispatch; this last byte is saved in IB0 by IB_ (lines 8, 17).Since refill occurs unless there are at least three bytes in IB, there will always be at least one byteleft when the next macro is started, except in the case of a three-byte instruction which occupies the25last three bytes of a doubleword; hence is is always possible to overlap the refill fetch with aninstruction dispatch, except in this case, which results in IBPTR=5 at the time of the NextMacro,and hence in a dispatch to 1 (line 14). In this case the AlwaysNextMacro dispatch is not possible,and the next macro cannot be dispatched until the following click (line 15). The resulting lost clickis only paid on 1/4 of the 3-byte instructions, however.30When a jump instruction is executed, the microcode must figure out which byte is being jumped to,and execute the proper IBPTR_i function in the third cycle of the click in which the new instructiondoubleword is fetched. It can then dispatch with AlwaysNextMacro in the next click, and thisdispatch can be overlapped with a refill if the jump was to byte 3 or 4, since in this case it is notnecessary to wait for the NextMacro to detect the need for a refill.355.2 StackA special set of 16 registers (S) is provided to hold the Mesa evaluation stack, together with a 4-bitregister (STKP) to address them. There are functions to increment and decrement STKP (push andpop), and it can be read onto W.12-15 and loaded from Y.12-15. An S register behaves just like a Uregister. Note that the operations on STKP act at the end of the instruction, so that S is addressed40by the old value of STKP during the instruction.There are actually two sets of S registers; the set to use in a particular cycle is selected by the CINbit. It is expected that CIN will always be 0 when S is referenced.The intended use of S registers is that the top of the stack will be kept in an R register (called TOS),and that STKP will be kept pointing to the S register containing the second word on the stack. This45means that the top two words are immediately available for a (non-arithmetic) binary operation.НЪОeЗpТНtwТjtwtwtТ└pН!иОdRtНGіОfПНЩО_wtТwtНЩО]▒wtwtНЩО\wtwtНЩОZ┤wtwtНОX/Т▌zxytytwtwtwtwНtНОV╙ТНОTRТ┴wtytytwtw{twtТ┼wtНОRмТ┌wtП)wtП"Т┐ НОQHТП;НОNТ└wtwtwt wtwtwtТ┘НaНОL≈Т└ wtwt wtwt wtТ┘ytНОKТw{twtw{wtwtНОGФТ√xtП!Т≈wtwt wt wtНОFaТ°wtП/Т² wt НОDэТ÷П.Т═П4НaНОCWТ▓П?Т⌠wtwtНОAрТ÷wtwtТ═НО@MТьxtТыwtНО>хТ┐ПHwtТ└НО=CТ;Т<ПGНaНО;ЎxtТ╪П"wtТҐwtНО:9wtТ▌zxtТ▐П5wtНО8ЄТ▄Т█П>wtzxtНО5┬Т⌡П=wtТ°НО4Т└П<Т┘П*НaНО2~ТҐПaНО0ЫТ╗П8Т╘wtxtНО/tТ■П:xtТ∙НО-ОТ┴П[Т┼ НО,jТwtП%НaНО)>Т└Т┘ПJНО'╧Т├zxytП,Т┤НО&4ТюТаП%xtНО$╞Т≤П4Т≥П1НО#*ТxtП!НaНО*yНОЧtТ▐wtТ░П-НОyТ÷ wtТ═П1wtxtНОТxtТ┤wtwtwtТ┬wНОotТ≥П'wtytТ wtНaНОЙТyt wtНОЎТ∙Т√wtПDwНО9tТwtwtНО Т├wtП,Т┤wtwtНО┬Т┴wtwtТ┼НaНОТЇ Т╦ПUЪNa ╪>Г]O$DRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM8These are simply programming conventions, however.5.3 Split adderThe split adder feature ors a bit into the MUX field of the microinstruction for bits 8-15 only. Theeffect is to change the selection of G and H inputs to the ALU for bits 8-15, as follows (* is theoperation specified by the ALU field):5A * Q becomes0 * AA * BbecomesX * A0 * QbecomesX * Q0 * BbecomesX * 0The motivation for this feature is to allow an operation of the form TOS + (MDS + IB), by choosing10MUX=A*B, A=TOS, B=MDS and X=IB, and taking advantage of the fact that MDS has 0 in the 8lsb, while IB has 0 in the 8 msb.SplitAdder is invoked by the ENS bit (unless this kludge proves intolerable). If ENU is off, ENS hasno other function, so this encoding causes no problem. If ENU is on, selecting S automaticallyinvokes SplitAdder, with two consequences:15SplitAdder cannot be used when reading or writing U. If it is only wanted with arithmeticto Y, this is not a problem, since U cannot participate in arithmetic.SplitAdder is always invoked when S is selected. This isn't a problem when S is being read,since MUX will never have one of the values which is transformed by SplitAdder. Care isneeded when S is written, however, since only the righthand MUX values in the above table20can be used.5.4 PC.16The machine contains a single-bit register PC.16 which is intended to be used for the leastsignificant bit of the Mesa byte program counter; an R register called PC will be used for theremainder of the program counter. There is a function Cin=PC.16 which makes PC.16 the carry25into the ALU, and also complements PC.16 (at the end of the instruction, so that the old value isthe one used for the carry). The effect, when combined with PC_PC+0, is to add 1 to the 17-bitPC. PC.16 can also be left-shifted into an R register; see section 3.1.6. Input-outputWildflower does not have a general-purpose high performance input-output system. Instead, it has30specialized arrangements for handling three high-bandwidth devices: disk, ethernet and display. Italso has an microcomputer bus, on which low-bandwidth devices are supposed to live. Theadvantage of this scheme is that the disk, ethernet and display can be handled with a very smallamount of hardware. All three devices depend heavily on receiving a known amount of servicefrom the processor with latencies of about 1 us. The assignment of clicks to input-output tasks is35detailed in section 2.1.There is an input bus IOIN which allows data from the devices to be read onto X; this is a slowsource, which does not permit arithmetic or writing into SU. There is also an output bus IOOUT forsending data to the devices. It is not yet decided whether this will be Y or H. If it is Y, This is aslow sink, which cannot accept data from arithmetic, SU, or MEMIN. Functions for each device read40input data and status onto IOIN and load output data and control from IOOUT. Each device also hasЪН_ОeЗpТНtwТjtwtwtТ└pН#)ОdRtНЩОfПНgО_ТП2НgО[yНgОWЙtТ▐П+wtП2Т░НgОVeТ╔П%wtТіwtП6НgОTЮТwtНtН]ОR┬wТ─twtН+НТwН]ОQТ─twН+tНwТtwН]ОO~tТ─wН+tНwТtwН]ОMЫtТ─wН+tНwТtwtНgОJмТ─П+Т│wtwtwt НаНgОIHwtwtwtТ═wtwtwtwtwtwtТ║ wtНgОGцТ wtНgОD≈Т▀Т▄wtП2wtwtНgОCТ©П:Тюwtwt НgОA█ТП*НаН]О?5Т░П2wtП'Н]О=╟ТwtwtП"Н]О:└Т┐П"wt Т└wtН]О8ЪТ wtПGТ⌡Н]О7zТ▀wtТ▄П/wtНаН]О5УТНgО1УyНgО.иtТОП+wtП$ТП НgО-DТгП5wtwtТхНgО+©ТїП7xtТ╗wtНаНgО*:Т═П#wtП#Т║НgО(╣Т°П)Т²wtwtНgО'0wtТwtП%wtНgО ╣xНgО┴tТ▓Т⌠ПNНаНgОТ Т⌡ПGНgОТДТЕП?НgОЗТ╗Т╘П@НgОuТЁП5ТЄП'НgОПТ·ПMТ÷НаНgОkТНgО?Т╙wtП&Т╚ wtНgО╨Т┴Т┼П'wtwtНgО5Т√yП?tТ≈НgО╟Т┴П5wtwtТ┼НаНgО+Т┐wtП'wtюа Д=Г]'яDRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM9a function to reset its request signal.In general, io works in the following way (see figure 3). Each device has a request signal whichindicates that the device wants service from the processor. This signal is the output of a flip-flopwhich is clocked by the processor clock; thus any necessary synchronization is done before this flip-flop (figure 3a). During the second cycle of the click preceding a potential click for the device, its5request signal is examined. If it is true, the device's task runs during the next click, which thusbecomes a service click for the device (figure 3b).Normally, the task will execute a function which clears the request signal during the service click,and therefore the task will not run again until the device sets request again. Care must be taken toavoid a race in which the request is set again before it is cleared; this would cause one request to be10lost. Alternatively, the task may refrain from clearing the request, in which case every potentialclick for that task will be a service click. Among other things, this provides a simple way for a taskto time short intervals, by simply leaving its request set, counting clicks, and multiplying by thefrequency of potential clicks for the task in the schedule. Also, properly designed synchronousdevices, such as the display, may operate in this mode. It would be possible to operate an15asynchronous device like the ethernet in this mode, and test in each click to determine whether datashould be transferred; this would result in some wasted cycles.6.1 Latency and bandwidthIf a device request is latched at time 0, the earliest time that the first microinstruction executed bythe task serving that device can complete is 300 (ns, or .3 us). The latest time is 300d+500, where20d is the maximum number of clicks between successive potential clicks for that task (2 for displayand disk, 4 for ethernet); the delays are illustrated in figure 3b. Of course, if the request is notremoved, then the maximum delay between service clicks is 300d+100; this is the time betweencompleting the last instruction of one service click and completing the first instruction of the nextone.25A device which receives service n times per round (8 clicks), and transfers b bytes in every serviceclick, can sustain a peak transfer rate rp of nb/2.4 megabytes/second, or 3.33nb megabits/second.Adequate buffering is of course required to sustain this rate. The amount of buffering requiresdepends on the amount of synchronization required between the device and the processor. Notethat we do not include any parallel-serial conversion register in the amount of buffering we count.30At one extreme, the display has n=3 and b=4, for rp=40 Mbit. This is also the actual rate r,because the display is run synchronously with the processor, and has just enough extra bufferingbeyond the minimum of b bytes to make use of every service click. At the other extreme, theethernet has r=3 Mbit, which means that n=b=1 provides enough bandwidth.The reader is invited to find flaws in the analysis which follows.35Latency considerations, however, make this inadequate with single-byte buffering. The amount ofbuffering required is given by a=(.3d+s+.5)r if the task takes or delivers a byte in its first cycle.Here s is the maximum delay between the device taking or delivering the data, and the system clockon which the request is clocked, including worst-case synchronization. If the data handling issynchronized to the clock (as is the case for the ethernet), there may still be one cycle of maximum40synchronization delay to allow for the fact that r is not synchronized to the processor clock. Thisdelay s might be negative, provided that smin+230 ns>0, (where smin is the minimum delay, andthe 230 ns is the minimum service time, 300 ns, minus the setup time for the IOIN bus, 70 ns). Forthe ethernet, which is synchronized when the wire is sampled on input, s=100, d=7 if n=1, andthis results in a=8.1 bits of buffering required. If we want to have only 8 bits, we must decrease d,45which can only be done by serving the device more than once per round. On output the ethernetoperates completely synchronously with the processor, so that s=0 and 8 bits would be enough.НЪОeЗpТНtwТjtwtwtТ└pН!иОdRtНGіОfПНО_ТП'НО[ЙТ╚П5Т╛ytНОZeТ÷Т═ПFНОXЮТ┴Т┼ПUНОW[Т⌠П7Т■П0ННОUжТ╛ПRТґНОTQТП3НОQ%Т═Т║ПEНОO═Т┬Т┴ПOНОNТ─П!Т│ПFНaНОL√Т╟Т╠П]НОKТ┤Т┬П^НОI▄ТЁП6ТЄП-НОHТ©П*ТюП6НОF┌ТэП;ТщНaНОDЩТ┐П7Т└П-НОCxТП?НО?xyНОytТІЪФa?>Г[лпDRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM10It is also necessary to ensure that an io task doesn't clear its request after a second one comes in(thus losing the second request). Assume that the clear is done in the first cycle of the service click.The interval between requests is b/r. This, rounded down to the nearest cycle, must be greater thanthe time from request to completion of first instruction, with a one cycle margin to allow forsynchronization variations. Thus floor(b/r)-1 > 3d+5. If the request flipflop is gated so that the5set overrides the clear, then equality is also safe.6.2 DiskThis section describes the disk controller design and microprogramming details. For a completeunderstanding it would be prudent to read the interface manual for the SA-4000, especially sections4 and 5.10The Shugart SA-4000 disk has a bit time of 140 ns, a byte time of 1.12 us, and 18000bytes/rotation; hence the rotation time is 20.16 ms. The parameters of the interface are b=1, d=2,n=3, r=7.14 Mbits, s=-120. The value for s is computed as follows. The minimumsynchronization delay is one cycle or 100 ns. The microcode takes or delivers data on the secondcycle of the service click; and we include this extra delay into s for convenience. If the request15raised on the disk bit clock is raised three bit times before the data is available, we get smin=200-3*140=-220, which is legal. The maximum synchronization time is two cycles or 200 ns, so s=300-420=-120. This yields a=(.6-.12+.5)7.14=1.02*7.14=6.96, so we get by with one byte ofbuffering.For request clearing, we have 11-1 >= 3*2+5, or 11>=11. This means that the request might be20set and cleared on the same clock.The intention is to format the disk into sectors, each containing three records: a 2-word header, a10-word label, and a 256-word data record. Each record also has a preamble, described below, anda 1-word checksum appended to it. Possible operations on a sector are to read any number ofcomplete records, and then write the remainder of the sector. There are 30 sectors on one track,25and hence 600 bytes per sector. The information above (not counting the preambles) amounts to542 bytes, which leaves 58 bytes, or 19 in each record, for the preamble. This amount of spacemust accommodate the 8 us acquisition time of the disk's read clock circuit, as well as all the timerequired for synchronization with the microcode.Each interaction with the microcode can occur as little as 400 ns after the disk-related hardware30generates the signal, or as much as 1300 ns. Thus there is a disk-to-microcode synchronization errorof almost one byte time. The preamble must be extended by twice this time, since the error is inone direction if reading is fast and writing slow, and in the other direction if the other way around.The preamble must have the property that the disk has 8 us between the arrival of Read Gate andthe occurrence of read data. The idea is to write 8 us worth of zeros, followed by a 1 bit, followed35immediately by data. The interface looks for the 1 bit in the serial stream coming from the disk,and thus synchronizes itself to the data stream. So the needed length of preamble is 8+2=10bytes, all zero except for a 1 at the end of the last byte; if time is measured in service clicks, therewill also be some breakage error. Since there is room for 19 bytes, we are in good shape. Detailsof the timing are presented below.40The disk controller interprets five functions:KData_ takes a byte from IOOUT for transmission to the disk. _KData reads a byte from the diskonto IOIN.8-15. These must be done within 11 cycles of the request, which is just the maximumdelay with d=2. rKReq resets the disk request, unless it is being set in the same cycle.45ЪН_ОeЗpТНtwТjtwtwtТ└pН#)ОdRtНЩОfПНgО_ТёПNТєНgО]▒Т┐П;Т└П.НgО\Т│П!ytytТ┌П(НgОZ┤ТмТнПVНgОYТ≥П(ytytytТ НtНgОW}ТП4НgОS}yНgОPQtТ╣ТІП@НgОNлТ┴Т┼ПJНgОMGТНаНgОJТПTНgОH√Т├Т┤ПEytytНgОGytТytyt Т ytП%НgОE▄Т÷П"Т═П9yНgОDtТґПAytТўНаНgОB┌Т≈ПTТ≤yОAУwОB┌tНgО@╦Т┐Т└ПFytНgО?3ТЭytП6ТЩНgО=ў НgО:┌Т─ПLТ│НаНgО8ЩТП"НgО5яТёТєytП*ytНgО4LТ▓ytytП!ytНgО2гТ╨ytТ╩ПKНgО1BТєПaНаНgО/ҐТ║Т╒ПQНgО.8Т╛ПVТґНgО,ЁТ∙ПLТ√НgО+.ТП0НgО(ТЄПGТ╣НаНgО&}Т┌П;Т┐П*НgО$ЬТ≈Т≤ПOНgО#sТ┼Т▀ПVНgО GТ▐ПVТ░НgОбТ▀П@Т▄П%НаНgО=Т²П-Т·П5НgО╦Т╧П(Т╨П4НgО3Т░ПbТ▒НgОўТ▓П1Т⌠П2НgО)ТП"НаНgОЩП.НgОяxtТ▌wtТ▐xtНgОLТїwtПMТ╗НgО гТ ytНgО ⌡xtПCНаЪра T>Г]ЇєDRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM11KCtl_ writes the disk control register from IOOUT. The bits of this register are sent directly to thedisk (except for CanLoadKSR, which is internal to the controller, and Write Gate, which is gatedwith OKtoRun). The bits are interpreted as follows:04Kinit: used for read initialization, as described below.05KReset': when reset, the disk is reset, and will neither generate nor remember5requests.06WantKByteReq: when set, allows a request to occur every 8 disk bit clock times.When a transfer is not in progress, this signal should normally be reset.07Direction Select: determines the direction of head motion on a seek. 1 is "out" oraway from the center of the disk.1008Step: instructs the disk to move the heads one track in the direction specified byDirection Select. The 0-1 transition is the active one. Direction Select must notbe changed in the same click. Step must spend at least 2 cycles in each state,which means that only one step/click is possible.09-11Head Select: selects one of the 8 possible heads.1512Fault Clea: Any write fault is reset on the 1-0 transition of this signal.13Read Gate: turns on the phase locked loop in the disk which controls datarecovery. It should be turned on only in the preamble of a disk record. There isgood data and clock 8 us after Read Gate is set.14Write Gate: turns on the write amplifier in the disk. This signal is gated with an20internal signal called OKtoRun, which ensures that the disk will not see WriteGate during power-up.15CanLoadKSR: allows the shift register in the disk controller which does serial-parallel conversion to be loaded from the output buffer. This signal must be 0during reading and 1 during writing. It also participates in read initialization, as25described below._KStatus reads the disk status information onto IOIN. This information is frozen whenever KReq isset, to ensure that it will not change between the occurrence of an interesting event and the time itis read by the task. Hence it is not possible to leave KReq set and monitor the status for someinteresting event.3008Track00: set when the disk is on track 0. This information is used to get themicrocode and the disk to agree about where the heads are.09Write Fault: set when the disk has decided that an improper attempt has beenmade to write. The disk latches this condition until it is reset by the Fault Clearcontrol signal.3510Seek Complete: cleared immediately after a Step, and set when the headcompletes stepping. After Seek Complete sets, it is still necessary to wait 20 msfor the head to settle before reading or writing.11Sector Mark: true for 1.1 us at the beginning of each sector (sector boundaries areset by jumpers in the disk). This signal causes a request, and hence the40occurrence of Sector Mark is frozen in KSTATUS until the request is cleared. If therequest is cleared within 1.1 us, it may be set again, since the disk's Secotr Markmay not have gone away.12Index Mark: true synchronously with Sector Mark once per rotation of the disk.13Ready: normally true continuously within 3 minutes after power up. If Ready45disappears, there will be a request, and hence the state of Ready will be frozen inKSTATUS until the request is cleared.НЪОeЗpТНtwТjtwtwtТ└pН!иОdRtНFСОfПНО_xtТ░П'wtТ▒П/НО]▒Т═П%Т║П;НО\ТП4НЩОYЄН╟П8НЩОW\Н╟ТЎП+Т©П#НН╟ОUвНЩОSН╟Т ПHТ⌡Н╟ОQЗТПIНЩОO╒Н╟Т└ПSН╟ОNТП!НaНЩОKеН╟Т≥П.Т П$Н╟ОJ@Т°П(Т²П+Н╟ОH╩ТЁ ТЄПEН╟ОG6ТП1НЩОDчН╟П1НaНЩОB├Н╟ПJНЩО@.Н╟ТЦП;ТД Н╟О>╘Т▀Т▄П;Н╟О=$ТП0НЩО:лН╟Т░ПSНaН╟О9GТҐП;ТЎН╟О7бТНЩО5jН╟ТҐПGТЎН╟О3ЕТ╚П)Т╛П&Н╟О2`Т²П%Т·П0НaН╟О0шТНО-╞xtТ─П(wtП&Т│НО,*Т█ Т▌ПWНО*╔ТїТ╗ytП;НО) ТНaНЩО&хН╟Т╨П/Т╩Н╟О%CТП:НЩО"КН╟Т╣П*ТІП"Н╟О!fТ■ПAТ∙Н╟ОАТНaНЩО┴Н╟ТП=ТН╟ОТ╒ПOТёН╟ОТП1НЩО'Н╟Т┤Т┬П>Н╟О╒ТШП)ТЭНaН╟ОТ┬П#Т┴wtП%Н╟О≤Т≥ПGТ Н╟ОТНЩО╩Н╟Т╔ПNНЩО cН╟Т╦ПLНaН╟ОчТ█П2Т▌П!Н╟О YwtТЪьa =Г]Ы√DRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM12There are three conditions which cause a disk request: next byte (only if WantKByteReq is set), notReady, and Sector Mark. The request will appear between 100 ns and 200 ns after the conditionbecomes true. If KReset' is reset (0), there will be no disk requests.The proper sequence for writing a record on the disk with m+1 bytes of preamble and n bytes ofdata after a sector mark is as follows:5We assume that the idle state of the interface is with 0 in KDATA and CanLoadKSR set.Turn on Write Gate and WankKByteReq, and block. The delay is .4-1.3 us from thesector mark. The next request will be caused by a byte clock.At the next service click, delay from sector mark is another .4-2.4 us, or a total of .8-3.7 us.FOR i IN [1..m-1] DO KDATA_0; Block ENDLOOP. Delay is 1.12m.10Now m zero bytes have been written (actually the mth one is just being written). DoKDATA_1; this writes the last byte of preamble. Block.FOR i IN [1..n] DO KDATA_Data[i]; Block ENDLOOPKDATA_ChecksumHi; Block; KDATA_CheckSumLo; Block; KDATA_0.The time available for the preamble is 19 byte times. Taking off 1 for safety, and 415(3.7/1.12=3.30) for the initial delay results in m=13. Hence the 1 bit at the end of the preambleis 1.12*14-.14=15.54 us from the beginning of the preamble, or 16.34-19.24 from the sector mark.The proper sequence for reading a record from the disk after a sector mark is as follows:Block (delays 1.0-2.2 us from the request). This ensures that the heads are into the regionwhere 0's have been written. In the first cycle of the third click, turn on Read Gate.20FOR i IN [1..11] DO Block ENDLOOP (delays 8.7-9.0 us).Now the disk has acquired its read clock and is supplying good data, which is zeros. Turnon KInit, CanLoadKSR and WankKByteReq, and block. The next request will becaused by a byte clock. There will be a 0 in the shift register. Delays .4-2.2 us.Now the counter in the controller is locked up at 9, and we are 10.1-13.4 us from the sector25mark. Turn off KInit and CanLoadKSR, and block. The controller is now waitingfor the 1 bit at the end of the preamble, and the next request will occur when thefirst data byte is ready to be read with _KDATA.FOR i IN [1..n] DO Data[i]_KDATA; Block ENDLOOPChecksumHi_KDATA; Block; CheckSumLo_KDATA; Set CanLoadKSR.30Slight variations are appropriate for reading and writing after a previously read or written sector.6.3 EthernetThis section to be written by Mike Schroeder.6.4 DisplayUnlike the other io devices on the machine, the display gets its timing entirely from the execution35of microinstructions. The interface contains a 32-bit main shift register DMAIN which can be loadedfrom MEMIN.0-31, an auxiliary 16-bit shift register DAUX which holds the bits which may remain tobe sent out when new memory data arrives, a counter which controls switching between the mainand auxiliary registers, some fast logic convert the 20 MHz rate at which the shift registers operateto the 40 MHz at which the display itself operates, and a control register which supplies horizontal40and vertical sync signals, and synchronizes the shift registers to the microcode as described below.The display needs 4 bits/cycle, or 12 bits/click. Hence in 3 clicks it needs 36 bits, which is 4 morethan the memory can supply. This deficiency is remedied by servicing the display at intervals of 2,3 and 3 clicks within a round of 8 clicks; thus the service pattern is A x B x x C x x, where thecapital letters name the display service clicks. DMAIN shifts out its last bit at the end of the third45Н_ОeЗpТНtwТjtwtwtТ└pН#)ОdRtНЩОfПНgО_Т┘ПcНgО]▒Т÷ПJТ═НgО\ТПGНgОXЮТ∙П:ytТ√ytНgОW[ТП'НtН]ОUжТїП8Т╗wtНПОTQТ┴П.wt Т┼НПОRлТП>Н]ОQGТ┼ПLТ▀Н]ОOбwtТytwtytwtwtwtytНаН]ОN=ТяytП+ТрytП!НПОL╦wtТП1Н]ОK3wtytwtytwtwtytytwН]ОIўty twty twtНgОF┌ТПGТ НаНgОDЩТ⌠П%Т■ytП0НgОCxТ≥Т ПLНgО@LТЯПPТРН]О>гТ⌠Т■ПOНПО=BТ▐ПQТ░НаН]О;ҐwtТytwtwtwtН]О:8Т▐П"Т░П8НПО8ЁТўП0wtТ╞НПО7.ТІТЇПKН]О5╘Т┐Т└ПJНаНПО4$Т═П@Т║НПО2÷Т╗П)Т╘П)НПО1ТП)wtН]О/∙wtytwtytwtytytwtwН]О.y wty wtНаНgО*ДТ╙Т╚ПSНgО&ДyТНgО#╦tП-НgО╦y НgО▄tТ≈Т≤ПSНаНgОТ├П6Т┤wtНgО┌Т█wtП*wtТ▌ НgОЩТ═П9Т║П$НgОxТ⌠П(Т■П=НgОСТ▓ПAТ⌠П#НаНgОnТ═Т║ПXНgОBТ┼ПaТ▀НgОҐТ┼Т▀ПQНgО 8Т÷Т═ПAНgОЁТ⌡П2wt Т°П%На,аl=Г\÷гDRAFT WILDFLOWER REFERENCE MANUAL DRAFTAugust 18, 1978 4:44 PM13cycle of A (A.3), and is loaded from MEMIN on that clock. At B.3 24 bits have been consumed, and8 remain. The 8 bits are saved in DAUX, and 32 new bits are loaded into DMAIN, so that 40 bits arenow buffered up. By C.3 36 bits have been consumed, 8 from DAUX and 28 from DMAIN. The 4remaining bits are again saved in DAUX, and 32 new bits again arrive. By the next A.3, all 36 bitshave been consumed, and we are back where we started.5To deliver a total of 1024 bits requires 32 clicks, or 102/3 rounds. Things are arranged so that the1st data click is a B click, and the 32nd data click is a C click. On the next A click the task setshorizontal blanking into the control register. During the next B, C, A, B, C and A clicks the taskidles (or samples the keyboard, or whatever). This 5.0 us is for horizontal retrace. On the final Aclick, the task fetches 0. On the following B click the task fetches the first doubleword of data, and10clears horizontal blanking. The 8 zeros in DAUX are supplied as data, followed by the first 32 bitsof real data in DMAIN, and we go around the loop again. Thus a scan line is a total of 13 roundslong.The display has a request signal which is set at the end of the first cycle of the first click of everynth round (i.e. every 2.4n us), where n is part of the display control register. Normally the display15task doesn't clear its request signal. During vertical retrace, however, and whenever the display ispainting scan lines not covered by bitmap, the task does clear the request, and thus takes only oneclick in 8n, rather than 3n clicks.. It is also possible to have blank left and right borders inmultiples of 3*32=96 bits, or about 1 inch, and take only 1 click/round instead of 3, using thismechanism with n=1. 20The display is controlled by two functions:Display_ loads DMAIN from MEMIN and simultaneously loads an assortment of control informationfrom IOOUT, as follows:08-10the request setting interval n described above.11-124 times the number of bits to be taken from DAUX before switching to DMAIN.25This should be 0 on an A click, 2 on a B click, and 1 on a C click.13if 1, the display is turned off (black).14if 1, horizontal blanking is turned on.15if 1, vertical blanking is turned on.rDReq clears the display request signal, which is set at the start of every nth round, as described30above.6.5 Microcomputer busNothing has been decided yet about how this will work.7. Debugging hardwarexxx35ЪНЪОeЗpТНtwТjtwtwtТ└pН!иОdRtНFСОfПНО_Т┌П$Т┐wtП7НО]▒Т│П#wtП"wtТ┌НО\Т⌠ПТ■П%НОAўТл ytytТмП(НО@)ТўП[Т╞НО>єТytНaНО;xП+НО8LxtТ≈wtwtТ≤П"НО6гТwtНЩО4oН╟ytНЩО2Н╟ТўП&Т╞wtwtНaН╟О0▓ТПCНЩО.:Н╟П(НЩО+БН╟П'НЩО)┼Н╟П%НО&^xtТїПGytНaНО$ыНО ыyТНОґtП6НО2xНОtНaЪ Дa©=ГTLJQR>>>>>>>>>ALUAA00A0BcombinationsF16lsh 1rsh 1lsh 1rsh 1>>>>>>>>>NopQ_FB_FB_F & Y_AB_F lsh 1B_F rsh 1B,,Q_F,,Q lsh 1B,,Q_F,,Q rsh 1ALUIllegalMUXLOADshifts into cyclesH>>>ZeroZero>>>>US16SC(small const)>>>>IbIoInYall othersare legalIoOut(B)(A)WX(STKP)Y lcy 8=F1Figure 1: Arithmetic data pathsGHXG+HG-HH-GGvHG&HG'&HG xor HG' xor HMemInMarMem-OutStkp>StkpHG>RH160-1912-158-158-15All paths are 16 bits (0-15) except as noted12-150-312-158-15An F1 makes8-1112-15>>IBHIBL32/task>(F1,Cin)Н%:ОKЄЧy$Н хОJ Ч$yН хОJ Ч∙$Н%:ОJ-Ч$UН хОM_Чr$Н#▐ОHМЧ$$Н"sОKьПН хОGяЧr$Н хОBBЧ∙$Н хОBBЧ$╡Н%:ОBfЧ$▌Н%:ОF&ЧU$Н%:ОC_ЧU$Н(░ОBТЧ$ rН&ЕО?{Ч╚$Н#▐О<ЄЧ$$Н"sОDФПН(░О7вЧ$VН's|ОGТПН'sОE-ПН'sОBfПН'sО?·ПН'sО;╩ПН'sО8ТПН'sО6,ПН-░ОJ ЧV$Н5ЕО:·Ч$▐Н-░О:{Чy$Н-░О:{Ч$╡Н(░О<ЄЧ$Н(░ОGяЧ$Н,sОDПН,sО8ТПН0WpОBfПН&ЕtОYъПН&ЕОXцПН&ЕОWіПН)ОYъПН)ОXцПН)ОWіПН)ОV┼ПН%:О\їПН&WОZЭЧД$Н(ОVfЧ$Н5ЕОBпЧД$Н8╛pОC┌ПН>иО?Ч$rН",tОCМПН9иОBпЧ$ yНОP&Ч$о$НОE Ч╚$Н:ОBТЧ$rН&ЕОKЄЧ$yНхОO ЧA$Н:ОI÷Ч$rНОFЄЧ$НОC┌Ч$хНОC_Ч$НVОFШПНVОCіПНхОKьЧ$UНхОKЄЧr$НхОM_Чr$НОJ Ч$НVОMіПНVОKШПН:ОKЄЧ▌$Н|ОI÷ПНОGТПНОFIПНОBТПНО?·ПН=ґО?ПН=ґОиО@ Ч9$НFО>^Ч$yНFО>^Ч∙$НJtО>┌Ч$UНFОAЄЧr$НFО9^Ч$yНFО9^Ч∙$НJtО9┌Ч$UНFО<ЄЧr$НFО4^Ч$yНFО4^Ч∙$НJtО4┌Ч$UНFО7ЄЧr$НGґpО?·ПНC;О1≈Чг$НC;О6 Чг$НC;О;≈Чг$НDФ|О┌ПН :О:·ПНVtО4╔ПНUpОE╩ПН▐tО;PПНхpО&·ПН&ЕtО[CПН)О[CПН&ЕОV┼ПН0WО]цПН0WО\їПН0WО[┼ПН0WОYQПН0WОX5ПН0WОWПН0WОUЭПН0WОTъПНUpОBТПНC;О/┌Ч$╚НО/^Ч4^$НО/^Ч$ НО8BЧ9$НО4^Ч9$НGО:·ПНF░О6╩ПНF░О5ПНC;О/^Чг$НF░О0ПНО:{Ч$√НДОH_Ч@$Н Д|ОD÷ПНpОGТПН.ОGfПН.ОПНДО;PПНхО$┬П,НVО;PПН&WО6чПНsО6чПН&ЕОAЄЧr$Н+WО9┌Ч$VН+WО9^Чr$Н&ЕО?·Ч$ДНK▒О1PПН▐xОSцПН ▐О?{Чr$Н ▐О=пЧ$yН ▐ОA&Чr$НtО?бПН ▐ОAmПН Д|О;╩ПН ДО=fПНVtО?4ПНVО@ъПН%:О6≈Чх$НAО6≈Ч$yНхО6чПН|ОAIПНVtО8┴ПАДU$AKJ<ЄjP1aP2aP3aP2bP1bP3bP2cP1cP1dALPHAALPHAALPHAALPHAALPHABETABETAIbPtrRunning1234123012345123012NextMacroNextMacro12345678910111213141516171819NextMacroNextMacroNextMacroNextMacroNextMacro_IB_IB_IB_IB_IB_IB_IBNextMacro; Refil + AlwaysNextMacroNextMacro; Refil + AlwaysNextMacroNextMacro; Refil + AlwaysNextMacroNextMacro; RefillP1aP2aP2aP3aP3aP3aP2bP2bP1bP3bP3bP3bP2c--P1cP1dP2dP2dLine--ALPHAP3aP2aP1aALPHAP3aP2aP1aP1aP2aP3aALPHAALPHAP3aP2aP1aBETAALPHAALPHAP2bP2bALPHAALPHABETABETAALPHAALPHAP2bBETAALPHAP3bP1bP1bP3bALPHABETABETAALPHAP3bP1bP1bP3bALPHABETABETAALPHAP3bP1bP1bP3bALPHABETAALPHAP1dP1cP2cP2cP1cP1dALPHAALPHAP1dP1cP2cP2dP2dP2dALPHAP2cP1dIB1IB2IB3IB4IB0IB0IB4IB3IB2IB1IB1IB2IB3IB4IB4IB3IB2IB1IB1Mesa instruction byte streamHeavy lines mark doubleword boundariesFigure 2: Operation of the instruction bufferThe heavy box encloses the byte which is on IBНхО\┐ПН╚О\┐ПНsО\┐ПН$О\┐ПН+ЕО\┐ПН/иО\┐ПН;tО\┐ПНC;О\┐ПНGО\┐ПН▐tО\_ПНVО\_ПН(О\_ПН3╛О\_ПН?WО\_ПН :О\_ПН7░О\_ПНUpОY.ПН9ОY.ПНrОVУПНrОS÷ПНrОPJПНrОLТПНrОI÷ПНrОFIПНrОBТПНrО?·ПНrОПНUО4ПНUО0бПНUО&аПНUОKmП"НUОAmП"НUО#lП"НUО-lПНVpОS÷ПНVОPJПНVОLТПНVОI÷ПНVОFIПНVОBТПНVО?·ПНVОиО[УЧ$9НBґО[УЧ$9НF░О[УЧ$9НДОVfЧ$9НОVfЧ$9НОVfЧ$9НхОVЧG─Н9ОVЧG─Н▐tОVяПНspОVУПН╚ОVУПНхОVУПН9ОXXЧ▐GН9ОVЧ▐GН ▐О[ўЧEtGНNXО[УЧ$9Н9ОUЭЧkєН9ОUЭЧNkНОVfЧk9Н9ОX5ЧДkН9ОUЧ▐GН9ОRйЧ▐GНДОSЧ$9НОSЧ$9НОSЧ$9НхОRйЧG─Н9ОRйЧG─Н▐tОS|ПНspОS÷ПН╚ОS÷ПНхОS÷ПНхОPJПН╚ОPJПНsОPJПН▐tОP&ПН9ОOtЧG─НхОOtЧG─НОO╩Ч$9НОO╩Ч$9НДОO╩Ч$9Н9ОOtЧ▐GН9ОQґЧ▐GН9ОNXЧ▐GН9ОLЧ▐GНДОLfЧ$9НОLfЧ$9НОLfЧ$9НхОLЧG─Н9ОLЧG─Н▐ОLяПНspОLТПН╚ОLТПНхОLТПН'sОIЧ$9Н#▐ОIЧ$9Н╛ОIЧ$9Н+WОHиЧG─НхОHиЧG─Н :tОI{ПН(ОI{ПНVОI{ПН$pОI÷ПНхОKЧ▐GНхОHиЧ▐GНхОEtЧ▐GНхОGґЧ▐GН$ОFIПНVtОF&ПН(ОF&ПН :ОF&ПНхОEtЧG─Н+WОEtЧG─Н╛ОE╩Ч$9Н#▐ОE╩Ч$9Н'sОE╩Ч$9Н'sОBfЧ$9Н#▐ОBfЧ$9Н╛ОBfЧ$9Н+WОBЧG─НхОBЧG─Н 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