-- Lark8274.txt
-- L. Stewart July 5, 1982 11:03 AM
8274 is at port 9x
Port Read Write
-------------------------------------
90 Ch. A Data Ch. A Data
92 Ch. A Status Ch. A Command
91 Ch. B Data Ch. B Data
93 Ch. B Status Ch. B Command
There are 8 write registers and 3 read registers per channel.
There is a pointer register.
On reset, the pointer points at WR0, where one can set
the pointer. The NEXT read or write accesses the selected
register, after which the pointer is reset.
See Intel Component Data Book page 8-196 ff for details.
Most of the registers are independent, but the two WR2s
are shared as are the RR2s.
WR0: channel commands and register pointer
command 00 - 07 set register pointer
command 10 reset External status interrupts
command 18 reset channel
command 28 reset TXInt pending (not understood)
command 38 end of interrupt
command F0 reset all error signals
WR1:
1E External status interrupt disabled, Tx and Rx interrupts
enabled, status affects vector, no Ready line.
Alternate:
00 No interrupts
WR2:
Channel A
04 Rx interrupts higher priority than Tx. Interrupts
enabled for both channels.
Channel B
00 Base of interrupt vectors
WR3:
C0 8 bit mode
C1 8 bit mode, Rx enabled
WR4:
4C 16x clock, 2 stop bits, no parity
WR5:
60 8 bit mode (Tx)
68 8 bit mode, Tx enable
WR6: 00 (sync address)
WR7: 00 (more sync address)
RR0:
Bit Meaning
---------------
7 Break/Abort
6 Tx Underrun
5 CTS
4 Sync/Hunt
3 CD
2 Tx Buffer empty
1 Interrupt pending (Ch A only)
0 Rx Char Available
RR1:
Bit Meaning
---------------
7 SDLC stuff
6 Framing Error
5 Rx Overrun
4 Parity error
3 SDLC stuff
2 SDLC stuff
1 SDLC stuff
0 Done
RR2: Channel B only
Channel vectors:
----------------
B A
0 4 Tx buffer empty
1 5 Ext/Status change
2 6 Rx char available
3 7 Special Rx condition
Test sequences
Reset both channels
O92,18,F0
O93,18,F0
Set up both channels, but do not enable
O92,01,00,02,04,03,C0,04,CC,05,60,06,00,07,00
O93,01,00,02,04,03,C0,04,CC,05,60,06,00,07,00
Enable Tx, Rx, channel A
O92,03,C1,05,68
Enable Tx, Rx, channel B
O93,03,C1,05,68
More on baud rates and required input frequencies
Baud 16x 32x 64x
--------------------------------------
300 4800 9600 19200
600 9600 19200 38400
1200 19200 38400 76800
2400 38400 76800 153600
4800 76800 153600 307200
9600 153600 307200 614400
19200 307200 614400 1228800
9513 capabilities
Starting from an input clock of 1.536 MHz.
The prescaler can divide by powers of 16 up to 64K
or by powers of 10 up to 10000
The FOUT scaler can divide by any integer up to 16
Interesting MM register values
8000 = BCD scaler
0000 = Binary scaler
4000 = disable data pointer
0000 = enable data pointer
2000 = 16 bit bus
0000 = 8 bit bus
1000 = FOUT off
0000 = FOUT on
0000 = /16
0100 = /1
0200 = /2
...
0F00 = /15
0000 = FOUT from Crystal input
0010 = FOUT from SRC 1
...
0050 = FOUT from SRC 5
0060 = FOUT from Gate 1
...
00A0 = FOUT from Gate 5
00B0 = FOUT from F1
00C0 = FOUT from F2 (one scaler stage)
...
00F0 = FOUT from F5
0008 = comparator 2 enabled
0000 = comparator 2 disabled
0004 = comparator 1 enabled
0000 = comparator 1 disabled
0000 = No time-of-day
0001 = TOD /5 input
0002 = TOD /6 input
0003 = TOD /10 input
WR4 values for 8274
00 = X1 clock
40 = X16 clock
80 = X32 clock
C0 = X64 clock
sync modes
00 = 8 bit sync char
10 = 16 bit sync char
20 = sdlc/hdlc
30 = external sync detection
modes
00 = synchronous
04 = 1 stop bit
08 = 1.5 stop bits
0C = 2 stop bits
00 = odd parity
02 = even parity
00 = no parity
01 = parity enabled
Control values for WR4
/16 4C
/32 8C
/64 CC
Next table shows MM register values and required 8274 division ratios
(8274 WR 4 values) 4C 8C CC
FOUT MM /16 /32 /64
307200 8500 19200 9600 4800
153600 8A00 9600 4800 2400
76800 82C0 4800 2400 1200
38400 84C0 2400 1200 600
19200 88C0 1200 600 300
9600 0AC0 600 300 150
use of Mode J (Variable duty cycle) for creating odd division ratios