Lark Manual
To    	Voice Project		Date	January 3, 1984
From	L. Stewart		Location	PARC
Subject	Lark Manual		Organization	CSL
XEROX
Release as	/Indigo/Voice/Documentation/LarkManual.tioga
Came from	/Indigo/Voice/Documentation/LarkManual.tioga
Last edited	by Stewart.pa, February 8, 1984 2:45 pm
Abstract	This is not a well organized document, but if you read through it, thus resolving all the forward references, you will be reasonable well informed. Don't forget to print a copy of the schematics.
Main Processor
The main processor is on pages 1 through 8.
The main CPU is an Intel 8088-2 (8 MHz vesion), running at 7.843 MHz, or one third the system crystal frequency of 23.53 MHz.  The main CPU has 8 K bytes of private EPROM and access to 56 K bytes of RAM which is shared with the slave processor and other devices.
The main CPU controls most of the IO devices.
Address Space
Memory Address Space
Main CPU address bits 16 through 19 are not used, so that the CPU addresses 64K bytes which repeat throughout the 1 Megabyte 8088 address space.  The address space from E000 to FFFF is occupied by the 8 K byte main EPROM (2764).  The address space from 0 to DFFF is occupied by the main (shared) memory system, which is composed of eight 64K dynamic rams.
IO Address Space
Main CPU IO devices occupy IO address space between 0 and 7F.  Device chip select signals are generated by the LS138 at location C7.  This decoder is enabled during non-interrupt IO cycles.  (The LS078 at E8 is needed because PIO floats high during 8088 interrupt acknowledge cycles.)
The address decoding is clear from the wiring of the LS138, but the reader should note that the separate address bits for accessing internal registers of some IO devices are wired in a non-standard way.
Right-side-up devices
The Ethernet controller (SLC) and DMA controller (8237) have internal registers selected as their respective documentation indicates.  These devices both generate and receive addresses and interpret the address bus as a bidirectional bus.  Because of the strange word IO references on the 8088, word IO references cannot be used with these devices.
Up-side-down devices
The 8274, 2001, 9513, 8259, and both 8255s have isolated pins for addressing internal registers.  These pins are generally wired to BAD01' and BAD02', rather than to the more conventional LA00 and LA01.  The chips are driven by buffered (and inverted) address bits in order to reduce the length and loading of the LA (latched address) bus.  The chips are driven by bits 1 and 2 rather than 0 and 1 in order to permit the use of 8088 word IO references.  The 8088 generates word IO references by doing two byte IO references to consecutive IO addresses.  Because address bit 0 is not used for the selection of internal registers, both cycles of a word IO reference will be directed to the same register.
Address Control
The main system PROM at B7 generates enable signals for the RAM, ROM, memory bus transceiver, and external bus.  Comments in the schematics describe the combinatorial nature of these signals, but the truth will be found in the Cedar program that generates the PROM contents.  See LarkPromsImpl.mesa (in LarkProms.df) and the PROM blower command files MakePCLarkMainProm.cm and MakeLarkMainProm.cm.  MakePCLarkMainProm.cm includes the address permutations for the PC board version, while MakeLarkMainProm.cm is for the stitchweld board.  
Hidden memory
The main memory system uses 64K ram chips, but only 56 K is accessable from the main CPU.  The highest 8 K bytes are accessable via DMA to either the SLC or the Encryption chip.  It should be possible to use this memory for something, such as stored waveforms (in encrypted form perhaps).  This has never been tested (February 6, 1984 4:23 pm).
Memory System
The main CPU controls the 8 K byte main EPROM, and 56 K bytes of RAM, which are shared with the slave CPU and DMA devices.
EPROM
The main EPROM, at E3, is selected by SelROM'.  SelROM' is generated by the main system control PROM at B7 when the main CPU makes a memory referecne in the range E000 to FFFF.  The EPROM socket is wired so that a 2716 or 2732 can be used, should it be desirable to use a smaller but lesss expensive chip.
RAM
The main Etherphone memory consists of eight 150 nanosecond 64K dynamic rams, shown on page 8.  Memory control is on page 6.
A memory cycle is started by the arrival of the main system control lines Rd' or Wr' or by Early-Read.  EarlyRd' is generated by the S74 at C10 in order to provide advance warning of processor or SLC reads.  The advance warning improves memory timing margins in these cases.
Memory cycle timing is provided by the 100 nanosecond delay line at H3.  RAS0 (Row Address Strobe) is generated right away, during any type of cycle.  Meanwhile, the memory address multiplexors are providing the row address to the chips.  The multiplexors are wired so that the row addresses are LA00--LA07.  This fact is important to the operation of refresh.  After 20 nanoseconds, the muliplexors switch and present the column address to the chips.  The column address is generated by LA08-LA15.
During a read, CAS (column address strobe) is generated at 40 nanoseconds, but during a write, it is delayed until 100 nanoseconds.  This is becuase the memory chips use CAS to latch the data during a write.  100 nanoseconds provides adequate setup time for the CPU (or SLC) to present the data to the memories.
After CAS is presented, memory system activity stops until the signal that started the memory cycle is removed.  When the signal is removed, RAS stops immediately.  CAS is stopped right away when the end of RAS disables the CAS timing multiplexor at H2.  After the end of RAS, the next cycle must not begin for 100 nanoseconds in order to allow time for the trailing edge of RAS to propagate through the delay line.
During a write, MWE' (Memory write enable) has the same timing as RAS.
Refresh
64 K dynamic rams require refresh in order to preserve data.  The rams come in two types, those that require that each of 128 rows be refreshed every 2 milliseconds and those that require that each of 256 rows be refreshed every 4 milliseconds.  The Lark can use either type of chip.
A refresh cycle is normally a cycles containing a RAS, but no CAS.  These cycles can be faster than full reads and use less power.  However, a read can also serve as a refresh and refreshes the entire row containing the bit read.  The Lark does memory refresh using normal read cycles.
For the discussion of how the Lark software does refresh see the discussion under Main CPU software.
External Bus
The original plans for the Etherphone included the notion of a locator.  The locator was to be a small device carried by staff members that wiould transmit their location to the network of Etherphones.  By this means, automatic forwarding to the nearest phone could be done.  Another notion was to include a TV style remote control receiver in each Etherphoine, so that ones phone could be operated by remote cotnrol.  At this writing, neither idea has been implenmented.  However, space was left in the Etherphone packaging for an additional circuit board with enough area to accomplish either task.
In order to accomodate the additional logic, an external bus interface was included on the digital board.  The external bus logic, at the top of page two, makes the main processor IO bus available off-board.  The external bus includes the bidirection eight bit data bus, address lines 1 though 4, EEnable, PDT, and the main read and write control signals.
EEnable is activated by any processor IO reference with address bit 7 high (the range from 80H to FFH).
PDT can be used off board to control the direction of a data bus transceiver.
In addition to these processor bus signals, the external bus connector includes two interrupt lines, two parallel port bits, and one RS-232 channel.
Glue (or miscellaneous)
This section describes odd bits of hardware that don't fit anywhere else.
Read and Write control signals
The LS153 at B10 is the source for the system wide control signals Rd' and Wr'.  These signals are logically generated by the main CPU, the slave CPU, the DMA controller, and the SLC at various times.  Let us consider each of these sources.
Main CPU
When the main CPU is generating references, either memoryu or IO, GSlaveDAck' will be high and ProcOrSLC' (Processor or SLC) will be low.  The CPU drives PRd' and PWr' (these signals are tri-state) and control multiplexor switches PRd' to Rd' and PWr' to Wr'.  Memories are connected to Rd' and Wr', so they work, and all IO devices are connected either to Rd' and Wr' or to PRd' and PWr', so they work.
SLC
When the SLC is acting as a slave, it listens to PRd' and PWr', so only the main CPU can reference the SLC.  When the SLC is acting as a master, it never references other IO devices, only memory.  When the SLC is master, GSlaveDAck' will be high and ProcOrSLC' will be low, the same as the Main CPU case. The SLC drives PRd' and PWr', just as did the main CPU.
Slave CPU
The slave CPU is never the target of references by other bus masters, but it occasionally requests control of the main busses and makes references as a master.  When this happens, GSlaveDAck' will be low and ProcOrSLC' will be high, causing the control multiplexor to switch SlaveRd' and SlaveWr' through to Rd' and Wr'.
DMA controller
Like the SLC, the 8237 DMA controller sometimes acts as a slave IO device and sometimes as a bus master.  The 8237 has two sets of control lines, IOR' and IOW', and MEMR' and MEMW'.  IOR' and IOW' are connected (wire or) to PRd' and PWr'.  When the DMA controller is a slave, the main CPU is able to reference the 8237 via IOR' and IOW'.  MEMR' and MEMW' are connected to the control multiplexor.  When the 8237 is  slave, these signals are not used.
What happens when the 8237 is a master?  The DMA controller uses both sets of control lines in this case.  The only device which operates together with the DMA controller (as master) is the 2001 encryption chip.  The control lines of this IO device are connected to PRd' and PWr'.  Consider the case that the DMA controller is controlling a write from the 2001 to memory.  Both GSlaveDAck' and ProcOrSLC' will be high, so the multiplexor will connect MEMR' (DMRd') and MEMW' (DMWr') through to Rd' and Wr'.  The DMA controller will assert IOR', which will drive PRd' and hence the 2001, while at the same time, the DMA controller will assert MEMW', which will drive Wr'.  The DMA controller simultaneously asserts read to the encryption chip and write to memory, performing a direct bus transfer.  This complexity is why the encryption chip is connected to PRd' and PWr' rather than to Rd' and Wr'.
Wait states and Ready
The 8088 normally takes four clock cycles to complete a single read or write bus cycle.  All memories in the Lark are sufficiently fast to respond, and are always willing to accept a cycle.  The situation is different for IO devices.  The SLC is a very asynchronous device, it may not be able to respond to a main CPU IO reference in four cycles.  For this reason, whenever the main CPU addresses SLC device registers, the main CPU goes not-ready until the SLC responds by asserting the signal SLCReady'.
During memory references, the main CPU ready line is normally held high (SLCReady' low) by the 8T09 at F7 (see the bottom of page 2).  However, this gate is disabled by SelSLC', the main CPU's chip select line for the SLC.  When this happens, SLCReady' will be pulled high and the main CPU stopped until the SLC is able to respond.
Other IO devices are always prepared to accept a bus cycle, but are not guaranteed to be fast enough to respond in four clock cycles.  Suppose that the main CPU generates an IO reference to some device other than the SLC.  As soon as PIO goes high, SLCReady' will go high, causing the main CPU to wait.  The main CPU will have already asserted one of Rd', Wr', or IntA'.  The OR of these signals will propagate through the one cycle delay imposed by the section of the LS374 and then cause SLCReady' to go low, alooiwing the bus cycle to complete.
To summarize, memory cycles run at full speed.  Main CPU references to the SLC wait until the SLC is ready, and main CPU references to other devices have one wait state.
Warning:  The SLC will never assert ready if a non-existant internal register is referenced.  This will cause the Lark to lock up until the watchdog timer or some other event causes a hardware reset.
Address latches
There are two address latches in the Lark, one at E2, used by the main CPU and the SLC, and one at D2, used only by the DMA controller.
There are various busses in the Lark, the LA or latched address, represents the truth for addresses.  The AD (address data) bus combines addresses and data.
When the processor makes a reference, LA08 - LA15 are driven directly by the CPU chip, while the low order 8 address bits are multiplexed on the AD bus.  During the first clock cycle of a bus cycle, the address is presented along with the signal PALE (processor address latch enable).  PALE becomes NALE and then strobes the address latch at E2.  ProcOrSLC' enables this address latch onto the low half of the LA bus.  The situation is the same when the SLC makes a reference, except that PALE (which is not tristate) is isolated from NALE, and NALE is driven by the SLC.
When the DMA controller makes a reference, the situation is more confused.  The DMA controller directly drives the low half of the LA bus, and the high order address is multiplexed onto the AD bus.  The DMA controller signals AEN and ADSTB load this high address into the multiplexor at D2.  The high order address is latched rather than the low order as an interesting efficiency trick.  The notion is that DMA transfers are largely sequential, if the high order address doesn't change, the DMA controller does not take the time to reload the address latch on each cycle, and is able to run the bus faster.  This effect probably does not come into play in normal Lark operations.
Pushbuttons
There are two pushbutton debouncers in the Lark, one for the reset button and one for non-maskable interrupt.  The design calls for single pole double throw momentary pushbuttons.  The armature is grounded and the poles are connected to the set and reset inputs of flip-flops.  The idea is that even if the switch contacts bounce high enough to open a contact, they never bounce high enough to close the other contact.  The pushbuttons are external to the lark package.  The wiring is connectd to the "special" connector.  The signals ManResetNC and ManNMINC must be wired to the normally closed (NC) terminals of the respective pushbuttons and the NO signals to the normally open terminals of the respective pushbuttons.
Pullups
There are many pullups on the Lark board.  These are generally SIP packages supplying 7 or 9 pullup resistors.  MOS signals are pulled up by 10K ohm resistors and TTL signals are pulled up by 1K ohm resistors.  All the pullupsa are shown on page 7.
Clocks
There are two primary crystals in the Lark:  12.288 Mhz, from which the audio sample rate and real-time clock are driven, and 23.53 Mhz, from which the processors and Ethernet are driven.
23.53 Mhz
The 23.53 MHz crystal, at K6, is buffered to become FClock and then divided by the LS393 at F9 to become Clk2.94, Clk5.8825, and Clk11.765.
Ethernet (SLC chip)
The switch at F10 is wired to permit SLCClkIn' to be driven by either Clk5.8825 or Clk11.765.  The SLC needs an input clock at four times the Ethernet bit rate.  For 1.47 Mbps service, Clk5.8825 is selected.  For 2.94 Mbps service, Clk11.765 would be selected.
At this writing, no 2.94 Mbps SLC chips are available, so Clk5.8825 is selected.
The SLC requires differential clocks on pins 8 and 7, which are provided by the 26LS31 at K4, which produces SLCClk and SLCClk'.  These signals are pulled up by 2K ohm resistors, so that the SLC will see clocks swinging up to 5 volts, rather than just TTL high.
A useful test point is CLKO, at SLC pin 6.  This signal should be at 1/2 the frequency of SLCClk if the SLC is at all healthy.
Encryption
The WD2001 encryption chip is driven by Clk2.94.  The chip has a 3 MHz limit, and this clock is synchronized, sort of, with the CPU clock.
Processors
FClock drives the EFI (external frequency input) of the 8284 clock generator at F6.  The timing outputs of the 8284 are SysClock and PClock.
SysClock runs at 1/3 the frequency of FClock, or 7.843 MHz.  It has a duty cycle of one third, so that it is low for two cycles of FClock and high for one cycle of FClock.  FClock drives both 8088s, and serves as a general synchronizer clock in the LS374 at B8.
PClock is a square wave at 1/2 the frequency of SysClock, or 3.9215 MHz.  It is available for the 9513 timer, but is not currently used.
12.288 Mhz
The 12.288 MHz crystal, at H9, is divided by the LS393 at F9 to become ClkDB2 and ClkDB4.  These clock signals, at 3.072 MHz and 1.536 MHz, are available at the DIP switch at F10, one of them is selected to become T1Clk.  (Using a 12.288 MHz crystal, ClkDB4 is selected.  If a 6.144 MHz crystal is used, ClkDB2 would be selected.) T1Clk necessarily runs at 1.536 MHz.  The LS393 section that does the dividing may be disabled (reset) by the signal StopAudClk, which comes from the 8255 parallel port at K2.  With the present software in the 9513 timer, refresh interrupts are generated by clocks derived from this section, so be careful not to disable it for too long.
Audio Clocks
T1Clk, at 1.536 MHz represents the fundamental audio clock in the system.  A "T1" line is a TDM serial bus running 24 voice channels at 8 bits per sample and 8000 samples per second.  24 times 8 times 8000 = 1,536,000.  There are 24 times 8, or 192 bits per "frame".  Note: sometimes a 193'rd bit is added to each frame for synchronization, in which case the fundamental clock becomes 1.544 MHz.
Voice output from the digital board may be found on page 7, generated by three sections of the 26LS31 at K4.  The three signals are T1Clock, a 1.536 MHz square wave, FrameSync, a one clock wide pulse occurring every 192 clock periods, and VoiceOut, the serial data line itself.
Other voice related clocks are TSN, "Time-Slot-N" and SLCHoldOff.  TSN is an 8-clock-wide pulse which occurs during time slot 1 (the first time slot after FrameSync) and time slot 13.  It is a signal driven by T1Clock and it is high for 8 clocks and low for 88 clocks (16 KHz).  It gates the T1Clock to produce AudShClk, which drives the VoiceIn shift register, the LS299 at A4.  AudShClock  is OR'd with OSRWr to generate the clock for the VoiceOut shift register, the LS164 at A4.
SLCHoldOff is phase locked with TSN and runs at 8 KHz.  The slave processor software tried to limit its accesses to shared memory to roughly the time of time-slot-1 and immediately thereafter.  SLCHoldOff brackets that period and tries to keep the SLC from contending with the slave CPU for memory.
9513  Timer
The 9513 timer chip, at L6 is quite complicated.  Read the data book.  In general, it has 6 independently programmable timers that are extremely capable.
Channel 0: SIOClkA
Channel 0 is not completely general, it can generate square waves divided down from T1Clk.  It is used to generate SIOClkA, the baud rate clock for channel A of the 8274.  The division ratios available are sufficient to generate all standard baud rates which are multiples of 300 baud.  For 1200 baud, (standard), the output frequency is 19.2 KHz, or 16 times the baud rate.  The remaining division is accomplished inside the 8274.
Channel 1: SLCHoldOff'
Channel 1 runs in Mode L, hardware-triggered delayed pulse one-shot.  It is triggered by TSN and generates an output which is low for 46 cllocks and delayed by 192/2 -7.  It is driven by T1Clk.
Channel 2: TSN
Channel 2 runs in Mode J, a free running variable duty-cycle rate generator.  It is high for 8 clocks and low for 88.  It is driven by T1Clk.
Channel 3: FrameSync'
Channel 3 runs in Mode R, a retriggerable one-shot.  It is driven by the low edge of SLCHoldOff' and generates a one cycle wide low pulse delayed by 5 clocks.
Channel 4: SIOClkB
Channel 4 is used to generate SIOClkB, the baud rate clock for channel B of the 8274.  It operates in Mode J, a free running variable duty-cycle rate generator.  It is (default) high for 40 clocks and low for 40 clocks, generating a division ratio of 80, from 1.536 MHz, for an output of 19.2 KHz.
Channel 5: TimerInt
Channel 5 is used to generate a Non-Maskable interrupt to the main CPU.  It triggers the refresh code and is very important.  Channel 5 runs in Mode D, rate generator with no gating.  It is driven by TSN and toggles its output every 8th TSN pulse.  The result is a 1 KHz square wave.
Reset
Main CPU reset
Reset for the main 8088 is generated on page 1 by the 8284.  The 8284 is only used for clock synchronization.  The reset input, res', comes from the bootm of page 3.  res' is the OR of power-up-reset (PwrReset') and reset pulses generated by the one millisecond one-shot at e9.
Power up reset
PwrReset' is a signal which drops low as soon as VCC disappears and which returns after VCC goes high.  When VCC ristes to 5 volts, the 6.8 microfarad capacitor starts to charge through the 47K resistor.  The time constant is about 300 milliseconds, so PwrReset' stays low quite a while after VCC stabilizes.  The capacitor signal is buffered by a schmidt trigger gate (LS132) so that PwrReset' will not glitch while rising slowly though the gate threshold.
Reset pulses
The 1 millisecond pulse generator is driven by positive transitions of the OR of the one-second watch-dog-timer one-shot and the reset push-button.  Thus the watch-dog-timer will cause a reset when the time expires provided that the reset pushbutton in in the normally closed position and the reset pushbutton will cause a reset when depressed, provided that the watch-dog-timer is running.
Watch-dog-timer
The watch-dog-timer is triggered by the OR of Reset and the parallel port bit KickWDT.  The first, reset pulse, generated by power-up, triggers the watch-dog-timer for the first time.  THe EPROM software in the main CPU then generates period pulses on KickWDT to retrigger the watch-dog-timer.
If the main CPU is not healthy, then the KickWDT function may not work.  In this case, the watch-dog-timer will repetitively time out, causing reset pulses at approximately one second intervals.  To debug a problem like this, the switch at F10 switch 5, when OPEN, will disable the watch-dog-timer function.  It should normally be CLOSED for operation however.
Slave CPU
Slave processor reset is entirely controlled by the main CPU.  The main CPU uses the parallel port bit SlaveReset to control the Slave CPU.
Interrupts
The main CPU 8088 has facilities for non-maskable and maskable interrupts.
Non maskable interrupts
NMI, the non-maskable interupt, is generated by the signal PNMI.  This signal can be selected by the dip switches at F10 to come from either ManNMI', the manual push-button, or from TimerInt, a periodic signal generated by the 9513 timer chip.  Normally, TimerInt is selected.  TimerInt is normally a 1 KHz square wave generating a non-maskable interrupt once each millisecond.  This interrupt is used for memory refresh and real-time clock.  It is described in the memory section.
Maskable interrupts
The maskable interrupts are under the control of an Intel 8259A-2 interrupt controller.The 8259 is programmable.  The truth of its initialization is in LarkMonML.dsm.  Interrupts enabled or disabled en mass by the 8088, or individually by reprogramming the 8259.  Normally, 8088 interrupts are enabled.  The 8259 is programmed to provide fixed interrupt priorities.  From highest to lowest, these are Ethernet receive, Ethernet transmit, Encryption, RS-232, and Analog A though D interrupts, of which only D is used.
Whenever a DMA transfer finished (when the byte count register in the 8237 carries to 0), the 8237 generates a pulse on the DMAEOP' net.  The Encryption interrupt flipflop at B9 is set by the AND of the EOP pulse and EncWrDAck.  (EncWrDAck is used rather than EncRdDAck because EncWrDAck AND EOP occurs after the last byte of the last DES block of a cipher operation has been transfered to memory, while EncRdDAck AND EOP would occur after the last byte of the last DES block of a cipher operation had been transfered to the DES chip, but before the operation was finished.  When the Encryption interrupt flipflop is set, the 8259 generates an interrupt.  The Encryption interrupt flipflop must be cleared under program control by toggling the parallel port biot ResEncInt' low and high again before the interrupt is dismissed.
The four Analog interrupts operate in much the same way.  The signals SetAlogIntA' through SetAlogIntD' set flipflops, which in turn cause interrupts.  The programmer is responsible for attempting to clear the flipflops through ResAlogInt'.  If the interrupt source is still asserting the Set signal, the attempt to clear the corresponding flipflop will be unsucessful.
Encryption
The encryption device is a Western Digital WD2001-30.  The suffix may change, but the requirement is that the device run at 2.94 MHz or above.
The 2001 can be used both via programmed IO (which indeed is used by the IO driver to control the chip and to load keys) or by DMA.  DMA access to the 2001 is described in the DMA Control section.
The WD2001 is connected to the MD memory bus rather than to the AD main CPU bus.  The chip data setup and hold times during DMA operation are sufficiently tight that it was best to avoid the additional delay through the AD/MD bus transceiver.  Contriwise, during programmed IO operation, the bus transceiver provides additional hold time for a CPU read from the chip.
When the 2001 is operating in DMA mode, it requests 8 bytes of data (a full DES block), operates upon it, then delivers 8 bytes of data.  Ideally, these 8 byte transfers could be done in a block. without rearbitration of the bus.  Unfortunately, even if the 8237 is programmed in block mode, the 2001 drops its request for a short time between bytes.  This interval is long enough to be noticed by the 8237, so it effectively operates in single transfer mode regardless.
Ethernet
The encryption device is a Xerox SLC.
RS-232
The RS-232 device is an Intel 8274 multi-protocol serial line controller.  It is capable opf asynchronous or bit or byte synchronous operation.
The baud rates for the two channels are set by the 9513 timer chip, described elsewhere.
No modem control signals are provided, and the RS-232 cannot be operated by DMA.  If the main CPU is not doing anything else, it should be capable of driving the serial lines at 19.2 Kbps.
The 8274 is very complicated, with many modes and control registers, but the Intel documentation should be adequate.
Parallel Ports
The Lark has two Intel 8255A-2 parallel port chips, each has 24 programmable bits.
The main CPU parallel port, at K2 is used mostly for internal control functions on the Lark digital board.
Main PIO Port A, output
ResAlogInt' is normally high and is toggled low then high to attempt to clear the analog interrupt flipflops at K7.
LED' drives an open collector buffer at L1 and then goes to the analog board, where it controls the light emiting diode on the speaker box.
SlaveReset is normally low and is toggled high then low to perform a hardware reset on the slave CPU chip.
SlaveNMI is normally low and is toggled high then low.  The rising edge generates a non-maskable interrupt to the slave CPU.
KickWDT is normally low and is toggled high then low to retrigger the watchdog timer for another second.
StopAudClk is normally low and is set high to gate off all clocks generated by the 12.288 MHz crystal. This was thought to be useful to avoid possible synchronizer failures while reprogramming the timer chip, since the CPU runs on the other crystal.  Refresh will stop when StopAudClk is high, so it shouldn't be left off for long!
P1A1 is an uncommitted output which is routed to the locator connector.
ResEncInt' is normally high and is toggled low then high to clear the encryption interrupt flipflop.
Main PIO Port B, input
This eight bit port is connected to the dip switch at K1.  It was originally used for the ethernet host number.  At present bits 0..5 are unused and bits 6 and 7 are reported to the download server as bits 0 and 1 of the "boot switches."  The boot switched have no function at present but might be used for development Larks or something.
Main PIO Port C, bits 0..3, input
P1C3 is an uncommitted input wired to both the locator connector and the analog board connector.
BootMode is wired to bit 8 of the dip switch at F10.  Its postion is polled at system reset time and reflected as bit 2 of the boot switches described above.
SynTSN permits the main CPU to sense the phase of the slave CPU main loop, should careful synchronization be required.  It is not used at present.
ManNMI' reflects the position of the manual non maskable interrupt pushbutton.  It is polled by the main CPU refresh software.
Main PIO Port C, bits 4..7
These signals are at present uncommitted and may be programmed as either inputs or outputs.  They are wired to the analog board connector.
The Extra IO PIO, at L2 is entirely uncommitted on the digital board.  All port bits are routed to the analog board.  Their nominal assignments are:
Extra PIO Port A, output
Revert' is routed to the analog board via an open collector buffer.  It controls the position of the Revert relays.
GoOffHook is routed to the analog board via an open collector buffer.  It controls the position of the off-hook relay.
CodecControlData, CodecControlClock.  These two signals are used to serially clock a time-slot code into the second codec on the analog board.  The second codec normally operates in time slot 12 (based on 0 as the first time slot after FrameSync').
SenseSH, SenseRI, SenseSwitch, SenseCode.  These signals are used to discover the state of the switchhook, ring indicator, toggle switch, and DTMF decoder.
Extra PIO Port B, output
SWDataStrobe0..SWDataStrobe3.  These signals are used to clock switching data into the four MC142100 analog switch chips.  One strobe per chip.
SwAddr0..SwAddr03.  These signals are bussed in common to the four MC142100 analog switch chips.  They address one of sixteen internal crosspoints.
Extra PIO Port C, bits 0..3, output
EnableRing'  controls whether speaker volume is controlled by the user's volume control or by the trimpot on the analog board.  (A separate volume control is provided so that the user cannot inadvertantly turn off ringing.
SideTone' controls whether a sample of the signal from the handset transmitter is fed back to the handset receiver.  This is desirable to provide a "live" sound to the phone.
P2C1 at present uncommitted.
SWData is used together with SwAddr0..SwAddr03 and SWDataStrobe0..SWDataStrobe3 to select whether the addressed crosspoint is to be opened or closed.
Extra PIO Port C, bits 4..7, input
DTMFCode0..DTMFCode3.  When the DTMF decoder detects a tone, these signals reflect which tone it is.
DMA Control
The DMA controller is an Intel 8237A-5, or the AMD equivalent, the 9517-5.  This chip is the 5 MHz version, but is run by PClock, a signal which is 1/2 the CPU clock of 7.843MHz.  The 8237 connects to the Hold and HoldA bus signals of the main 8088 and can sieze control of the main CPU bus and shared memory bus.  The 8237 has 4 independent channels which from highest to lowest priority are used for slave CPU shared memory access, Ethernet, Encryption reads, and Encryption writes.
The 8237 is essentially fully programmable.  The truth of its initialization is in LarkMonML.dsm.  The priority structure is normally set as described above, but can be reprogrammed as round-robin.
Slave CPU
Channel 0 of the 8237 is used for slave CPU access to shared memory.  This channel is programmed in "cascade mode" and merely serves to arbitrate bus acess for the slave CPU.
Ethernet
Channel 1 of the 8237 is used in cascate mode to arbitrate bus acess for the SLC Ethernet chip.
The SLC runs the memory system at about 2 microseconds per cycle, four times slower than the CPUs or DMA controller.  When the SLC is transmitting to itself, and therefore transferring 3 Mbps, it uses bus time equivalent to 12 Mbps.  The entire memory bandwidth is 15.7 Mbps, so when the SLC is both reading and writing it uses 3/4 of the bus.  When transferring in one direction only, it uses 3/8 of the bus.
Encryption
Channels 2 and 3 of the 8237 are used together to provide DMA access to memory for the WD2001 Encryption chip.  When the 2001 is ready for data, a request is made via EncRdReq to channel 2 of the 8237.  Channel 2 is programmed by the encryption device driver to read from main memory.  The 8237 generates the memory address and simultaneously activates its MEMR' (memory read) and IOW' (IO write) signals.  MEMR' drives the memory system, via the control multiplexor at B10, and IOW' drives the PWr' bus, which is connected to the 2001.  EncRdDAck (Encryption Read DMA Acknowlege) forces a chip select to the encryption chip and PWr' causes the 2001 to accept the memory data.  EncRdDAck also forces the 2001 signal A0 low, so that the DMA write to the encryption chip will be directed to the data register rather than the control register.
Notice that the DMA controller does not do a separate read from memory and then a write to the device.  The DMA controller generates the address, then signals read to the memory and write to the IO device, letting the data transfer take place directly from memory to device.
A similar sequence of events occurs when the the 2001 signals data available to be writted to main memory.
SLCHoldOff
The SLC Holdoff logic at the bottom of page five was added fairly late in order to correct a DMA interference problem between the SLC and the slave CPU.
Even though the slave CPU has higher DMA priority, once the SLC aquires the bus, it can hold it as long as desired.  The SLC is equipped with 16 byte fifos for data, so it can stand quite long arbitration delays.  However, when an Ethernet transfer is initiated, the SLC immediately fills the fifo from memory, using 16 consecutive cycles.  Since the SLC drives the memory system using two microsecond cycles, it could sieze the memory for 32 microseconds, which was too long for the slave.
The SLC Holdoff circuits try to prevent this circumstance by bunching SLC references towards the end of each T1 frame, allowing the slave CPU clear access to the shared memory during the first portion of the T1 frame.  The slave CPU program is written to bunch shared memory references at the beginning of each frame.
The SLCHoldoff circuit is driven by the SLCHoldOff' signal from the 9513 timer.  This signal is synchronized to the SLC clock by the LS74 at D10.  Gated SLC request, GSLCReq, is enabled by the synchronized rising edge of SLCHoldOff'.  GSLCReq is disabled by the end of the first SLC requset occurring after the falling edge of SLCHoldOff'.  SLCHoldOff' is set low somewhat before the beginning of each T1 frame, to allow time for the rather fuzzy GSLCReq disable conditions to act, and SLCHoldOff' is set high after the slave CPU has had a sufficient chance to reference shared memory.  The timing parameters for SLCHoldOff are not very precise, but it seems to work.
Main Processor EPROM Software
The EPROM for the main CPU contains three kinds of software: basic housekeeping, monitor, and library.  Basic housekeeping software includes things like memory refresh and internal interrupts.  The monitor includes code for downloading and debugging assistance, library software includes subroutine packages of general use which are put in EPROM because there is room.
Hardware reset
Refer to LarkMonML.dsm.  After a hardware reset, the main CPU begins execution at address FFF0 in the EPROM.  This location contains an 8088 long jump instruction to address EOOA, which is a known address for system restarts after a hardware reset.
At this point, the system reset might have been caused by a power on reset, a reset pushbutton reset, or a watchdog timer reset, but which is not known.
Next a few critical IO device initialization actions are taken.  All relays are turned off, the timer is reset, and the watchdog timer is started.  An attempt is now made to distinguish between power up resets and the other cases.  This is done by assuming that if the power has been off, then the RAM has been scrambled.  A seal is stored by the initialization code.  If, after a reset, the seal is gone, then the code assumes that a power up reset has taken place.
Next a full initialzation of IO devices and interrupt vector space is done and the monitor is called.
Hardware initialization
Initialization of the bare machine proceeds as follows:
A temporary refresh cycle is made, by reading 256 consecutive addresses in ram.  This is to tide things over until the real refresh machinery is enabled.
The interrupt vector space is filled.
IO devices are initialized using the initialization control strings stored in EPROM (see LarkMonML.dsm).
The register save area is modified to clear all the segment registers.
Interrupts
After a hardware reset, the main CPU begins execution at address FFF0 in the EPROM.  This location contains an 8088 long jump instruction to address EOOA, which is a known address for system resets.
Hardware reset
After a hardware reset, the main CPU begins execution at address FFF0 in the EPROM.  This location contains an 8088 long jump instruction to address EOOA, which is a known address for system resets.
Execution off the top of RAM into the EPROM
The code in the EPROM at address E000 is intended to catch program execution off the top of the RAM into EPROM space.  The first several instructions are NOPs.  THe reason for this is that the 8088 has variable length instructions.  The longest instruction is six bytes long or so.  By placing seven NOPs at the front of the EPROM, instruction execution will be forced back "in phase" since NOP is a one byte instruction.  The NOPs are followed by a jump to code which sets up the stack to look like an interrupt was taken.  The monitor is then started with code cRUNERR.
NMI button
The refresh code (see below) occasionally polls the NMI pushbutton, which is available to the program as a parallel port bit.  If a down transition is detected, the code at pnmib (possible nmi button) is called to alter the stack so that the interrupt return from the refresh code will transfer control to the monitor with code cNMI and the stack in such a state that the original user job can be resumed.
Return from Monitor
This can't happen, since the monitor is an endless loop, but if it does, the monitor will be restarted with code cMONRET.
Trace Trap
The 8088 trace trap interrupt is used for single stepping.  The 8088 appears to have two hardware bugs that this code patches.  If an interrupt occurs with the trace trap enabled, the interrupt is honored first, but control passed to the trace trap handler.  This case can be detected because the TF flag will be on for real trace traps.  In other cases, the stack is altered so that the interrupt handler will run at full speed and then the trace trap interrupt is dismissed.
The second bug is related.  Sometimes, if interrupts are enabled together with single stepping, several trace trap interrupts occur without any advance of the PC (or any execution of user instructions!)  The monitor checks for this case and will retry the single step up to 200 times before giving up.
Other interrupts
All other interrupts (except the 8259 hardware interrupts) are handled by the UnkInt (unknown interrupt) routine.  The initialization code sets up the vector space so that control passes to UnkInt with the interrupt type encoded in CS.  CS is copied to BX and then a long jump is taken to common code to clear CS.
Common interrupt code
The common interrupt code at intcom is presumed to be called with BX saved, the interrupt code in BX, and CS, IP, and the flags on the stack as they were pushed by the interrupt.  The common code saves the rest of the registers in the save area and branches to the monitor.
Monitor
The monitor is called as a C procedure with the BootReason code as an argument.  No matter what the BootReason, the monitor always follows the same steps:  the attention of a downloading/debugging server is attracted and the monitor enters a loop responding to downloading and debugging requests.
The process of attracting the attention of a server depends on whether a particular server has registered itself with the Lark.  If so, please-help packets containing the Lark state and BootReason are sent to that server.  If no reply is received after several attempts, or if no server is registered, then please-help packets are broadcast at increasing intervals until a reply is received.  The interval stabilizes at 30 seconds.
Refresh
Every millisecond, main CPU takes a non-maskable interrupt, the NMI service routine executes 64 instruction fetches and dismisses.  These instruction fetches are actually directed to the main EPROM, but the RAM memory timing proceeds anyway.  (Actual reads are done, the data is prevented from polluting the main CPU bus because the memory bus data transceiver at F2 is disabled during reads from the EPROM.  The programming of the main system control PROM does this.)
The 64 bytes worth of instructions are mostly NOPs, but contain two other bits of code.  Each millisecond, the 32 bit real time clock is incremented, and the NMI interrupt vector locations are altered to point to the next copy of the NMI service routine.
There are really four copies of the NMI service routine, occupying a contiguous 256 byte section of memory.  The four service routines are executed in round robin order and together refresh the memory, 64 rows each millisecond.
Note 1:  One of the four copies of the service routine contains instructions which poll the manual NMI pushbutton.  If memory refresh is running, depressing the NMI pushbutton will cause a trap to the EPROM monitor.
Note 2:  The 8088 has an instruction prefetch unit.  There is a small fifo of instruction bytes fed by the prefetch unit and emptied by the CPU.  The prefetch unit can fill the fifo at the rate of one byte every 4 bus cycles. The 8088 executes NOP (a one byte instruction) in 3 cycles, so during a long sequence of NOPs, the prefetch queue will normally be empty and the memory bus will be busy.  However, many other instructions, like the ones used to update the clock, run for much longer than the time to fetch the instruction.  During the execution of a sequence of such instrucitons, the prefetch queue will tend to fill up and the bus will go idle.  In order to keep the bus busy and shorten the execution time of the refresh code, the long-running instructions are spread out though the NOPs in order to try to keep the prefetch queue not-full and the bus busy.  This does not disturb the multiple precision increment of the real-time clock because NOP does not affect the condition code.  This allows the ADC (add carry) of the high order clock word to be separated from the ADD 1 of the low order clock word.
Note 3:  A design flaw of the 8086 series is that INC (increment) does not set the carry flag in the condition code, so it cannot be used for a multiple-precision increment.
Slave Processor
The slave processor is nearly all contained on page 9.
The slave CPU is an Intel 8088-2 (8 MHz vesion), running at 7.843 MHz, or one third the system crystal frequency of 23.53 MHz.  The slave system has 8 K bytes of private EPROM, 2 K byes of private RAM, and access to 48 K bytes of shared memory.
The only IO devices controlled by the slave CPU are the voice input and output shift registers.
Processor Control
Housekeeping
The slave 8088 does not require an 8284 clock generator chip.  It runs off the main 8284.  Overall control of the operation of the slave CPU is provided by main CPU control of the signals SlaveReset, which resets the slave, and SlaveNMI, which can generate a non-maskable interrupt to the slave CPU.
Memory Address Space Layout
The slave CPU, like the main, operates entirely within a single 64 K byte memory address space.  Address bits A16, . . ., A19 are not used, so the 64 K space which is used is repeated throughout the 1 MB address space of the 8088.  The 64 K memory address space is broken into 8 regions of 8 K bytes each.
Region 0, addresses 0000H - 1FFFH -- slave EPROM 
Region 1, addresses 2000H - 3FFFH -- slave RAM
Region 2 - 6, addresses 4000H - DFFFH -- shared RAM
Region 7, addresses E000 - FFFF -- slave EPROM
EPROM
The slave EPROM is a 2764 8K by 8 chip.  The socket is wired in such a way that a 2716 can be plugged in, should it ever be interesting to use a smaller but less expensive chip.
The slave EPROM appears in two places, at address 0 and at address E000H.  The 8088 starts execution after a reset at address FFF0H, so this space is mapped to the EPROM.  The address space at 0 is needed to support interrupt vectors, such as non-maskable-interrupt, so this space is mapped to the EPROM as well.
RAM
The slave RAM is only 2K bytes, but occupies 8 K bytes of address space.  It is repeated 4 times, appearing at 2000H, 2800H, 3000H, and 3800H.  The copy at 2000H is the primary copy.  Slave RAM is needed for a small stack to support interrupts, scratchpad space for bufffering data, and space for soft-loading of programs and tables.
IO Address Space Layout
The only two IO devices are the voice input and output shift registers.  The input shift register occupies one byte at (currently) IO address 000H.  The output shift register occupies two bytes at 004H and 00CH.  The most significant bit of the output shift register (the mu law sign bit) is wired to bit 3 of the address bus, so that to write a positive 7 bit value to the output shift register, write it to address 004H, but to write a negative 7 bit value to the output shift register, write it to address 00CH.  Look at the EQUs in LarkSDlave.dsm for the port addresses, should they change.
Shared Memory Access
When the slave processor makes a memory reference to the region of address space between 4000H and DFFFH, the slave system control PROM at location #c6 decodes the address as being in shared memory.  The signal SelShare' is activated.  This signal is inverted (to PreSlaveReq), delayed one cycle of SysClk and presented to the 8237 DMA controller as SlaveReq.  Simultaneously, the leading edge of PreSlaveReq causes SlaveReady to go low, halting the progress of the slave bus cycle.  Eventually, the DMA controller will aquire control of the main CPU and memory busses and return an acknowlegement to the slave system as SlaveDAck'.
SlaveDAck' becomes GSlaveDAck' (gated slave DMA ack), which enables the slave system shared memory address bus drivers (#b3 and #c3) and data bus transceiver (#a5).  At the same time, GSlaveDAck' enables the control signal multiplexor at #b10 (page 2) to gate SlaveRd' and SlaveWr' onto Rd' and Wr', the main read and write control lines.  These main control lines activate the shared memory system.
GSlaveDAck' is further delayed and then causes SlaveReady to go high, allowing the slave CPU to complete the buys cycle and proceed (this delay is adequate so that the shared memory data will be valid by the time the slave CPU gets around to latching the memory data on a read).  At the time of the next slave ALE, the slave system control PROM (if the address leaves the shared memory region) will release SelShare'.  When SelShare' is released, GSlaveDAck' is immediately disabled, to prevent the slave address drivers from polluting someone else's cycle, and SlaveReq is released.  The release of SlaveReq eventually propagates through the 8237 and releases the main system busses.
Notice that if the slave CPU makes consecutive references to shared memory, the shared memory will be held active.  The shared memory will only be released if the slave CPU makes a reference to an address outside the shared region.  For a burst reference, then, the slave processor will only incur one shared memory arbitration delay.  This has a number of consequences for the programming of the slave CPU:
Word references are better than byte references.  The 8088 has an 8 bit bus, and word references proceed as two consecutive 8 bit references to adjacent addresses.  The second byte reference is essentially free for the slave because it does not incur a shared memory arbitration delay.
Block instructions are good, but.  The most interesting fact is that the 8088 instruction STOSW, store-string-word, makes many consecutive references, so it does not release the shared memory.  MOVSW makes alternating word read and work write references, so it releases the shared memory between words.
Beware of instuction fetches.  Even if all the data references in your program are to shared memory, the slave CPU will release the shared memory in order to fetch instructions from local memory.  The details of this process are a bit fuzzy, since the 8088 has an instruction prefetch unit.
Read the section on the DMA controller and arbitration of the shared memory for additional information.
Synchronization
The slave processor program is responsible for the handling of all voice samples.  The voice shift registers are single buffered, so the slave CPU must be very careful to reference the IO locations corresponding to the shift registers at times when they are not shifting.
This problem is solved by the signal SamSync'.  SamSync' is set by FrameSync', which occurs every 125 microseconds at the start of each T1 frame.  SamSync' is cleared by a write to the voice output shift register (OSRWr').  SamSync' is connected to the Test' input of the slave 8088, and is used for time synchronization of the slave CPU program.  The synchronization is accomplished by the 8088 WAIT instruction.
Voice IO
Input shift register
The voice input shift register is the LS299 at location #e7.  It is clocked by AudShClk (Audio Shift Clock), which is generated by the AND of T1Clk and TSN.  It is a burst of eight cycles of T1Clk (1.536 MHz) every 62.5 microseconds.  It shifts the serial voice data from the codecs into the input shift register.
The input shift register is gated onto the slave data bus by the AND of SelISR (select input shift register) and SlaveWr.  The slave program must be careful not to do such a read reference while the register is shifting.
Output shift register
The voice output shift register is the LS166 at location #a4.  It is clocked by OSRClk' (output shift register clock), which is generated by the OR of AudShClk and OSRWr.  In addition, the shift/load' control is connected to OSRClk' (which is the AND of SelOSR and SlaveWr).  The register is loaded by a slave CPU wirte operation to either address 004H or 00CH, and then shifted by AudShClk.
The input shift register is gated onto the slave data bus by the AND of SelISR (select input shift register) and SlaveWr.  The slave program must be careful not to do such a read reference while the register is shifting.
One thing to notice is that the input and output shift registers shift on different edges of AudShClk.  Careful study of the Intel 2910 codec data sheets will reveal the rational for this.
SamSync' note
Originally, the synchronizing signal for the slave CPU was simply TSN.  This would work fine provided that the slave was guaranteed to begin execution of the WAIT instruction before the end of TSN.  Two factors led to the current scheme of having SamSync set by FrameSync and cleared by a write to the output shift register:
DMA interference introduces variable running time of the slave CPU loop.  The set/clear model makes it possible for the slave to "keep up" provided that the average running time of the loop is under 125 microseconds and that no single shift register access miss the window of opportunity (while the register is not shifting)..
TSN is now active for both time slot 1 and timeslot 13.  Where before, the slave might miss a sample if it missed a TSN, now it will not slip out of phase with the codecs and start sending material to the wrong codec.
Slave CPU Program organization
Naturally, the software can change at any time, so this discussion is pertinant to the slave PCU software as of January 13, 1984.  Refer to LarkSlave.dsm
Initialization
On slave CPU reset (which is generated by a parallel port bit from the main CPU), the slave begins execution at location FFF0H.  This location contains an 8088 long jump instruction which clears the CS register and transfers control to location E000H, the start of the slave EPROM.  This code path contains a HLT instruction followed by a jump to the halt.
Note to repairmen:  This has a bug, the initialization code should set up the other segment registers and a stack, so that the NMIs will have someplace to go.  It seems to work, but it is probably lucky.
Note to repairmen:  The HLT, JMP *-1 sequence is necessary to create an infinite loop.  If an interrupt is taked during the execution of a HLT, then when the interrupt returns, execution resumes at the instruction after the HLT.
The main processor starts the slave running by issuing a SlaveNMI positive transition via the parallel port.  This forces the slave CPU to trap to location 0008H.  Since the EPROM is exists at location 0 as well as E000H, this is in effect the same as a trap to E008H.
E008H contains a vector directing the slave CPU to begin execution of the main line slave EPROM code.  This code initializes the machine, then reads a control block from a fixed location in shared memory.  The control block directs further action.
Slave CPU dispatch
When the main CPU wakes up the slave by using an NMI, the slave CPU reads a control block from shared memory.  The control block currently occupies shared memory in the vicinity of address D9F0.  See LarkSlave.dsm.  After an NMI, slave execution transfers to location SlaveNMI.  The word in shared memory at location CodeLoc is tested against a series of constants:
Prog03I1:  start executing voice program O3I1  (see below)
Prog02I2: start executing voice program 02I2  (see below)
ProgBLT: execute a BLT within the slave address space.
The slave reads parameters for a block transfer from shared memory, then executes the bloct transfer withing the slave address space.  Since the slave address space includes shared memory, this BLT can transfer data between the main and slave systems.  This method is used for soft loading the slave RAM and for debugging slave programs.
ProgJMP: transfer to a particular address in the slave address space.  This command can start execution of soft loaded code in the slave RAM, for example.
LoadCode (default):  load slave RAM software from shared memory and start.  This function has been unbundled and generalized by ProgBLT and ProgJMP.  It should probably be removed.
Main Loop
The slave CPU normally executes in a tight loop processing voice samples.  As of January 13, 1984, there are two copies of the loop in slave EPROM (03I1 and O2I2).  They do different things but have a common organization.
The loop is synchronized by a WAIT instruction.
WAIT polls the Test input of the CPU.  This pin is wired to SamSync', which is set by FrameSync', which happens at the beginning of each T1 frame.  Thus after the execution of a particular pass of the slave loop, the program waits for the next FrameSync before proceeding.
The loop is unrolled 8 times.
There are 8 copies of the code for the loop in the slave EPROM.  The idea is that references to shared memory via block instructions are more efficient than accesses via random instructions.  The slave program is written to deal with 8 sample blocks of voice.
All shared memory references are concentrated at the head of the loop.
The head of the loop occurs in close proximity to FrameSync (due to the synchronization).  All shared memory references occure immediately after the WAIT instruction.  At this time, the SLC (Ethernet chip) is supposed to be disabled by the SLCHoldOff circuits, leaving the shared memory available for the slave CPU.  See the section on SLCHoldOff for more information.
Program O3I1
One of the standard slave programs is called O3I1, for out-three in-one.  This program reads three voice streams from ring buffers in shared memory and adds them together into a single outgoing stream which is sent to the voice output shift register.  The output ring buffers are zeroed after reading.  O3I1 also reads a single voice stream from the voic einput shift register and writes it to a ring buffer in shared memory.
Program O3I1 loop structure
The shared memory references in the eight copies of the main loop code accomplish the following functions:
Loop 0:
read InGain and OutGain control words from shared memory
write the ring buffer pointer to shared memory
write the silence value (voice energy) to shared memory (every 160 samples only)
Loop 1: write 8 voice samples to the input ring buffer
Loop 2: read 8 samples from #3 output ring buffer
Loop 3: read 8 samples from #1 output ring buffer
Loop 4: read 8 samples from #2 output ring buffer
Loop 5: write 8 zeros to #1 output ring buffer (auto-zero)
Loop 6: write 8 zeros to #2 output ring buffer (auto-zero)
Loop 7: write 8 zeros to #3 output ring buffer (auto-zero)
Program notes
Conference calls are handled by summing the voice found in the three output ring buffers and sending the composite stream to the D/A portion of the CODEC.  Since the voice is stored in the ring buffers in encoded form, the summing process involves the conversion from mu-law to linear, an addition with limiting, and a conversion back to mu-law before the voice sample can be sent to the CODEC.  The conversion from mu-law to linear is handled by a 256 entry table of 16 bit words.  The encoding of the 16 bit values is two's complement.  After the linear values converted from the three ring buffers are added together, tests are made for overflow and underflow.  Since the voice output shift register appears at separate port addresses for positive and negative values, the code first branches on the sign of the result then checks for positive or negative overflow.
If the low order bit of the mode word (SPMode) is set, the incoming voice stream from the CODEC is added into the conference facility as a fourth party.
Program O2I2
One of the standard slave programs is called O2I2, for out-two in-two.  It drives both codecs independently.  For each codec, samples from a shared memory ring buffer are played out through the codec, an energy number is computed from samples read from the codec, gain is applied to samples read from the codec, and the gain controlled samples are written to a shared memory ring buffer.
Program O2I2 loop structure
The shared memory references in the eight copies of the main loop code accomplish the following functions:
Loop 0:
write the ring buffer pointer to shared memory
write the silence value for CODEC 1 to shared memory (every 160 samples only)
write the silence value for CODEC 2 to shared memory (every 160 samples only)
Loop 1: write 8 voice samples to the input ring buffer for CODEC 1
Loop 2: write 8 voice samples to the input ring buffer for CODEC 2
Loop 3: read 8 samples from #1 output ring buffer
Loop 4: read 8 samples from #2 output ring buffer
Loop 5: write 8 zeros to #1 output ring buffer (auto-zero)
Loop 6: write 8 zeros to #2 output ring buffer (auto-zero)
Loop 7: 
read gain control word for CODEC 1
read gain control word for CODEC 2
read mode bits (SPMode)
Program notes
If SPMode is set, then the input and output ring buffers are located at the same address in shared memory.  Since the voice input from the codec is handled first, this passes the input voice through to the output.
Analog Board
The Lark analog board is organized around an 8 by 8 analog crossbar switch.  The inputs and outputs of the crossbar switch connect to analog interfaces for the telephone set, telephone line, microphone, speaker, DTMF decoder, CODECs, and line inputs and outputs.
Physical considerations
The Lark analog board plugs onto the back of the digital board in a sandwich arrangement, The analog board receives communications and power through a 56 pin connector.
There are no internal cables.  Connectors for analog services (e.g. telephone line) mount directly on the edge of the analog board and through the Lark connector panal.
The analog board is supported at the front (connector panal) edge by angle brackets and at the rear edge by the interboard connector.
Signal levels
The general idea for signal levels within the analog board is that all the various sources and sinks traffic in a standard signal level at the crossbar switch.
What is the standard level?
According to CCITT, a test tone at 0 dBm analog should be 3.17 dB below the digital clipping level.  Let's work with voltage rather than power, so that we can ignore impedance levels for the moment.  0 dBm is 1 milliwatt in 600 ohms, corresponding to  (P = E^2/R)  0.775 v RMS or 0.775 * 1.41 * 2 = 2.19 v peak-to-peak.
If 2.19 v p-p is "0 dBm", then what is the digital clipping level?  3.17dB corresponds to a voltage ratio of 1.44, so digital clipping level should be 1.44 * 2.19 = 3.15 v p-p.
Standard levels at the crossbar switch.
The crossbar switch, described below, is designed so that digital clipping level at the Codecs corresponds to a voltage at the crossbar at 2.13 v p-p.  Thus the digital clipping level is -0.24 dBm and the voltage at the crossbar corresponding to "0 dBm" is 3.17 dB lower or -3.41 dBm.  The voltages involved at the crossbar are .523 v RMS or 1.48 v p-p.
All sources should produce this standard signal of 1.48 v p-p and all sinks should accept this level.
Differential levels and the telephone interfaces.
Inside the analog board, all sources should produce "the same" level and all sinks should accept this level.  This is easy for codecs and line.  However, because of the loss in the local loop, telephone sets are designed to transmit a relatively louder signal and receive a relatively weaker one.
The amplifiers which handle the telephone set and the telephone line will have to compensate for this effect.
The TeleSetSource amplifier will introduce loss to bring down the teleset transmit level to the standard level.  The TeleSetSink amplifier will introduce loss to reduce the standard level to that expected by the telephone set.
The TeleWallSource amplifier will introduce gain to boost the weak signal from the central office to the standard level.  The TeleWallSink amplifier will introduce gain to bring the standard level up so that it will compensate for the loss going to the central office.
This design strategy has a deleterious effect on hybrid performance.  Suppose the round trip loss to the CO is 10 dB.  Then the transmit and receive arms of the four wire side of our hybrid must have 5 dB gain each.  If the native hybrid had 20 dB return loss, then the final system will have only a 10 dB return loss.
Crossbar switch
The crossbar switch is contructed from four Motorola MC142100 analog crosspoint switches.  Each 142100 contains 16 separately switchable crosspoints connecting four inputs and four outputs.  The four 142100s are interconnected in a square array yielding an 8 by 8 crossbar switch.
The crossbar switch is shown on page four of the analog schematics.
Electrical Architecture
The crosspoint chips are operated between plus 5 and ground, primarily in order to make the digital control ports TTL compatible.  These operating conditions mean that all analog signals must be confined to the range between 0 and 5 volts as well.  If an analog input exceeds this range, the crosspoint switches may begin to conduct even if they are supposed to be off.
The DC operating point of the crosspoints is maintained at 2.5 volts by capacitively coupling all analog inputs and outputs through 0.33 microfarad capacitors C22 - C37.  The DC reference is supplied to each input and output by 470K ohm resistors connected to SwitchRef, the 2.5 volt source. SwitchRef is heavily bypassed by C38 and C39 to avoid coupling between crossbar ports through the 470K resistors.
The 0.33 microfarad coupling capacitors provide a 1600 ohm impedance at 300 Hz.
All sources which feed the crossbar switch are designed for 10 K ohm source impedance.  All sinks are designed to present "high" load impedances.  The general idea is that one source can drive many sinks with little loss, and that several sources can drive a single sink by resistive mixing.  When two sources drive a single sink, however, there is a 6 dB level loss for each source because the two 10K source impedances form a 50% voltage divider.
Digital Control
As mentioned above, the digital control liens for the CODECs are TTL compatible.  Each MC142100 has six control lines, A, B, C, and D address one of the sixteen crosspoint switches within the chip.  Din is the data line and says whether the crosspoint is to be opened or closed.  Strb is a clock line that latches Din into the selected crosspoint.
The four MC142100s are controlled by 9 control lines from the digital board.  SwAddr0..SwAddr3 are bussed to the A, B, C, and D lines of each chip.  SwData is also busses to all chips.  SwDataStrobe0..SwDataStrobe3 are separately wired to the Strobe inputs of each chip.
The strobe lines are wired separately in order to avoid a demultiplexor.
To set a particular crosspoint of the 64 possible crosspoints, SwAddr0..SwAddr3 and SwData are set up in a way appropriate for the particular crosspoint in the particular chip, then the appropriate strobe signal is asserted.
At present, the software only changes one crosspoint at a time, but the hardware is capable of setting or clearing the corresponding crosspoints in more than one chip by simultaneously asserting more than one strobe.
Levels
Digital clipping level at the codecs corresponds to 2.13 v p-p at the crossbar.  The crossbar switch will not start to misbehave until the signals reach nearly 5 v p-p, which gives a 6 dB margin.
Two sources, Microphone and TeleWall, have special circuitry to limit levels.  The diode strings at the top of page 4 limit the Mike and TeleWallSrc nets to plus or minus 1.4 volts relative to SwitchRef.  These two sources are the only ones which might commonly be expected to overload under some conditions.  (The line level sources are the next most likely, but they are not protected.)
CODECs
The CODECs are shown on page 1 of the analog schematics.  There are two CODEC-filter pairs, each constructed with the Intel 2910A CODEC and 2912A switched capacitor filter.
Analog interface
Digital clipping level at the output of the 2912 (pin 4) is +/- 3.2 v or 9.3 dBm.  The resistive divider (R7, R8 or R16, R17) connecting the codec to the crossbar has a ratio of .333, putting the peak voltage at the crossbar at 2.13 v p-p, as desired.  Pin 4 (VFRO) of the 2912 is an operational amplifier output and has essentially zero impedance.  The parallel combination of the output voltage divider presents a 10 K ohm impedance looking into the CODEC output from the crossbar.
The transmit section of the codec (CodecSink) has an intrinsic 3 dB gain, plus gain setting resistors, the gain is (1 + R5/R4) + 3 dB.  R5 = R4, so the overall gain is 2.82 (1/0.354).  The crossbar is capacitively coupled and 2912 pin1 (VFX1+) is an operational amplifier input with very high impedance.  R6, the 470K ohm resistor, is intended to provide a zero volt DC operating point to the op amp and to provide a source of bias current.
Digital interface
The T1 serial bit stream from the digital board voice out shift register arrives on the VoiceOut' net along with the 1.536 MHz clock T1Clock.  T1Clock is used both as the shift clock within the 2910 CODEC, but as the master clock for the 2912 switched capacitor filters.  Synchronization is provided by FrameSync.  FrameSync provides a one cycle pulse during the T1Clock cycle immediately before the 8 cycles containing voice data for CODEC 1.
CODEC 1, because the DC input is grounded and the ClkC input is pulled up, automatically operates in time slot 1 (or 0), the time slot immediately after FrameSync.  This is so-called direct control mode.  The output TSX' is a useful test point because it is driven low during the time slot that the CODEC thinks is active.
CODEC 2 operates in a time slot programmed by the digital board.  The two signals CodecControlData and CodecControlClk are parallel port bits which form a programmed IO serial channel.  CODEC 2 is directed to operate in a particular time slot by information shifted in serially on these lines.  The only restriction on this process is that it be completed within one frame time (125 microseconds).  The software does this by waiting sor SynTSN before starting the programmed IO shifting of the timeslot information into the CODEC.  This code is written in assembler.
Microphone
The microphone preamplifier is shown on page 2 of the analog schematics.
Analog interface
The microphone amplifier is designed for 600 ohm microphones.  Jumper J1 permits the Lark to provide phantom power to a microphone which requires it.  Trimpot R25 permits microphone gain adjustment within a narrow range.
Circuit notes
The amplifier has no automatic gain control. The second half of U8 is unused in order to avoid crosstalk problems.  Resistor R28 sets the source impedance of the microphone amplifier as seen by the crossbar switch to 10K ohms.
Speaker
The speaker amplifier is shown on page 2 of the analog schematics.
Analog Interface
The input from the crossbar switch to the speaker amplifier is through SpeakerSink.  Because the crossbar output is capacitively coupled, resistor R29 provides a 0 volt DC operating point for the input of op amp U9 and provides a source of bias current.  The amplifier is a single ended LM1877 design and can provide about a 6 v p-p undistorted sine wave output.  This translates to about 1/2 watt into an 8 ohm speaker.
Digital Interface
The speaker amplifier is provided with two volume controls.  One is the internal trimpot R32 and one is the external potentiometer on the speaker control box.  One or the other volume control is selected by the CD4053B analog switch under the control of the p[arallel port bit EnableRing'.  The idea is that the internal trimpot will be enabled during the generation of ringing sounds, so that the user cannot inadvertently turn off ringing merely by turning down the volume control on the speaker box.
DTMF decoder
The DTMF decoder uses the Mitel MT8865 DTMF filter chip and MT8860 detector chip and may be found on page 3 of the analog schematics.
Analog Interface
The Mitel chip set is very sensitive, so a resistive voltage divider is used between the crossbar switch and the 8865 filter chip in order to present a high impedance to the crossbar.  Components R43, R44, and C17 set the detection parameters of the detector.
Digital Interface
The four signals DTMFCode0..DTMFCode3 are wired to a parallel input port on the digital board, they present the active DTMF tone when the CodeValid signal is high.  Transitions of CodeValid, through the sense scanner, produce interrupts on the digital board.
Line level
The line level circuits may be found on page 3 of the analog schematics.
Line Input
The line input amplifiers, in op amp U14 are capacitively coupled to the outside world.  They are designed to have a load impedance of 10K ohms to the external source.  This (for audio) moderatly low impedance makes noise pickup much less of a problem.  The line in amplifiers have a gain of 1.5, so that a one volt p-p external signal corresponds to "0 dBm" at the crossbar.
The line input amplifiers have no intrinsic level limits other than the plus and minus 12 volt power suply rails.  It is possible to drive a strong signal into the line in ports and overload the crossbar switch, producing feedthrough into not-intentionally-connected circuits.  If the external signals stay below about 3 v p-p there will be no trouble.
Line Output
The line output amplifiers, in op amp U15 are capacitively coupled to the output circuits, to positively prevent a non-zero DC output.  The external connectors are referenced to the analog board ground, hovever, through the output voltage dividers.  They are designed to have a source impedance of 1 K ohms to the external sink.  The line out amplifiers have a gain of .687, so that a "0 dBm" signal at the crossbar will produce a one volt p-p external signal.
Telephone Set
The Telephone Set interface (TeleSet) circuits may be found on page 6 of the analog schematics.
Digital interface
The telephone set interface is equipped with a Revert function, or power-fail line transfer circuit.  When the poower fails, or the Revert command signals are asserted, all the relays on page 6 fall back to their deenergized states.  When this happens, the telephone set is connected directly through to the back-door telephone line, so that the user retains telephone service.
The Revert function is implemented in two parts, the main part, controlled by the Revert' paralllel port bit, switches the talking paths of the telephone set, the receiver and transmitter, back to the phone line.  The secondary part of the Revert function, controlled by the SwitchHS' control line, switches the telephone set hookswitch contacts to the A and A1 leads of the back door.
Another digital control function related to the telephone set is Sidetone.  In a normal telephone, a small portion of ones own voice is fed back from the transmitter (mouthpiece) to the receiver (earpiece).  This makes the telephone sound "live".  In the Lark, this function is switchable, uinder the control of the SideTone' parallel port signal.  When active, Sidetone causes voice to flow through the TeleSetBypass net and  into the amplifier which drives the telephone set receiver.
Analog interface
Resistor R77 sets the 10 K ohm source impedance seen by the crossbar switch.  Resistor R79 provides the usual zero volt DC operating point and bias current source for the TeleSetSink buffer amplifier.
The telephone set used with the Lark is a standard 2500 type set, slightly modified for four wire service.  Normally, the telephone set receiver is driven directly by the network inside the telephone.  The Lark telephones are modified to bring out the receiver terminals to the analog board (HSRcvr1 and HSRcvr2).  In addition, the points on the network where these leads were originally attached are also brought out (HSRcvr1A and HSRcvr2A).  Relay K2 is responsible for switching the receiver.  In the de-energized position it connects the telephone set receiver back to the network, restoring the original 2500 set circuitry and disconnecting the receiver from the TeleSetSink amplifier.  In the energized position, K2 connects the receiver to the TeleSetSink amplifier.  Relay K3 handles the transmitter path.  In the de-energized position it connects tip and ring of the telephone set (called HSXmtr1 and HSXmtr2) through to tip and ring of the telephone line.  In the energized position, it connects tip and ring of the telephone set to the "local battery" and the TeleSetSrc amplifier.  Relay K4, controlled by SwitchHS', handles the switchhook.  In the de-energized position it connects the telephone set switchhook contacts through to A and A1 of the telephone line.  In the energized position, it connects the telephone set switchhook contacts to the SwitchHook' sense line.  Transitions of SwitchHook', through the sense scanner circuits, cause interrupts on the digital board.
Circuit notes
When the telephone set is connected to the Lark, (reversion relays energized), transistor Q1, acting as a current source, provide local battery. Loop current is approximately calculated by .7 volts accross R74, which at 18 ohms provides about 40 milliampers of loop current.  The on-hook loop voltage is 12 rather than 48, for a real phone line.
The follower formed by pins 1, 2, and 3 of U23 is present in order to keep the resistor values of the summing amplifier down to reasonable values while still providing a high impedance to the crossbar.
TeleSetSource has a gain of 0.386 (or -8.26 dB).  After accounting for the -3.41 dB reference level, the extraordinary gain of TeleSetSource is -4.85 dB.
TeleSetSink has a gain of 1.33 (2.5 dB), but the Telephone set receiver is fed through a 910 ohm resistor, which forms a voltage divider together with the receiver element.  The division ratio of this voltage divider must be measured before the extraordinary gain can be determined.
Telephone Line
The Telephone Line interface (TeleWall) circuits may be found on page 5 of the analog schematics.
Digital interface
The digital controls for the telephone line interface are the control signals ShuntA' and GoOffHook for the two relays.  GoOffHook connects tip and ring of the telephone line to the electrinci holding coil and hybrid.  This "picks up" the phone line either for placing or answering a call.
ShuntA connects the A lead to the A1 lead.  This activates the key system.  (Generally, one puts a line on hold by breaking the A-A1 connection before dropping the line.)
The ring detector provides a digital indication of ringing from the central office.  Transitions of RingIndicator, through the sense scanner, cause interrupts on the digital board.
Analog interface
Resistor R71 sets the 10 K ohm source impedance seen by the crossbar switch.  Resistor R60 provides the usual zero volt DC operating point and bias current source for the TeleWallSink buffer amplifier.  Jumper J3 is normally set to the AB position, so that the voice driving the TeleWall comes only from the output of Codec 1.  This design choic is for FCC registration purposes.  Voice from Codec 1 will be low-pass filtered by its passage through the 2912 filter chip and the software on the digital board can provide level limiting to assure that the 3 second average power on the phone line does not exceed -9 dBm.
The analog interface  to the phone line is via the electronic holding coil formed by Q2 and the hybrid circuit centered aropund transformer T1.  C43 is present because the Midcom 671-0339 transformer is not rated for DC.
Circuit notes
When the telephone set is connected to the Lark, (reversion relays energized), transistor Q1, acting as a current source, provides local battery. Loop current is approximately calculated by .7 volts accross R74, which at 18 ohms provides about 40 milliampers of loop current.  The on-hook loop voltage is 12 rather than 48, for a real phone line.
LED drive
The LED circuits are on page 7 of the analog schematics.  The digital control signal LED, when high, allows current to flow from VCC through R88, diode 21, and the light emiting diode (which is located on the speaker box).  When LED is low, current from VCC through R88 is shunted to ground through the open collector gate driving LED.  Diode 21 is present so that the light emiting diode will be off provided that the LED control signal is below about one volt.
Sense Scanner
The sense scanner circuits are on page 7 of the analog schematics.  The general idea is that and transition of any of the four digital signals, SwitchHook, RingIndicator, Switch, and CodeValid will cause AlogInt' to go low, triggering an interrupt on the digital board.  When the interrupt handler runs, the sixteen possible combinations of the four parallel port bits SenseSH, SenseRI, SenseSwitch, and SenseCode are tried under program control, until a configuration is found that matches the signals SwitchHook, RingIndicator, Switch, and CodeValid.  The program can then make a note of which ones changed. 
Silence
The signal marked Codec1BSrc on the analog schematics drives input 4 of the crossbar switch.  This signal was originally intended to be a higher level version of Codec1ASrc.  WIth R10 set to 330 ohms and R9 left not-installed, this crossbar input is silence.  This signal does not correspond to the general notion that crossbar sources have 10K ohm impedance.  Silence has a 330 ohm impedance.  This is fine because it does not make any sense to mix silence and any other signal source.
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