; Microcode for Spruce -- Orbit, TriCon
; PackMu XSpruceMc.Mb SpruceMc.Br 77764

#SpruceDefs.mu;

; Initial Instructions for RAM tasks
!17,20,NOVEM,ORBIT,,LOC3,,,,,,,,,,,LOC16,LOC17; 0-17

; (There is a hack in the read microcode that causes the reset location for task 16 to be used. This means
; that it is not possible to run task 16 (= Diablo disk word task) in the Ram.)

; RAM entry points: RMR set, special Spruce Interpretation operations, PC link returns, Ram Trap code
!17,20,START,LOC21,LOC22,ROWROT,FlushChars,ShowChars,Mret,DoR,BandEnter,BankBlt,,,,,,RamTrap; 20-37

; (177026 is PC-return code passed to MUL in uses update code within ShowChars, so Mret is 26
; DoR is modified during LOADR, STORER instructions to do the actual register manipulation)

;*** This code is carefully placed in the RAM for an emulator "no-op boot". Boot locus bit 15 must be 0.

NOVEM: SWMODE;
:START;

;***This instruction will cause the boot-locus-vector to be set to the value in AC0 at the next boot
;JumpRam(20b) or (22b) will set reset mode register -- one was Spruce convention, the other Trident

START: RMR←AC0, :NOVEM; this location (20) is emulator’s START in ROM!
LOC22:RMR←AC0,:NOVEM;

; RAM TRAP -- used for GetFrame, Return, LOADR, STORER (R-reg read/write)
; This code derived from [*]<Altosource>BcplRunTimeSources.dm(RamTrap.mu)

; Trap handler and dispatcher for instructions that trap into the RAM. In the following predefinition,
; the tags correspond to opcodes 60000, 60400, 61000, 61400, ... 77400. Note that opcodes 60000, 60400,
; 61000, 64400, 65000, 67000, and 77400 cannot be used since control never gets to the RAM for these.

;61400 62000 70000 70400 71000 71400
!37, 40, TrapDispatch,,,GetFrame, Return,,,,,,,,,,,,StoreR, StoreS, LoadR, LoadS;

;; STORER is Nova instruction 70000. STORER r*8 does [ @AC0←r; AC0←AC0+1 ].
;; LOADR is Nova instruction 71000. LOADR r*8 does [ r←@AC0; AC0←AC0+1 ].
;; If r is an S-Register, this approach will turn STORER into STORES and LOADR into LOADS.

RamTrap:
instr←L;Added by DCS to retain original for IR dispatch later
T←37;
L←XREG AND T;
TrapDispatch:;Can’t loop here because opcode 60000 doesn’t cause RamTrap
SINK←LREG, BUS, TASK;
:TrapDispatch;

%2,3,1, DoSto, DoLd; Kill low bit of IR dispatch, below
%1,1777,1772, DoSt1, RQuit; DoSt1 must be at 1772; DoR goes to 1772 or 1773

StoreS:T←60;
L←0, :LoadStore;
StoreR:L←T←0, :LoadStore;
LoadS: T←100, :LS1;
LoadR:T←20;
LS1:L←2000;
LoadStore:
low←L, L←T;
T←XREG;
XREG←L;
T←177400.T;
T←7+T+1;
L←XREG+T, TASK;
XREG←L; **
MakeLow:
T←low;
L←101771+T+1;
low←L;
L←XREG;
T←27, WRTRAM;
L←low;
; one cycle
IR←instr;
MAR←AC0, :DoSto; [DoSto, DoLd]
DoSto:SINK←0, BUS, :DoR;
DoSt1:MD←LASTL, :RQuit;
DoLd:NOP;
;available
;available
L←MD;
SINK←0+1, BUS, :DoR;
RQuit:L←AC0+1, TASK;
AC0←L, :NOVEM; **

DoR:NOP, :DoSt1; [DoSt1, Rquit] L←R or R←L -- rewritten before execution each time

; BankBlt(from, to, size) -- all assumed even
; from = AC0
; to = AC2
; size = AC3, assumed even

!1,2, BankGo, BankDone;

BankBlt:
T←AC3;
L←AC0+T;
AC0←L;
L←AC2+T;
AC2←L, :lp1;
BankLoop:
T←AC3;
lp1:MAR←AC0-T;
L←-2+T;
AC3←L, SH<0;
NOP, :BankGo;
BankGo:
L←MD;
MTEMP←L;
L←MD;
XMAR←AC2-T;
NOP;
MD←MTEMP, TASK;
MD←LASTL, :BankLoop; **
BankDone: TASK;
:NOVEM; **



#TriConBody.Mu;From [*]<Altosource>TFSSources.dm
#GetFrame.Mu;From [*]<Altosource>BcplRuntimeSources.dm
#OrbitMc.Mu;The body of the Orbit microcode
;;#RowRotateMc.Mu;The Spruce row rotation microcode
;;#ShowCharMc.Mu;Spruce Showchars inner loop!

;; DCS, December 5, 1977 5:40 PM, derived from OrbitMc and Tricon Microcode
;; December 27, 1977 2:21 PM, Reassign R71-R76 to get out of Tricon’s way
;; March 6, 1978 4:29 PM, becomes "command" file with TriCon’s improvement; add RowRotate
;; October 3, 1978 11:49 AM, add ShowCharMc
;; October 19, 1978 8:11 AM, add LOADR, STORER RamTrap instructions
;; October 20, 1978 12:01 PM, add SpruceDefs, reorganize, add Taft-style RAM Trap code
;; October 23, 1978 6:51 AM, add FlushChars at 24
;; April 5, 1979 9:39 AM, version that includes XM font microcode
;; April 7, 1979 4:00 PM, add BankBlt(from,to,size) at 31 -- all args must be even, requires Alto II
;; January 29, 1980 10:51 AM, derived from XSpruceMC.mu
;;