-- File: [Indigo]Dragon>DragonProcessorImpl1.sak -- Dragon processor with random fetch -- DIRECTORY DragonCache: TYPE, DragonProcessor: TYPE, SakuraRT: TYPE, SimIO: TYPE; DragonProcessorImpl1: MONITOR IMPORTS SakuraRT, SimIO EXPORTS DragonProcessor = BEGIN Processor: PUBLIC PROC [ClockA, ClockB, Fault, Reject: SakuraRT.Handle, InData: SakuraRT.Handle, Op: SakuraRT.Handle, RQ: SakuraRT.Handle, OutData: SakuraRT.Handle] = { Fetch: PROC [vp: LONG CARDINAL, bl: INTEGER [0..37B], word: INTEGER [0..3]] = { printval: LONG CARDINAL _ word + bl * 4 + vp * 128; SakuraRT.GetNew[ClockB, TRUE]; {SakuraRT.Put[RQ, NEW[BOOLEAN _ TRUE]]; SakuraRT.Put[Op, NEW[DragonCache.PbusOp _ Fetch]]; SakuraRT.Put[OutData, NEW[DragonCache.PbusType _ [Instruction[vp, bl, word]]]]}; DO SakuraRT.GetNew[ClockA, TRUE]; IF NOT NARROW[SakuraRT.Get[Reject], REF BOOLEAN]^ THEN EXIT ENDLOOP; SimIO.WF1[" Fetch started %ld*n", @printval]; SakuraRT.GetNew[ClockB, TRUE]; SakuraRT.Put[RQ, NEW[BOOLEAN _ FALSE]]; SimIO.WF1[" Fetch finished %ld*n", @printval]}; FetchAndRead: PROC [vp: LONG CARDINAL, bl: INTEGER [0..37B], word: INTEGER [0..3], data: LONG CARDINAL] = { printval: LONG CARDINAL _ word + bl * 4 + vp * 128; SakuraRT.Put[RQ, NEW[BOOLEAN _ TRUE]]; SakuraRT.Put[Op, NEW[DragonCache.PbusOp _ Fetch]]; SakuraRT.Put[OutData, NEW[DragonCache.PbusType _ [Instruction[vp, bl, word]]]]; DO SakuraRT.GetNew[ClockA, TRUE]; IF NOT NARROW[SakuraRT.Get[Reject], REF BOOLEAN]^ THEN EXIT ENDLOOP; SimIO.WF1[" Fetch started %ld*n", @printval]; SakuraRT.GetNew[ClockB, TRUE]; {SakuraRT.Delay[30]; WITH b: NARROW[SakuraRT.Get[InData], REF DragonCache.PbusType]^ SELECT FROM Data => IF data # b.data THEN ERROR ENDCASE => ERROR; SakuraRT.Put[RQ, NEW[BOOLEAN _ FALSE]]}; SimIO.WF1[" Fetch finished %ld*n", @printval]}; Read: PROC [data: LONG CARDINAL] = { DO SakuraRT.GetNew[ClockA, TRUE]; IF NOT NARROW[SakuraRT.Get[Reject], REF BOOLEAN]^ THEN EXIT ENDLOOP; SakuraRT.GetNew[ClockB, TRUE]; SakuraRT.Delay[30]; WITH b: NARROW[SakuraRT.Get[InData], REF DragonCache.PbusType]^ SELECT FROM Data => IF data # b.data THEN ERROR ENDCASE => ERROR}; {ENABLE {ABORTED => GO TO Aborted}; SakuraRT.Put[RQ, NEW[BOOLEAN _ FALSE]]; SakuraRT.GetNew[ClockB, TRUE]; NULL; SakuraRT.GetNew[ClockB, TRUE]; NULL; Fetch[0, 0, 1]; FetchAndRead[0, 0, 2, 37777777776B]; FetchAndRead[0, 0, 3, 37777777775B]; FetchAndRead[0, 1, 0, 37777777774B]; Read[37777777773B]; SakuraRT.ProcessEnd[]} EXITS Aborted => SakuraRT.AbortAll[]}; END.