-- File: [Indigo]<Sakura>Dragon>DragonProcessorImpl2.sak
-- Dragon processor with random fetch
--  8-Mar-82 12:37:45

DIRECTORY
  DragonCache: TYPE, 
  DragonProcessor: TYPE, 
  RandomCard: TYPE, 
  SakuraRT: TYPE, 
  SimIO: TYPE;

DragonProcessorImpl2: MONITOR
  IMPORTS RandomCard, SakuraRT, SimIO
  EXPORTS DragonProcessor
  
  = BEGIN
  Processor: PUBLIC PROC
       [ClockA, ClockB, Fault, Reject: SakuraRT.Handle, InData: SakuraRT.Handle, 
        Op: SakuraRT.Handle, RQ: SakuraRT.Handle, OutData: SakuraRT.Handle] = {
    Fetch: PROC [loc: CARDINAL] = {
      vp: LONG CARDINAL; 
      bl: INTEGER [0..37B]; 
      word: INTEGER [0..3]; 
      printval: LONG CARDINAL;
      [vp, bl, word] ← SplitAddress[loc]; 
      printval ← word + bl * 4 + vp * 128; 
      SakuraRT.GetNew[ClockB, TRUE];
       {SakuraRT.Put[RQ, NEW[BOOLEAN ← TRUE]]; 
        SakuraRT.Put[Op, NEW[DragonCache.PbusOp ← Fetch]]; 
        SakuraRT.Put[OutData, NEW[DragonCache.PbusType ← [Instruction[vp, bl, word]]]]}; 
      DO SakuraRT.GetNew[ClockA, TRUE];
          IF NOT NARROW[SakuraRT.Get[Reject], REF BOOLEAN]↑ THEN EXIT
         ENDLOOP; 
      SimIO.WF1["  Fetch started %ld*n", @printval]; 
      SakuraRT.GetNew[ClockB, TRUE]; SakuraRT.Put[RQ, NEW[BOOLEAN ← FALSE]]; 
      SimIO.WF1["  Fetch finished %ld*n", @printval]}; 
    
    FetchAndRead: PROC [loc, prevloc: CARDINAL] = {
      vp: LONG CARDINAL; 
      bl: INTEGER [0..37B]; 
      word: INTEGER [0..3]; 
      printval: LONG CARDINAL; 
      data: LONG CARDINAL;
      [vp, bl, word] ← SplitAddress[loc]; 
      printval ← word + bl * 4 + vp * 128; 
      data ← 37777777777B - prevloc; 
      SakuraRT.Put[RQ, NEW[BOOLEAN ← TRUE]]; 
      SakuraRT.Put[Op, NEW[DragonCache.PbusOp ← Fetch]]; 
      SakuraRT.Put[OutData, NEW[DragonCache.PbusType ← [Instruction[vp, bl, word]]]]; 
      DO SakuraRT.GetNew[ClockA, TRUE];
          IF NOT NARROW[SakuraRT.Get[Reject], REF BOOLEAN]↑ THEN EXIT
         ENDLOOP; 
      SimIO.WF1["  Fetch started %ld*n", @printval]; 
      SakuraRT.GetNew[ClockB, TRUE];
       {SakuraRT.Delay[30]; 
        WITH b: NARROW[SakuraRT.Get[InData], REF DragonCache.PbusType]↑ SELECT FROM 
          Data => IF data # b.data THEN ERROR
          ENDCASE => ERROR; 
        SakuraRT.Put[RQ, NEW[BOOLEAN ← FALSE]]}; 
      SimIO.WF1["  Fetch finished %ld*n", @printval]}; 
    
    Read: PROC [prevloc: CARDINAL] = {
      data: LONG CARDINAL;
      data ← 37777777777B - prevloc; 
      DO SakuraRT.GetNew[ClockA, TRUE];
          IF NOT NARROW[SakuraRT.Get[Reject], REF BOOLEAN]↑ THEN EXIT
         ENDLOOP; 
      SakuraRT.GetNew[ClockB, TRUE]; SakuraRT.Delay[30]; 
      WITH b: NARROW[SakuraRT.Get[InData], REF DragonCache.PbusType]↑ SELECT FROM 
        Data => IF data # b.data THEN ERROR
        ENDCASE => ERROR}; 
    
    SplitAddress: PROC [loc: CARDINAL] RETURNS [vp: LONG CARDINAL, 
                                                bl: INTEGER [0..37B], 
                                                word: INTEGER [0..3]] = {
      word ← loc MOD 4; 
      loc ← loc / 4; 
      bl ← loc MOD 40B; 
      vp ← loc / 40B}; 
    
    loc, prevloc: CARDINAL;
    
    {ENABLE {ABORTED => GO TO Aborted};
     SakuraRT.Put[RQ, NEW[BOOLEAN ← FALSE]]; 
     SakuraRT.GetNew[ClockB, TRUE]; NULL; 
     SakuraRT.GetNew[ClockB, TRUE]; NULL; 
     [] ← RandomCard.InitRandom[-1]; 
     prevloc ← RandomCard.Choose[0, 2000]; 
     Fetch[prevloc]; 
     THROUGH [0..300] DO
         loc ← RandomCard.Choose[0, 2000]; 
         FetchAndRead[loc, prevloc]; 
         prevloc ← loc
         ENDLOOP; 
     Read[prevloc]; 
     SimIO.WF0["++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"]; 
     SakuraRT.ProcessEnd[]}
    EXITS
      Aborted => SakuraRT.AbortAll[]};
  
  END.