<Rosemary.DF>> <> <> Library ExamplePrimitives; SRHC: CELL [input< INT[4] ~ "[0..16)", clock<, output> INT[4]] InitData init: [0..15] _ 7 DefaultInitExpr NEW [SRHC.SRHCInitRec _ [13]] | State latched: [0..15] _ 0 Initializer latched _ init Expand temp: INT[4]; Pass: PassBlock[input: input, gate: clock, output: temp]; CEDAR --any old Cedar code may appear here ; Inv: InvertBlock[input: temp, output: output] Eval IF clock THEN latched _ input; output _ IntNot[4, latched]; ENDCELL