FILE: SRHC.rose, from [Indigo]<Rosemary>Rosemary.DF
last changed by Barth, January 4, 1983 10:44 am
Last Edited by: Spreitzer, March 19, 1983 12:19 pm
Library ExamplePrimitives;
SRHC: CELL [input< INT[4] ~ "[0..16)", clock<, output> INT[4]]
InitData
init: [0..15] ← 7
DefaultInitExpr NEW [SRHC.SRHCInitRec ← [13]] |
State
latched: [0..15] ← 0
Initializer
latched ← init
Expand
temp: INT[4];
Pass: PassBlock[input: input, gate: clock, output: temp];
CEDAR
--any old Cedar code may appear here
;
Inv: InvertBlock[input: temp, output: output]
Eval
IF clock THEN latched ← input;
output ← IntNot[4, latched];
ENDCELL