
<<FILE: SRHC.mesa, from [Cherry]<Barth>Dragon>LogicSimulation>Rosemary.DF>>
<<last changed by Barth, January 4, 1983 11:44 am>>
<<Last Edited by: Spreitzer, March 2, 1983 5:26 pm>>

DIRECTORY Rosemary, IntTypes, PassTransistor, Inverter;

SRHC: CEDAR PROGRAM IMPORTS Rosemary, IntTypes =

BEGIN OPEN Rosemary, IntTypes;

SRHCInterfaceRef: TYPE = REF SRHCInterfaceRec;
SRHCInterfaceRec: PUBLIC TYPE = RECORD [
input: Node,
clock: Node,
output: Node];

SRHCIORef: TYPE = REF SRHCIORec;
SRHCIORec: TYPE = MACHINE DEPENDENT RECORD [
fill1(0:0..11): [0..4095],
input(0:12..15): [0..15],
fill2(1:0..14): [0..32767],
clock(1:15..15): BOOLEAN,
fill3(2:0..11): [0..4095],
output(2:12..15): [0..15]];

SRHCInitRef: TYPE = REF SRHCInitRec;
SRHCInitRec: PUBLIC TYPE = RECORD [
init: [0..15] _ 0];

typicalInit: SRHCInitRef _ NEW [SRHCInitRec _ []];

SRHCStateRef: TYPE = REF SRHCStateRec;
SRHCStateRec: TYPE = RECORD [
latched: [0..15]];

SRHCExpand: ExpandProc = {
OPEN NARROW[interfaceNodes, SRHCInterfaceRef], NARROW[initData, SRHCInitRef];
temp: Node _ CreateNode[within: thisCell, name: "temp", type: IntType[4]];
[] _ CreateCell[within: thisCell, instanceName: "Pass", className: "PassTransistor", interfaceNodes: NEW 
[PassTransistor.PassTransistorInterfaceRec _ [input: input, gate: clock, output: temp]]];
[] _ CreateCell[within: thisCell, instanceName: "Inv", className: "Inverter", interfaceNodes: NEW [Inverter.InverterInterfaceRec _ 
[input: temp, output: output]]];
};

SRHCInit: InitProc = {
oldIO: SRHCIORef _ NEW[SRHCIORec];
newIO: SRHCIORef _ NEW[SRHCIORec];
cell.realCellStuff.oldIO _ oldIO;
cell.realCellStuff.newIO _ newIO;
IF leafily THEN
BEGIN
state: SRHCStateRef _ NEW[SRHCStateRec];
cell.realCellStuff.state _ state;
BEGIN
OPEN NARROW[initData, SRHCInitRef], newIO, state;
latched _ init;
END;
END;
};

SRHCEval: EvalProc =
BEGIN
newIO: SRHCIORef _ NARROW[cell.realCellStuff.newIO];
oldIO: SRHCIORef _ NARROW[cell.realCellStuff.oldIO];
oldIO^ _ newIO^;
BEGIN OPEN newIO, NARROW[cell.realCellStuff.state, SRHCStateRef];
IF clock THEN latched _ input;
output _ IntNot[4, latched];
END;
END;


SRHCPorts:Ports _ NEW[PortsRep[3]];
SRHCPorts[0] _ [0, 1, "input", IntType[4], TRUE, FALSE];
SRHCPorts[1] _ [1, 1, "clock", Bit, TRUE, FALSE];
SRHCPorts[2] _ [2, 1, "output", IntType[4], FALSE, TRUE];
RegisterCellClass[className: "SRHC",
expandProc: SRHCExpand,
initProc: SRHCInit,
evalProc: SRHCEval,
ports: SRHCPorts,
interfaceTemplate: NEW [SRHCInterfaceRec _ [
input: NEW [NodeRep _ [name: "input", type: IntType[4]]],
clock: NEW [NodeRep _ [name: "clock", type: NIL]],
output: NEW [NodeRep _ [name: "output", type: IntType[4]]] ]],
ioTemplate: NEW [SRHCIORec]
];

END.