FILE: SRHC.mesa, from [Cherry]<Barth>Dragon>LogicSimulation>Rosemary.DF
last changed by Barth, January 4, 1983 11:44 am
Last Edited by: Spreitzer, March 2, 1983 5:26 pm
DIRECTORY Rosemary, IntTypes, PassTransistor, Inverter;
SRHC: CEDAR PROGRAM IMPORTS Rosemary, IntTypes =
BEGIN OPEN Rosemary, IntTypes;
SRHCInterfaceRef: TYPE = REF SRHCInterfaceRec;
SRHCInterfaceRec:
PUBLIC TYPE =
RECORD [
input: Node,
clock: Node,
output: Node];
SRHCIORef: TYPE = REF SRHCIORec;
SRHCIORec:
TYPE =
MACHINE
DEPENDENT
RECORD [
fill1(0:0..11): [0..4095],
input(0:12..15): [0..15],
fill2(1:0..14): [0..32767],
clock(1:15..15): BOOLEAN,
fill3(2:0..11): [0..4095],
output(2:12..15): [0..15]];
SRHCInitRef: TYPE = REF SRHCInitRec;
SRHCInitRec:
PUBLIC
TYPE =
RECORD [
init: [0..15] ← 0];
typicalInit: SRHCInitRef ← NEW [SRHCInitRec ← []];
SRHCStateRef: TYPE = REF SRHCStateRec;
SRHCStateRec:
TYPE =
RECORD [
latched: [0..15]];
SRHCExpand: ExpandProc = {
OPEN NARROW[interfaceNodes, SRHCInterfaceRef], NARROW[initData, SRHCInitRef];
temp: Node ← CreateNode[within: thisCell, name: "temp", type: IntType[4]];
[] ← CreateCell[within: thisCell, instanceName: "Pass", className: "PassTransistor", interfaceNodes: NEW [PassTransistor.PassTransistorInterfaceRec ← [input: input, gate: clock, output: temp]]];
[] ← CreateCell[within: thisCell, instanceName: "Inv", className: "Inverter", interfaceNodes: NEW [Inverter.InverterInterfaceRec ← [input: temp, output: output]]];
};
SRHCInit: InitProc = {
oldIO: SRHCIORef ← NEW[SRHCIORec];
newIO: SRHCIORef ← NEW[SRHCIORec];
cell.realCellStuff.oldIO ← oldIO;
cell.realCellStuff.newIO ← newIO;
IF leafily
THEN
BEGIN
state: SRHCStateRef ← NEW[SRHCStateRec];
cell.realCellStuff.state ← state;
BEGIN
OPEN NARROW[initData, SRHCInitRef], newIO, state;
latched ← init;
END;
END;
};
SRHCEval: EvalProc =
BEGIN
newIO: SRHCIORef ← NARROW[cell.realCellStuff.newIO];
oldIO: SRHCIORef ← NARROW[cell.realCellStuff.oldIO];
oldIO^ ← newIO^;
BEGIN OPEN newIO, NARROW[cell.realCellStuff.state, SRHCStateRef];
IF clock THEN latched ← input;
output ← IntNot[4, latched];
END;
END;
SRHCPorts:Ports ← NEW[PortsRep[3]];
SRHCPorts[0] ← [0, 1, "input", IntType[4], TRUE, FALSE];
SRHCPorts[1] ← [1, 1, "clock", Bit, TRUE, FALSE];
SRHCPorts[2] ← [2, 1, "output", IntType[4], FALSE, TRUE];
RegisterCellClass[className: "SRHC",
expandProc: SRHCExpand,
initProc: SRHCInit,
evalProc: SRHCEval,
ports: SRHCPorts,
interfaceTemplate: NEW [SRHCInterfaceRec ← [
input: NEW [NodeRep ← [name: "input", type: IntType[4]]],
clock: NEW [NodeRep ← [name: "clock", type: NIL]],
output: NEW [NodeRep ← [name: "output", type: IntType[4]]] ]],
ioTemplate: NEW [SRHCIORec]
];
END.