
<<NBitSR.Mesa>>
<<Last Edited by: Spreitzer, March 2, 1983 5:05 pm>>

    DIRECTORY IO, Rosemary, RoseClocks, IntTypes, SRWC;

    NBitSR: CEDAR PROGRAM IMPORTS IO, Rosemary, RoseClocks, IntTypes =

    BEGIN OPEN Rosemary, IntTypes;

        NBitSRInterfaceRef: TYPE = REF NBitSRInterfaceRec;
        NBitSRInterfaceRec: PUBLIC TYPE = RECORD [
            input, output, phi1, phi2: Node];

        NBitSRIORef: TYPE = REF NBitSRIORec;
        NBitSRIORec: TYPE = MACHINE DEPENDENT RECORD [
            fill1(0:0..14): [0..32767],
            phi1(0:15..15): BOOLEAN,
            fill2(1:0..14): [0..32767],
            phi2(1:15..15): BOOLEAN,
            fill3(2:0..11): [0..4095],
            input(2:12..15): [0..15],
            fill4(3:0..11): [0..4095],
            output(3:12..15): [0..15]];

        NBitSRInitRef: TYPE = REF NBitSRInitRec;
        NBitSRInitRec: TYPE = RECORD [n: CARDINAL];

        InitFor: PROC [n: CARDINAL] RETURNS [NBitSRInitRef] =
            {RETURN [NEW [NBitSRInitRec _ [n]]]};

        NBitSRExpand: ExpandProc = {
            OPEN NARROW[interfaceNodes, NBitSRInterfaceRef], NARROW[initData, NBitSRInitRef];
            prev, next: Node;
            next _ input;
            FOR i: CARDINAL IN [0..n) DO
                prev _ next;
                next _ IF n = i+1 THEN output ELSE CreateNode[within: thisCell, name: IO.PutFR["node%g", IO.card[i+1]], type: IntType[4]];
                [] _ CreateCell[within: thisCell, instanceName: IO.PutFR["SRWC%g", IO.card[i]], className: "SRWC", interfaceNodes: NEW 
                [SRWC.SRWCInterfaceRec _ [input: prev, phi1: phi1, phi2: phi2, output: next]]];
                ENDLOOP;
            };

        TopNBitSRExpand: ExpandProc = {
            front: Node _ CreateNode[within: thisCell, name: "front", type: IntType[4]];
            back: Node _ CreateNode[within: thisCell, name: "back", type: IntType[4]];
            pha: Node _ CreateNode[within: thisCell, name: "PhaseA"];
            phb: Node _ CreateNode[within: thisCell, name: "clk2"];
            dull1: Node _ CreateNode[within: thisCell, name: "dullOne"];
            prompt: Node _ CreateNode[within: thisCell, name: "praumpt"];

            cg: Cell;

            [] _ CreateCell[within: thisCell, instanceName: "DuLL1", className: "Dullard", interfaceNodes: NEW [RoseClocks.DullardInterfaceRec 
            _ [dull1]]];

            cg _ CreateCell[within: thisCell, instanceName: "clkGen", className: "DaisyClock", interfaceNodes: NEW 
            [RoseClocks.DaisyClockInterfaceRec _ [PhaseA: pha, PhaseB: phb, daisyIn: dull1, daisyOut: prompt]], initData: 
            RoseClocks.Init[]];

            [] _ CreateCell[within: thisCell, instanceName: "cntr", className: "Counter", interfaceNodes: NEW [CounterInterfaceRec _ [prompt: 
            prompt, count: front]]];

            [] _ CreateCell[within: thisCell, instanceName: "shifter", className: "NBitSR", interfaceNodes: NEW [NBitSRInterfaceRec _ [input: 
            front, output: back, phi1: pha, phi2: phb]], initData: initData];

            SetDriver[within: thisCell, driver: cg];
            };

        NBitSRInit: InitProc = {
            cell.realCellStuff.oldIO _ NEW[NBitSRIORec];
            cell.realCellStuff.newIO _ NEW[NBitSRIORec];
            };

        TopNBitSRInit: InitProc = {
            cell.realCellStuff.oldIO _ cell.realCellStuff.newIO _ NIL};

        CounterInterfaceRef: TYPE = REF CounterInterfaceRec;
        CounterInterfaceRec: TYPE = RECORD [prompt, count: Node];

        CounterIORef: TYPE = REF CounterIORec;
        CounterIORec: TYPE = MACHINE DEPENDENT RECORD [
            fill1(0:0..14): [0..32768),
            p(0:15..15): BOOLEAN,
            fill2(1:0..11): [0..4096),
            n(1:12..15): [0..16)];

        CounterInit: InitProc = {
            cell.realCellStuff.newIO _ NEW [CounterIORec];
            cell.realCellStuff.oldIO _ NEW [CounterIORec];
            };

        CounterEval: EvalProc = {
            new: CounterIORef _ NARROW[cell.realCellStuff.newIO];
            old: CounterIORef _ NARROW[cell.realCellStuff.oldIO];
            old^ _ new^;
            new.n _ (1 + new.n) MOD 16;
            };

    Setup: PROC = {
        NBitSRPorts:Ports _ NEW[PortsRep[4]];
        CounterPorts: Ports _ NEW [PortsRep[2]];
        TopPorts: Ports _ NEW [PortsRep[0]];

        NBitSRPorts[0] _ [0, 1, "phi1", Bit, TRUE, FALSE];
        NBitSRPorts[1] _ [1, 1, "phi2", Bit, TRUE, FALSE];
        NBitSRPorts[2] _ [2, 1, "input", IntType[4], TRUE, FALSE];
        NBitSRPorts[3] _ [3, 1, "output", IntType[4], FALSE, TRUE];

        CounterPorts[0] _ [0, 1, "prompt", Bit, TRUE, FALSE];
        CounterPorts[1] _ [1, 1, "count", IntType[4], FALSE, TRUE];

        RegisterCellClass[className: "NBitSR",
            expandProc: NBitSRExpand,
            initProc: NBitSRInit,
            evalProc: NIL,
            ports: NBitSRPorts,
            interfaceTemplate: NEW [NBitSRInterfaceRec _ [
                input: NEW [NodeRep _ [name: "input", type: IntType[4]]],
                phi1: NEW [NodeRep _ [name: "phi1"]],
                phi2: NEW [NodeRep _ [name: "phi2"]],
                output: NEW [NodeRep _ [name: "output", type: IntType[4]]] ]],
            ioTemplate: NEW [NBitSRIORec]
            ];

        RegisterCellClass[className: "Counter",
            expandProc: NIL,
            initProc: CounterInit,
            evalProc: CounterEval,
            ports: CounterPorts];

        RegisterCellClass[className: "TopNBitSR",
            expandProc: TopNBitSRExpand,
            initProc: TopNBitSRInit,
            evalProc: NIL,
            ports: TopPorts];
        };

    Setup[];

    END.