LichenOps:
CEDAR
DEFINITIONS =
BEGIN OPEN LichenDataStructure;
NotNormal: ERROR [msg: ROPE];
NotComparable: ERROR [msg: ROPE];
Source: TYPE = RECORD [stream: IO.STREAM ← NIL, name: ROPE ← NIL];
AssertionOp: TYPE = {ignore, report, check, establish};
MerelyCheckableAssertionOp: TYPE = AssertionOp [ignore .. check];
FailableAssertionOp: TYPE = AssertionOp [report .. check];
AssertionFamily: TYPE = {normal, comparable};
DimName: ARRAY Dim OF ROPE;
EOName: ARRAY EO OF ROPE;
EndName: ARRAY End OF ROPE;
NamingNames: PROC [naming: Naming] RETURNS [names: Names];
EnumerateNames: PROC [names: Names, consume: PROC [name: ROPE, class: ATOM--UNION[$designed, $unknown, $progged]--]];
RopeListIncludes: PROC [rl: RopeList, r: ROPE] RETURNS [found: BOOL];
NamesInclude: PROC [names: Names, name: ROPE] RETURNS [BOOL];
FindPort: PROC [ports: PortS, name: ROPE] RETURNS [portIndex: NAT];
notFound: NAT = LAST[NAT];
Insert: PROC [st: SymbolTable, names: Names, val: REF ANY];
Delete: PROC [st: SymbolTable, names: Names, val: REF ANY];
Lookup: PROC [st: SymbolTable, key: ROPE] RETURNS [val: REF ANY];
AntiAlias: PROC [ra: REF ANY] RETURNS [val: REF ANY];
PickAName: PROC [names: Names] RETURNS [name: ROPE];
GlobalPortName: PROC [ct: CellType, portIndex: PortIndex] RETURNS [r: ROPE];
GlobalCellTypeName: PROC [ct: CellType] RETURNS [r: ROPE];
GlobalVertexName: PROC [v: Vertex] RETURNS [r: ROPE];
GlobalName:
PROC [ra:
REF
ANY, soFar: Naming ← [
NIL,
NIL]]
RETURNS [
ROPE];
Naming: TYPE = RECORD [first: ROPE, designed, unknown, progged: RopeList ← NIL];
GetArrayPort: PROC [a: Array, index: ArrayIndex, eltPortIndex: PortIndex] RETURNS [arrayPortIndex: PortIndex];
ToVertex: PROC [context, ra: REF ANY] RETURNS [v: Vertex];
ToType: PROC [design: Design, ra: REF ANY] RETURNS [type: CellType];
KeepAll: PROC [REF ANY] RETURNS [BOOL];
Warn: PROC [source: Source, format: ROPE, v1, v2, v3, v4, v5: IO.Value ← [null[]]];
Err: PROC [source: Source, format: ROPE, v1, v2, v3, v4, v5: IO.Value ← [null[]]];
Log: PROC [format: ROPE, v1, v2, v3, v4, v5: IO.Value ← [null[]]];
Fail: PROC [af: AssertionFamily, ao: FailableAssertionOp, format: ROPE, v1, v2, v3, v4, v5: IO.Value ← [null[]]];
FlushLog: PROC;
WriteAll: PROC [when: ROPE, a, b: CellType, hashTable: HashTable];
EnsureAllIn: PROC [design: Design];
EnsurePorts: PROC [CellType];
EnsureParts: PROC [CellType];
ExpansionKnown:
PROC [CellType]
RETURNS [
BOOL];
Ask only after ensuring parts.
GetInternalStyle:
PROC [CellType]
RETURNS [InternalStyle];
InternalStyle: TYPE = {graph, array};
NoteChange: PROC [CellType];
CheckType: PROC [ct: CellType, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, ignoreInstances: BOOL ← FALSE];
CheckPerType:
PROC [key, val:
REF
ANY]
RETURNS [quit:
BOOL];
key is the CellType.
val is LIST[norm, comparable, ignoreInstances].
CheckParentType: PROC [key, val: REF ANY] RETURNS [quit: BOOL];
AddCellType: PROC [ct: CellType];
AddVertex: PROC [v: Vertex];
DeleteVertex: PROC [v: Vertex];
Connect: PROC [cv, nv: Vertex, portIndex: PortIndex];
RemoveEdge: PROC [Edge];
AddWorld: PROC [ct: CellType];
IsMirror: PROC [v: Vertex] RETURNS [isMirror: BOOL];
UnlinkInstance: PROC [v: Vertex];
LinkInstance: PROC [v: Vertex];
AddNames: PROC [ra: REF ANY--UNION[Vertex, CellType]--, names: Names];
MergeNets: PROC [net1, net2: Vertex] RETURNS [merged, doomed: Vertex];
NewDetailedPorting: PROC [shape: ARRAY Dim OF Range] RETURNS [dp: DetailedPorting];
CompareGraphs: PROC [a, b: CellType, seeAllInstanceNames: BOOL] RETURNS [equiv: BOOL];
END.