
    <<Format.Tioga>>
<<Last Edited by: Spreitzer, June 17, 1985 5:40:26 pm PDT>>
Circuit Descriptions
Design Descriptions
    A design description consists of a number of files.  There is one file for each cell type, and one file to tie them all together.  
    The file that ties them all together is a DF file (so that it can be used to transport and keep track of all the other files).
    These DF files may import cell types from other designs.  This is done with the DF-file import construct.  To enable this, all 
    DF-files should export all their contents.
    In the DF file, stylized comments can give information beyond the scope of the bare DF-file definition.  The stylized comments 
    begin with a double dash and continue with an assertion in LISP syntax.  Here are some kinds of assertions that are likely to 
    be popular:

        CellTypeName: (CellType cellTypeName:ID CellTypeNameAssertion*)
            The following file contains the information about the named cell type.  The following kinds of assertions are likely to be popular:

                WhoGen: (G namer:Namer)
                Namer: D | P
                    This says who came up with the name.  "D" means a designer, "P" means a program.  The reason for this is that program-generated 
                    names sometimes significantly less meaningful than user-generated names.

                Aliases: (A Alias*)
                Alias: (ID NameAssertion*)
                    This introduces alternate names.  WhoGens are possible NameAssertions.

Example Design Description
    Here is an example, wherein the design consists of two cell type descriptions: one for a shift-register half-cell, and one for a 
    shift-register whole-cell (with an import thrown in just for fun):

        -- Shifting.DF written by Rosemary structure capturer at August 18, 1984 2:56:17 pm PDT

        Exports [Indigo]<Rosemary>2.6>Shifting>
          Shifting.DF                                07-Aug-84 15:02:15 PDT
        -- (CellType "Shift Register Whole Cell" (G D))
          SRWC.cell                                07-Aug-84 14:58:25 PDT
        -- (CellType "Shift Register Half Cell")
          SRHC.cell                                07-Aug-84 14:58:26 PDT

        Exports Imports [Foo]<Bar>Gronk>Zot.DF Of 29-Feb-83 23:45:67 PST
            Using [Glork.cell]
Cell Type Descriptions
    A description of a cell type consists of a sequence of assertions, in LISP syntax.  One file per cell type, and one cell type per 
    file.
    The assertions about a cell type are divided into two groups: public and private.  In a file describing a cell type, all the public 
    assertions come first, then a delimiting assertion, then all the private assertions.  The delimiting assertion is 
    "(PrivateFollows)".
    There is no fixed ordering among the kinds of assertions.  However, defining assertions should come before referencing ones.
    The set of possible assertions is open-ended.  Here follows a list of assertions that are expected to be popular:

        CreatingUser: (CreatingUser userName:ID)
        CreationTime: (CreationTime Time)
        CreationSite: (CreationSite ID)
            A way to say who really created this file, and when and where.

        VersionSpec: (Version version:Version)
            A way to give a version stamp.

        DeriverSpec: (DerivingProgram derivingProcName:ID version:Version)
            If this file has been automatically derived by a program, the program can be identified by such an assertion.

        SourceSpec: (Source sourceName:ID version:Version)
            If this file has been automatically derived from some other files, they can be specified with source specs.

        CellTypeName: (CellTypeName celltypeName:ID CellTypeNameAssertion*)
            This gives a name for this cell type.  This information should be redundant with that in the design DF file.

        CellTypeEquivalenceClass: (EC relation:ID equivClass:ID)
            This specifies the equivalence class of the cell type, as determined by the given relation (which, of course, must be an 
            equivalence relation).  The cell types in an equivalence class may be interchanged without "significant" effect, where 
            "significant" means noticed by the given relation.  For example, two buffers that differ only in some transistor sizes 
            might be in the same equivalence class under the "equal connectivity" relation.

        PortsSpec: (Ports PortSpec*)
        PortSpec: (portName:ID PortAssertion*)
            A port is the means of communication between the nets inside a cell and the nets outside.  An internal net is inaccessible outside 
            (i.e., cannot be connected to) unless it is connected to a port.  All that must be given for a port is its name.  
            Again, the set of possible other assertions is open-ended.  Here are some that are likely to be popular:

                PortEquiv: (EC relation:ID equivClass:ID)
                    This specifies the equivalence class of the port, as determined by the named relation.  The ports in an equivalence class may be 
                    interchanged without "significant" effect ("a significantly different from b" means "NOT R(a,b)", where R is 
                    the given relation).  For example, the inputs of an NMOS NOR gate might all be in the same equivalence class 
                    for the connectivity relation, saying that connecting to any one of them is as good as another.

                PortDirection: (Direction)
                Direction: IN | OUT | BIDIR
                    This describes the information flow through the port.

                WhoGen: as above.
                Aliases: as above.

        PortNet: (PN portName:ID netName:ID)
            This specifies what net a port is connected to.

        NetSpec: (N netName:ID NetAssertion*)
            This identifies a net.  Here are some assertions likely to be popular:

                WhoGen: as above.
                Aliases: as above.

        CellInstance: (CI instanceName:ID typeName:ID CellInstanceAssertion*)
            This identifies a cell instance.  Here are some assertions about cell instances that are likely to be popular:

                CellInstanceConnections: (CIC CellInstanceConnection*)
                CellInstanceConnection: (portName:ID netName:ID)
                    This says how a cell instance is connected up to its surroundings.

                WhoGen: as above.
                Aliases: As above.

        Taciturnity: (InsidesUnspecified)
            This says there is nothing being said about the insides of this kind of cell.
Example Cell Type Description
    Here is an example, describing a shift-register whole-cell made out of two shift-register half-cells:

        (CreatingUser "Spreitzer.pa")
        (CreationTime "August 18, 1984 2:29:38 pm PDT")
        (CreationSite "Xerox PARC CSL Sea-Horse")
        (Version "7aa0d8300a60")
        (DerivingProgram "Rosemary" "000049fe9d23")
        (Source "SRWC.BCD" "873b4ae19d59")
        (Source "SRWC.RosePorts" "3c4a893a2d11")
        (CellTypeName "Shift Register Whole Cell" (G D))

        (Ports
            ("in" (EC "in" "connectivity"))
            ("ph1")
            ("ph2")
            ("out"))
        (PrivateFollows)
        (N "in")
        (N "ph1")
        (N "ph2")
        (N "out")
        (N "mid")
        (PN "in" "in")
        (PN "ph1" "ph1")
        (PN "ph2" "ph2")
        (PN "out" "out")
        (CI "first" "Shift Register Half Cell"
            (CIC
                ("in" "in")
                ("clock" "ph1")
                ("out" "mid")))
        (CI "second" "Shift Register Half Cell"
            (CIC
                ("in" "mid")
                ("clock" "ph2")
                ("out" "out")))