.extDoc.Tioga

Last Edited by: Spreitzer, June 5, 1985 11:17:01 am PDT

Printed 4/27/85 1

EXT(5) UNIX Programmer's Manual EXT(5)

NAME
ext - format of .ext files produced by Magic's hierarchical
extractor

DESCRIPTION
Magic's extractor produces a .ext file for each cell in a
hierarchical design. The .ext file for cell name is
name.ext. This file contains three kinds of information:
environmental information (scaling, timestamps, etc), the
extracted circuit corresponding to the mask geometry of cell
name, and the connections between this mask geometry and the
subcells of name.

A .ext file consists of a series of lines, each of which
begins with a keyword. The keyword beginning a line deter-
mines how the remainder of the line is interpreted. The
following set of keywords define the environmental informa-
tion:

tech techname
Identifies the technology of cell name as techname,
e.g, nmos, cmos.

timestamp time
Identifies the time when cell name was last modified.
The value time is the time stored by Unix, i.e, seconds
since 00:00 GMT January 1, 1970. Note that this is not
the time cell was extracted, but rather the timestamp
value stored in the .mag file. The incremental extrac-
tor compares the timestamp in each .ext file with the
timestamp in each .mag file in a design; if they
differ, that cell is re-extracted.

version version
Identifies the version of the extractor used to write
name.ext. This information is currently unused, but
may be used by future versions to allow compatibility
with old format .ext files.

scale rscale cscale lscale
Sets the scale to be used in interpreting resistance,
capacitance, and linear dimension values in the
remainder of the .ext file. Each resistance value must
be multiplied by rscale to give the real resistance in
milliohms. Each capacitance value must be multiplied
by cscale to give the real capacitance in attofarads.
Each linear dimension (e.g, width, height, transform
coordinates) must be multiplied by lscale to give the
real linear dimension in centimicrons. At most one
scale line may appear in a .ext file. If none appears,
all of rscale, cscale, and lscale default to 1.

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EXT(5) UNIX Programmer's Manual EXT(5)

The following keywords define the circuit formed by the mask
information in cell name. This circuit is extracted
independently of any subcells; its connections to subcells
are handled by the keywords in the section after this one.

node name R C x y [attrs]
Defines an electrical node in name. This node is
referred to by the name name in subsequent equiv lines,
connections to the terminals of transistors in fet
lines, and hierarchical connections or adjustments
using merge or adjust. The node has a total capaci-
tance to ground of C attofarads, and a lumped resis-
tance of R milliohms. For purposes of going back from
the node name to the geometry defining the node, (x,y)
is the coordinate of a point inside the node. If there
were any attribute labels attached to geometry in this
node, they appear in the comma-separated list attrs.

equiv node1 node2
Defines two node names in cell name as being
equivalent: node1 and node2. In a collection of node
names related by equiv lines, exactly one must be
defined by a node line described above.

fet type xl yl xh yh area perim sub GATE T1 T2 ...
Defines a transistor in name. The kind of transistor
is type, a string that comes from the technology file
and is intended to have meaning to simulation programs.
The coordinates of a square entirely contained in the
gate region of the transistor are (xl, yl) for its
lower-left and (xh, yh) for its upper-right. All four
coordinates are in the name's coordinate space, and are
subject to scaling as described in scale below. The
gate region of the transistor has area area square cen-
timicrons and perimeter perim centimicrons. The sub-
strate of the transistor is connected to node sub,
which is defined in the technology file for this type
of transistor.

The remainder of a fet line consists of a series of
triples: GATE, T1, .... Each describes one of the ter-
minals of the transistor; the first describes the gate,
and the remainder describe the transistor's non-gate
terminals (e.g, source and drain). Each triple con-
sists of the name of a node connecting to that termi-
nal, a terminal length, and an attribute list. The
terminal length is in centimicrons; it is the length of
that segment of the channel perimeter connecting to
adjacent material, such as polysilicon for the gate or
diffusion for a source or drain.

The attribute list is either the single token ``0'',

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EXT(5) UNIX Programmer's Manual EXT(5)

meaning no attributes, or a comma-separated list of
strings. The strings in the attribute list come from
labels attached to the transistor. Any label ending in
the character ``^'' is considered a gate attribute and
appears on the gate's attribute list. Gate attributes
may lie either along the border of a channel or in its
interior. Any label ending in the character ``$'' is
considered a non-gate attribute, and appears on the
list of the terminal along which it lies. Non-gate
attributes may only lie on the border of the channel.

The keywords in this last section describe the subcells used
by name, and how it makes connections to and between them.

use def use-id TRANSFORM
Specifies that cell def with instance identifier use-id
is a subcell of cell name. If cell def is arrayed,
then use-id will be followed by two bracketed subscript
ranges of the form: [lo,hi,sep]. The first range is
for x, and the second for y. The subscripts for a
given dimension are lo through hi inclusive, and the
separation between adjacent array elements is sep cen-
timicrons.

TRANSFORM is a set of six integers that describe how
coordinates in def are to be transformed to coordinates
in the parent name. It is used by ext2sim(1) in
transforming transistor locations to coordinates in the
root of a design. The six integers of TRANSFORM
(ta, tb, tc, td, te, tf) are interpreted as components
in the following transformation matrix, by which all
coordinates in def are post-multiplied to get coordi-
nates in name:

ta td 0
tb te 0
tc tf 1

merge path1 path2 R C
Used to specify a connection between two subcells, or
between a subcell and mask information of name. Both
path1 and path2 are hierarchical node names. To refer
to a node in cell name itself, its pathname is just its
node name. To refer to a node in a subcell of name,
its pathname consists of the use-id of the subcell (as
it appeared in a use line above), followed by a
slash (/), followed by the node name in the subcell.
For example, if name contains subcell sub with use
identifier sub-id, and sub contains node n, the full
pathname of node n relative to name will be sub-id/n.

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Connections between adjacent elements of an array are
represented using a special syntax that takes advantage of
the regularity of arrays. A use-id in a path may optionally
be followed by a range of the form [lo:hi] (before the fol-
lowing slash). Such a use-id is interpreted as the elements
lo through hi inclusive of a one-dimensional array. An ele-
ment of a two-dimensional array may be subscripted with two
such ranges: first the y range, then the x range.

Whenever one path in a merge line contains such a subscript
range, the other must contain one of comparable size. For
example,

connect sub-id[1:4,2:8]/a sub-id[2:5,1:7]/b

is acceptable because the range 1:4 is the same size as 2:5,
and the range 2:8 is the same size as 1:7.

When a connection occurs between nodes in different cells,
it may be that some resistance and capacitance has been
recorded redundantly. For example, polysilicon in one cell
may overlap polysilicon in another, so the capacitance to
substrate will have been recorded twice. The values R and C
in a merge line provide a way of compensating for such over-
lap. The value R milliohms (usually negative) is added to
the sum of the resistances of nodes path1 and path2 to give
the resistance of the aggregate node. The value C
attofarads (also usually negative) is added to the sum of
the capacitances (to substrate) of nodes path1 and path2 to
give the capacitance of the aggregate node.

adjust path R C
Provides a way of adjusting the resistance of the node
named by the hierarchical path, without specifying a
connection. R milliohms and C attofarads are added to
the resistance and capacitance respectively of node
path.

cap node1 node2 C
Defines a capacitor between the nodes node1 and node2,
with capacitance C. This construct is used to specify
both internodal capacitance within a single cell and
between cells.

AUTHOR
Walter Scott

SEE ALSO
ext2sim(1), magic(1)

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