(CellTypeName "WeakNonInvertingLatch")
(Ports
	("Clock" (G D))
	("D" (G D))
	("Q" (G D))
	("Vdd" (G D))
	("Gnd" (G D))
	("BiasMinus" (G D)))
(PrivateFollows)
(N "BiasMinus" (G D))
(N "Clock" (G D))
(N "D" (G D))
(N "Gnd" (G D))
(N "Q" (G D))
(N "Vdd" (G D))
(N "t1" (G D))
(N "t2" (G D))
(PN "Clock" "Clock")
(PN "D" "D")
(PN "Q" "Q")
(PN "Vdd" "Vdd")
(PN "Gnd" "Gnd")
(PN "BiasMinus" "BiasMinus")
(CI "bias" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: TRUE, biased: TRUE, offStrength: driveWeak]" (G D) (CIC
	("gate" "BiasMinus")
	("ch1" "Gnd")
	("ch2" "t1")))
(CI "latch" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "Clock")
	("ch1" "D")
	("ch2" "Q")))
(CI "pd1" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "Q")
	("ch1" "Gnd")
	("ch2" "t2")))
(CI "pd2" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "t2")
	("ch1" "t1")
	("ch2" "Q")))
(CI "pu1" "Transistor[strength: drive, positive: FALSE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "Q")
	("ch1" "Vdd")
	("ch2" "t2")))
(CI "pu2" "Transistor[strength: driveWeak, positive: FALSE, mode: Enhancement, unidirectional: TRUE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "t2")
	("ch1" "Vdd")
	("ch2" "Q")))