(CellTypeName "BiasGen")
(Ports
	("Vdd" (G D))
	("Gnd" (G D))
	("BiasMinus" (G D))
	("BiasPlus" (G D)))
(PrivateFollows)
(N "Gnd" (G D))
(N "Vdd" (G D))
(N "bn" (G D) (A "BiasMinus" (G P)))
(N "bp" (G D) (A "BiasPlus" (G P)))
(PN "Vdd" "Vdd")
(PN "Gnd" "Gnd")
(PN "BiasMinus" "bn")
(PN "BiasPlus" "bp")
(CI "t1" "Transistor[strength: drive, positive: FALSE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "bp")
	("ch1" "Vdd")
	("ch2" "bp")))
(CI "t2" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "Vdd")
	("ch1" "Gnd")
	("ch2" "bp")))
(CI "t3" "Transistor[strength: drive, positive: FALSE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "Gnd")
	("ch1" "Vdd")
	("ch2" "bn")))
(CI "t4" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "bn")
	("ch1" "Gnd")
	("ch2" "bn")))