(CellTypeName "PreGrantDrive")
(Ports
	("nlRequest" (G D))
	("PhA" (G D))
	("PhB" (G D))
	("nPreGrant" (G D))
	("NoGrant" (G D))
	("ShifterOut" (G D))
	("Vdd" (G D))
	("Gnd" (G D))
	("BiasMinus" (G D)))
(PrivateFollows)
(N "BiasMinus" (G D))
(N "Gnd" (G D))
(N "NoGrant" (G D))
(N "PhA" (G D))
(N "PhB" (G D))
(N "PreGrant" (G D))
(N "ShifterOut" (G D))
(N "Vdd" (G D))
(N "nPreGrant" (G D))
(N "nlRequest" (G D))
(N "t1" (G D))
(N "t2" (G D))
(N "t3" (G D))
(PN "nlRequest" "nlRequest")
(PN "PhA" "PhA")
(PN "PhB" "PhB")
(PN "nPreGrant" "nPreGrant")
(PN "NoGrant" "NoGrant")
(PN "ShifterOut" "ShifterOut")
(PN "Vdd" "Vdd")
(PN "Gnd" "Gnd")
(PN "BiasMinus" "BiasMinus")
(CI "i1" "Inverter" (G D) (CIC
	("in" "ShifterOut")
	("out" "t2")
	("Vdd" "Vdd")
	("Gnd" "Gnd")))
(CI "l1" "DualRailLatch" (G D) (CIC
	("Clock" "PhB")
	("D" "t2")
	("Q" "nPreGrant")
	("nQ" "PreGrant")
	("Vdd" "Vdd")
	("Gnd" "Gnd")
	("BiasMinus" "BiasMinus")))
(CI "n1" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "nlRequest")
	("ch1" "t1")
	("ch2" "ShifterOut")))
(CI "n2" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "PhB")
	("ch1" "Gnd")
	("ch2" "t1")))
(CI "n3" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "PhA")
	("ch1" "t3")
	("ch2" "NoGrant")))
(CI "n4" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: FALSE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "PreGrant")
	("ch1" "Gnd")
	("ch2" "t3")))