DIRECTORY Basics, CompareDataStructure, DFUtilities, FS, IO, List, OrderedSymbolTableRef, Rope, TextReplace, ViewerIO; CompareTransforms: CEDAR DEFINITIONS = BEGIN OPEN CompareDataStructure; --Not YET implemented-- nyet: ERROR; Error: ERROR [format: ROPE, v1, v2, v3, v4, v5: IO.Value _ [null[]]]; RopeMap: TYPE = TextReplace.RopeMap; CellTypeS: TYPE = REF CellTypeSeq; CellTypeSeq: TYPE = RECORD [SEQUENCE length: NAT OF CellType]; VertexSList: TYPE = LIST OF VertexS; VertexSS: TYPE = REF VertexSSeq; VertexSSeq: TYPE = RECORD [SEQUENCE length: NAT OF VertexS]; VertexS: TYPE = REF VertexSeq; VertexSeq: TYPE = RECORD [SEQUENCE length: NAT OF Vertex]; NamesSS: TYPE = REF NamesSSeq; NamesSSeq: TYPE = RECORD [SEQUENCE length: NAT OF NamesS]; NamesS: TYPE = REF NamesSeq; NamesSeq: TYPE = RECORD [SEQUENCE length: NAT OF Names]; BoolS: TYPE = REF BoolSeq; BoolSeq: TYPE = RECORD [SEQUENCE length: CARDINAL OF BOOL]; EdgeList: TYPE = LIST OF Edge; NewPortNamer: TYPE = RECORD [ NameNewPort: PROC [ data: REF ANY, first: BOOL, ct: CellType, ports: PortS, portIndex: PortIndex, oldNet: Vertex, oldConnections: EdgeList] RETURNS [names: Names, equivClass: EquivClass], data: REF ANY]; Renamer: TYPE = RECORD [ data: REF ANY, Rename: PROC [data: REF ANY, oldNames: Names, oldEquiv: EquivClass] RETURNS [newNames: Names, newEquiv: EquivClass] ]; Mapper: TYPE = REF MapperRep; MapperRep: TYPE = RECORD [ map: PROC [data, domain: REF ANY] RETURNS [range: REF ANY], data: REF ANY]; Bag: TYPE = REF BagRep; BagRep: TYPE = RECORD [ data: REF ANY, Enumerate: PROC [context, data: REF ANY, to: PROC [REF ANY]]]; Differentiate: PUBLIC PROC [design: Design, newNames: Names, instances: REF ANY] RETURNS [newCT: CellType]; Undifferentiate: PROC [design: Design, toTypeA, fromTypes: REF ANY] RETURNS [changed: VertexList]; NewEmptyCellType: PROC [design: Design, names: Names] RETURNS [cellType: CellType]; CreateEmpty: PROC [design: Design, childNames: Names, childType, parentType: CellType] RETURNS [child: Vertex]; DeleteEmpty: PROC [design: Design, child: Vertex] RETURNS [parentType: CellType]; RenameVertices: PROC [design: Design, parentA, vertices: REF ANY, renamer: Renamer]; RenamePorts: PROC [design: Design, typeA: REF ANY, renamer: Renamer]; RenameCellType: PROC [design: Design, typeA: REF ANY, renamer: Renamer]; RenameTypes: PROC [design: Design, typesA: REF ANY, renamer: Renamer]; RenameAll: PROC [design: Design, renamer: Renamer]; LowerChildren: PROC [design: Design, childTypeA: REF ANY, gcNamesl: NamesList, sibber: Mapper--child => siblings--, newPortNamer: NewPortNamer] RETURNS [gcs: VertexS, children: VertexList]; RaiseGrandchildren: PROC [design: Design, gcsA: REF ANY, newPortNamer: NewPortNamer] RETURNS [newChildrens: VertexSList]; ExpandVertex: PROC [design: Design, childA: REF ANY]; ExpandChildren: PROC [design: Design, parentTypeA: REF ANY, flatten: BOOL _ FALSE]; Group: PROC [design: Design, parentTypeA, childrenA: REF ANY, childNames, childTypeNames: Names, newPortNamer: NewPortNamer] RETURNS [newChild: Vertex, newGrandchildren: VertexS]; NameNewPortFromAnyOldPort: PROC [ data: REF ANY, first: BOOL, ct: CellType, ports: PortS, portIndex: PortIndex, oldNet: Vertex, oldConnections: EdgeList] RETURNS [names: Names, equivClass: EquivClass]; NameNewPortFromAnyOldPortInstance: PROC [ data: REF ANY, first: BOOL, ct: CellType, ports: PortS, portIndex: PortIndex, oldNet: Vertex, oldConnections: EdgeList] RETURNS [names: Names, equivClass: EquivClass]; NameNewPortFromOldNet: PROC [ data: REF ANY, first: BOOL, ct: CellType, ports: PortS, portIndex: PortIndex, oldNet: Vertex, oldConnections: EdgeList] RETURNS [names: Names, equivClass: EquivClass]; DontNameNewPort: PROC [ data: REF ANY, first: BOOL, ct: CellType, ports: PortS, portIndex: PortIndex, oldNet: Vertex, oldConnections: EdgeList] RETURNS [names: Names, equivClass: EquivClass]; NamesListToSeq: PROC [l: NamesList] RETURNS [s: NamesS]; ListNames: PROC [vertexs: VertexS] RETURNS [nl: NamesList]; VVSMapFromTIIlNames: PROC [design: Design, l: TIIlNamesList] RETURNS [m: Mapper]; TIIlNamesList: TYPE = LIST OF TIIlNames; TIIlNames: TYPE = RECORD [typeName, v1Name: ROPE, v2Names: LORA]; TIINamesList: TYPE = LIST OF TIINames; TIINames: TYPE = RECORD [typeName, v1Name, v2Name: ROPE]; OneMap: PROC [from, to: REF ANY] RETURNS [mapper: Mapper]; FavorSimpleNames: PROC [data: REF ANY, oldNames: Names, oldEquiv: EquivClass] RETURNS [newNames: Names, newEquiv: EquivClass]; ReNameByName: PROC [rm: RopeMap] RETURNS [Renamer]; MapRopePairs: PROC [pairs: RopePairList] RETURNS [rm: RopeMap]; RopePairList: TYPE = LIST OF RECORD [old, new: ROPE]; RenamePairs: PROC [pairs: RopePairList] RETURNS [Renamer]; SetNames: PROC [names: Names _ useOldNames, equivClass: EquivClass _ useOldEquivClass] RETURNS [Renamer]; useOldNames: Names; useOldEquivClass: EquivClass; all: REF ANY; ChildrenOfType: PROC [design: Design, parentTypeA, childTypeA: REF ANY] RETURNS [bag: Bag]; ImplicitChildrenOfType: PROC [design: Design, childTypeA: REF ANY] RETURNS [bag: Bag]; FirstCellType: PROC [design: Design] RETURNS [ct: CellType]; NextCellType: PROC [prev: CellType] RETURNS [next: CellType]; END. tCompareTransforms.Mesa Last Edited by: Spreitzer, January 10, 1985 11:57:34 am PST You get two tries. Ports after portIndex are not yet filled in. The EquivClasses are significant for CellTypes and Ports, but not for Vertices. = ReNameByName[MapRopePairs[pairs]] For enumerating the CellTypes of a Design. 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