(CellTypeName "PassBlock")
(Ports
	("input[0]" (G D))
	("input[1]" (G D))
	("input[2]" (G D))
	("input[3]" (G D))
	("gate" (G D))
	("output[0]" (G D))
	("output[1]" (G D))
	("output[2]" (G D))
	("output[3]" (G D)))
(PrivateFollows)
(N "gate" (G D) (A "sGate" (G P)))
(N "input[0]" (G D) (A "in[0]" (G P)) (A "sin[0]" (G P)))
(N "input[1]" (G D) (A "in[1]" (G P)) (A "sin[1]" (G P)))
(N "input[2]" (G D) (A "in[2]" (G P)) (A "sin[2]" (G P)))
(N "input[3]" (G D) (A "in[3]" (G P)) (A "sin[3]" (G P)))
(N "output[0]" (G D) (A "out[0]" (G P)) (A "sout[0]" (G P)))
(N "output[1]" (G D) (A "out[1]" (G P)) (A "sout[1]" (G P)))
(N "output[2]" (G D) (A "out[2]" (G P)) (A "sout[2]" (G P)))
(N "output[3]" (G D) (A "out[3]" (G P)) (A "sout[3]" (G P)))
(PN "input[0]" "input[0]")
(PN "input[1]" "input[1]")
(PN "input[2]" "input[2]")
(PN "input[3]" "input[3]")
(PN "gate" "gate")
(PN "output[0]" "output[0]")
(PN "output[1]" "output[1]")
(PN "output[2]" "output[2]")
(PN "output[3]" "output[3]")
(CI "pass[0]" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: TRUE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "gate")
	("ch1" "input[0]")
	("ch2" "output[0]")))
(CI "pass[1]" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: TRUE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "gate")
	("ch1" "input[1]")
	("ch2" "output[1]")))
(CI "pass[2]" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: TRUE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "gate")
	("ch1" "input[2]")
	("ch2" "output[2]")))
(CI "pass[3]" "Transistor[strength: drive, positive: TRUE, mode: Enhancement, unidirectional: TRUE, biased: FALSE, offStrength: none]" (G D) (CIC
	("gate" "gate")
	("ch1" "input[3]")
	("ch2" "output[3]")))